JPS60223221A - ジヨセフソン効果を用いたタイミング信号発生回路 - Google Patents

ジヨセフソン効果を用いたタイミング信号発生回路

Info

Publication number
JPS60223221A
JPS60223221A JP59078963A JP7896384A JPS60223221A JP S60223221 A JPS60223221 A JP S60223221A JP 59078963 A JP59078963 A JP 59078963A JP 7896384 A JP7896384 A JP 7896384A JP S60223221 A JPS60223221 A JP S60223221A
Authority
JP
Japan
Prior art keywords
circuit
logic
input
timing signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59078963A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0535610B2 (enExample
Inventor
Junichi Sone
曽根 純一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59078963A priority Critical patent/JPS60223221A/ja
Publication of JPS60223221A publication Critical patent/JPS60223221A/ja
Publication of JPH0535610B2 publication Critical patent/JPH0535610B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
JP59078963A 1984-04-19 1984-04-19 ジヨセフソン効果を用いたタイミング信号発生回路 Granted JPS60223221A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59078963A JPS60223221A (ja) 1984-04-19 1984-04-19 ジヨセフソン効果を用いたタイミング信号発生回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59078963A JPS60223221A (ja) 1984-04-19 1984-04-19 ジヨセフソン効果を用いたタイミング信号発生回路

Publications (2)

Publication Number Publication Date
JPS60223221A true JPS60223221A (ja) 1985-11-07
JPH0535610B2 JPH0535610B2 (enExample) 1993-05-27

Family

ID=13676546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59078963A Granted JPS60223221A (ja) 1984-04-19 1984-04-19 ジヨセフソン効果を用いたタイミング信号発生回路

Country Status (1)

Country Link
JP (1) JPS60223221A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233242A (en) * 1991-08-14 1993-08-03 Westinghouse Electric Corp. Superconducting push-pull flux quantum gate array cells

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233242A (en) * 1991-08-14 1993-08-03 Westinghouse Electric Corp. Superconducting push-pull flux quantum gate array cells

Also Published As

Publication number Publication date
JPH0535610B2 (enExample) 1993-05-27

Similar Documents

Publication Publication Date Title
US10103736B1 (en) Four-input Josephson gates
CA1257344A (en) Dual domino cmos logic circuit, including complementary vectorization and integration
US5670898A (en) Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance
JPH0233174B2 (enExample)
AU2018364955A1 (en) Large fan-in RQL gates
KR20200102503A (ko) Rql 다수결 게이트들, and 게이트들, 및 or 게이트들
US4749886A (en) Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate
TW200410131A (en) Apparatus and method for converting, and adder circuit
JPS60223221A (ja) ジヨセフソン効果を用いたタイミング信号発生回路
JP2023002458A (ja) 超伝導排他的論理和(xor)ゲートシステム
JP2540794B2 (ja) プログラマブルロジツクアレイ回路
US5951631A (en) Carry lookahead adder
JPH11143686A (ja) 部分積生成回路
Pandey et al. A PFSCL based configurable logic block
JPH02124627A (ja) クロックドライバー回路
Himabindu et al. Design of area and power efficient full adder in 180nm
JPS60198920A (ja) インタ−フエイス回路
JPH08139379A (ja) 超伝導論理ゲート段のシミュレーション用回路モデル
JPH0430767B2 (enExample)
US7215142B1 (en) Multi-stage inverse toggle
Akl et al. Feedback-switch logic (fsl): A high-speed low-power differential dynamic-like static cmos circuit family
JP3485854B2 (ja) 関数機能再構成可能な集積回路
JP2564300B2 (ja) ダイナミツク型フリツプフロツプ
KR950007464B1 (ko) 전가산기
Lin et al. Practical realization of multiple-input exclusive-OR circuits for low-power applications