JPS60222861A - Detection of position - Google Patents

Abstract

PURPOSE:To enable detection of the mark position with a high detection rate and high accuracy by using alignment marks of which the integrated density distribution has plural peak values so that binary coding processing can deal with many kinds of wafers as well. CONSTITUTION:Integration of data in a direction X and a direction Y is executed by the hardware of a TV prealignment detecting circuit which executes addition and stores the result thereof into memories 36, 40. Random noises are averaged by the addition and S/N is improved. The set value of a slicing level is determined by a mu processor which accesses the contents of the memories 36, 40, determines the difference (peak value) between the max. value and min. value thereof and sets, for example, 50% as the slicing level. The matching of the actual mark width and the detection pattern is processed. The alignment marks of any kind and state of wafers are exactly detected and the position thereof is measured by using the alignment marks of which the integrated density distribution has the plural peak values.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an apparatus for detecting the position of a pattern on an object to be inspected.
The present invention relates to a method for accurately detecting a pattern position from an image signal obtained by imaging with an imaging means such as a television camera or CCD when aligning a reticle (or a reticle).

[Prior art]

2. Description of the Related Art Conventionally, it has been widely known that when detecting the position of a certain mark in a semiconductor printing apparatus, an output signal of the mark obtained by an imaging means is binarized.

However, the output signal varies depending on the type of wafer on which the mark is formed or the size of the step, and the binarization process often cannot cope with the variation. Therefore, it is possible to detect a pattern different from the mark,
Alternatively, there is a drawback that the detection rate ITf is determined to be low even though the mark is present in the detection field of view.

[Purpose of the invention]

The present invention has been proposed in view of the above-mentioned drawbacks, and by using an alignment mark whose integrated concentration distribution has multiple peak values, the present invention enables binarization processing to be applied to various types of wafers, and achieves a high detection rate. The purpose of this paper is to provide a highly accurate mark position detection method.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. First, the overall configuration will be outlined with reference to Figure 881, which depicts the external appearance.

l is a mask with an integrated circuit pattern and other mask setting marks and fine alignment marks. 2 is a mask chunk that holds mask 1 and moves mask l in the plane and in the rotational direction. 3 is a reduction projection lens, 4 is a wafer provided with a photosensitive layer, and is provided with a fine fist alignment mark and a pre-alignment mark. 5 is a wafer or a stage. The wafer stage 5 holds the wafer 4 and moves it in the plane and in the rotational direction, and also moves between the wafer printing position (within the projection field) and the television pre-alignment position.

6 is an objective lens of a television pre-alignment river detection device, 7 is an image pickup tube or solid-state image sensor, and 8 is a television receiver for video observation. A binocular unit 9 is useful for observing the surface of the wafer 4 through the projection lens 3.

IO is an upper unit that houses an illumination optical system for converging the mask illumination light emitted from the light source 10a and a detection device for fine alignment.

The wafer stage 5 holds the wafer transported by a wafer transport means (not shown) at a predetermined position, and first moves to a position where the alignment mark on the wafer is within the field of view of the objective lens 6 for television prealignment. The positional accuracy at this time is due to mechanical prealignment accuracy, and the field of view of the objective lens 6 is approximately the diameter I.
It is about s rin to 2 mm. Alignment within this field of view
The mark is detected by the image pickup tube 7, and the coordinate position of the 7 alignment mark within the television pre-alignment field of view is detected. On the other hand, since the detection position for auto-alignment of the projection optical system and the position of the origin in the TV pre-alignment field mentioned above are set in advance, the auto-alignment position can be determined from these two points and the coordinate position of the TV pre-alignment mark. The amount by which the wafer stage 5 is fed is determined.

The position detection accuracy of the television pre-alignment is less than ±5, and even when taking into account the error caused by the movement of the wafer stage from the television pre-alignment position to the fine alignment position, it is about ±10 AL. Therefore, fine alignment only needs to be performed within a range of approximately ±10, which is 10% of the field of view of conventional fine alignment.
/100 or less, which means that fine alignment can be performed faster than before.

FIG. 2 shows an embodiment of the detection device for television pre-alignment, in which the reduction projection lens 3, wafer 4,
The objective lens 6 and image pickup tube 7 are the same as in FIG.

On the other hand, 11 is a light source for illumination, and uses a halogen lamp, for example. 12 is a condenser lens. 13A! l:1
3B is a bright field diaphragm and a dark field diaphragm that can be attached and detached interchangeably.
In the figure, a bright field diaphragm 13A is installed in the optical path. A condenser lens 12 images the light source 11 onto a bright field aperture. 14 is a relay lens for lighting. A cemented prism 15 has a function of making the optical axis of the illumination system and the optical axis of the light receiving system coaxial, and includes an inner reflective surface 15a and a semi-transparent reflective surface 15b. Here, the light source 11, condenser lens 12, bright or dark field diaphragms 13A and 13B, illumination relay lens 14, cemented prism 15, and objective lens 6 constitute an illumination system, and the light beam emitted from the objective lens 6 illuminates the wafer 6-t. Use epi-illumination.

Next, 16 is a relay lens, 17 is a mirror that bends the optical path, 1
Reference numeral 9 denotes an imaging lens, which includes the above-mentioned cemented prism 5, relay lens 16, mirror 17, imaging lens 19, and imaging tube 7.
The optical path passing through the objective lens 6 is reflected by the inner reflective surface 15a of the cemented prism and forms a semi-transparent surface 15b.
, and is reflected again by the inner reflective surface 15 a toward the relay lens 16 . A pre-alignment mark image on the wafer 4, which will be described later, is formed on the imaging surface of the imaging tube 7.

In addition, we will discuss the detection function of the pre-alignment mark.
Electrical processing of the detected video signal will be described later. The light flux from the illumination light source 11 is converged by the condenser lens 12, illuminates the aperture of the bright field diaphragm 13A or the dark field diaphragm 13B, further passes through the illumination relay lens 14, and is transmitted through the semi-transparent surface 15b of the cemented prism. The light is reflected by the reflective surface 15a and passes through the objective lens 6 to illuminate the wafer 4.

The light beam reflected on the surface of the wafer 4 is subjected to an imaging action by the objective lens 6, and enters the cemented prism 15, where it is reflected on the reflecting surface 15a.
Then, it is reflected by the semi-transparent surface 15b and the reflective surface 15a, and then emitted, relayed by the relay lens 16, reflected by the mirror 17, and imaged by the imaging lens 19 onto the imaging tube 7.

Next, the state is switched to a dark field state so that the pre-alignment mark image can be clearly seen, and the image is captured to detect the position of the pre-alignment mark image. The wafer fist stage 5 moves and stops so that the wafer 4 occupies a predetermined position 4' of the projection lens 3 in accordance with the position of the pre-alignment mark detected by electrical processing to be described later. Note that the wafer 4 may be once aligned at the standard position and then deformed so as to be moved to the projection field.

FIG. 3 is a block diagram showing one embodiment of a television pre-alignment detection circuit.

There are various methods for detecting the television pre-alignment mark shown in FIG. 5A, which will be described later, but the embodiment shown in FIG.
direction (horizontal direction) and Y direction (vertical direction), respectively.
It is added. The advantages of addition are: (1) Addition averages out random fist noise and improves the S/N ratio.

■Position detection in the X direction and Y direction can be performed independently, making detection easier. For example, the memory capacity for storing 0 image data becomes smaller.

Block X surrounded by a broken line in the block diagram of Figure 3
is a block that adds the density of pixels in the X direction, and block Y is a block that adds the density of pixels in the Y direction.

In FIG. 3, 31 is a video amplifier, 32 is an analog-to-digital converter, and 33 is a latch. The video signal sent from the television camera control section (B in FIG. 3) is amplified by the video amplifier 31, and then converted into an analog-to-digital converter. After being digitized by the converter 32, it is stored in the latch 33. The output data of the latch 33 is output to an addition block X in the X direction and an addition block Y in the Y direction. In block Y, 34 is an adder that adds data in the Y direction, 35 is an addition output latch that latches the output data of the adder 34, 36 is a Y-direction integration memory that stores the data of the addition output latch 35, and 37 is a memory 36 This is an addition manual latch that latches the output data of .

In block X, 38 is an adder that adds data in the X direction, 38 is a latch that latches the output of the adder on the third day,
Reference numeral 40 denotes an X-direction integration memory that stores the output data of the latch 39. Although there is no particular limitation on the number of bits of digital data in these circuits, for example, the analog-to-digital converter 32 has an 8-bit configuration, and the adder 34, 38 and memory 36, 40 have a 16-pin configuration.

On the other hand, 41 is a sequence and memory control circuit that controls the timing and sequence of the television pre-alignment detection circuit, as well as read/write and chip select of the memory 36, and 42 is a memory control circuit that controls the memory 40 in block X. It is a circuit. 43 is a control register for a microprocessor (not shown) to control the sequence and memory control circuit 41, and the input of the register is connected to the data bus 44 of the microprocessor. The microprocessor also connects the memory 3 via this data bus 44.
6.40 can be accessed. 45.46
．． 47.48 are buffers for that purpose, buffer 4
5.47 operates when the microprocessor writes data to the memory, and buffers 46.48 operate when reading data. 48 is a clock circuit, and 50.51 is a memory e-write address circuit and a memory read address circuit that generate write addresses and read addresses for the X-direction accumulation memory 36. 52 is an address selector that switches between the memory read address and the write φ address, and 53 is an address buffer when the microprocessor accesses the memory 3B.
The output of bar and fa 53 is selected, and the output of bar and fa 53 is prohibited. 54 is a memory address circuit that generates the address of the X-direction integration memory 40, and 55 is an address selector that switches between the address of the memory address circuit 54 and the address generated when the microcomputer accesses the memory 40.

56 is a TV synchronization signal generation circuit that generates a TV water synchronization signal, vertical synchronization signal, blanking signal, etc. based on the clock of the clock circuit 48. 57 and 58 are connected to the data bus 44 of the microcomputer, respectively;
An X position display register, a Y position display register 58 is a marker display circuit, and the microprocessor outputs the position of the alignment mark detected in the TV pre-alignment to the X position display register 57 and the Y position display register 58. The marker display circuit 59 sends the mixed signal to the video input terminal of the TV camera control section.

Next, the function and operation of the television pre-alignment circuit shown in FIG. 3 will be explained.

The functions of the television pre-alignment detection circuit are: (1) integration of data in the X direction, (2) integration of data in the Y direction, and (2) display of the pre-alignment mark detection position on the TV monitor. Among these, the integration of data in the X direction and the integration of data in the Y direction are performed by the hardware of the television Φ prealignment detection circuit, and the added data is stored in the memory.

Data addition is done in units of one frame of the TV signal,
As will be described later, the addition of one frame may be completed as necessary, or the addition of a plurality of frames may be performed.

In either case, during addition, the data and address buses of memory 36, 40 are electrically isolated from the data and address buses of the microprocessor, and the addresses of memory 36 are connected to the address selector. 52, the address of the memory 40 is connected to the address of the address selector circuit 55, and the sequence and memory control circuit 41. The addition is executed under the control of a read/write signal and a chip select signal generated by hardware from the memory control circuit 42.

When the addition of a predetermined number of frames is completed, the sequence and memory control circuit 41 connects the interconnected signal line I.
An end of addition signal is generated on NT. After the addition completion signal is generated, the microprocessor accesses the memory 36 and the memory 40 and detects the television pre-alignment mark position from the addition data. When the microprocessor accesses the memory 36, 40, the memory address, read/write signal, chip select signal, etc. are naturally controlled by control signals from the microcomputer. Further, data in the memory 36 is transferred to a buffer 4B, and data in the memory 40 is transferred to a data bus 44 via a buffer 48.
and read by the microprocessor.

By the way, addition in the X direction in block X in FIG.
Before explaining addition in the Y direction in block Y, a pixel division method will be described with reference to FIG. FIG. 4 shows pixels in which a television screen is divided into N parts in the X direction and M parts in the Y direction. Pixel Pli indicates the pixel in the i-th row and i-th column. The number of divisions M in the Y direction usually matches the number of horizontal scanning lines. Therefore, in order to divide into pixels, an analog-to-digital converter (third
Sampling may be performed N times as shown in FIG. 32).

Therefore, addition in the X direction is S XI = D A T A (P o ) + D
AT A (P 12 ) +------+D
AT A (PIN).

S×2=DATA (P2.)+DATA (P22)
＋−−−−−−+DATA(P2N),
Syu = D A T A (P Ml ) + D A
T A (P M2) +-------+ D A
T A (P P?1), addition in the Y direction is SY, = DATA (P,,) + DATA (P2.)
+-------10D AT A (P M□), 5Y
2='DATA (PI2)+DATA (P22)+
−−−−−−+ D A T A (P, 2), S
vw = DA TA (PIN) + DA
T A (P 2N) +−−−−−−+ D A T
A (P MN ).

When the addition is completed, S is stored in the X direction integration memory 40.
The data of XI, S x2---S , , Y
In the direction integration memory 36, S Yl, S Y2--
---8YN data is stored.

Next, a method of determining the authenticity of an alignment mark by determining the signal width according to an embodiment of the present invention and detecting the position of the alignment mark will be described.

In order to clarify the content of the embodiment, a conventional example will be explained first. The conventional TV alignment mark illustrated in FIG. 5(A) is either provided within the scribe line of the wafer or at a specific chip pattern position on the wafer. The cross-shaped marks provided are arranged so that the direction of the cross pattern is substantially parallel and perpendicular to the scanning direction of the imaging tube.

In particular, the illustrated mark is composed of a collection of minute bar-like protrusions tilted at 45° in the scanning direction, and if illumination light hits these protrusions from a direction perpendicular to them, an extremely clear pattern shape can be imaged. It is something.

The density distribution when the density of this TV pre-alignment mark is integrated in the X and Y directions is shown in Figure 5 (B).
The result will be as shown in (C).

FIG. 5(B) shows the distribution of density in the Y direction when added in the X direction, and FIG. 5(C) shows the distribution of density in the X direction when added in the Y direction. Therefore, for example, in Fig. 5(C), if an appropriate slice level , the pattern shape center MX is given by MX=(MR-ML)/2.

Similarly in the Y direction, the center MY of the pattern is aligned, and these values become the center coordinates of the pre-alignment mark. The slice level setting value is determined by the microprocessor accessing the contents of the addition memory (Fig. 3 (3B, 40)), determining the difference (peak value) between the maximum value and the minimum value, and setting the slice level to 50, for example. It is determined by setting the value of % as the slice level.

By the way, a pattern of an actual element may be provided in the area around the pre-alignment mark shown in FIG. 5(A). Furthermore, depending on the mechanical pre-alignment accuracy of the wafer transport system, it is not always the case that only the alignment mark is captured within the field of view of the television image pickup tube. Therefore, it is conceivable that a pattern of an actual element is captured as the detection pattern, or that there is no pattern at all and the bias component is used as the detection pattern.

Therefore, it becomes necessary to determine whether or not the captured pattern is really an alignment mark. For this reason,
When using a mark as shown in Figure 5 (A) as an alignment mark, the actual mark width PM (Figure 5 (A))
When the detection pattern is binarized at a predetermined slice level, the width of the part that becomes "l", that is, the consistency with the value of MR-A, is used to judge whether the detection pattern is an alignment mark or not. (This will be referred to as matching processing.)

A specific example of what has been described above is shown in FIG. When some actual device pattern is captured together with the alignment mark as shown in FIG. 6(A), the added density data becomes as shown in FIG. 6(B) and (C). When binarization is performed with a predetermined slice level SLI in the X direction, a binarization pattern as shown in FIG. 6(D) is obtained. There are two parts that are "1", (1) and (2), but the difference between the actual mark width PM and each mark width of (1) and (2), that is, (XRI - XLI) - P
M, (XR2-XL2) Request, sono value is small (1
) is more likely to be an alignment mark,
Furthermore, it was checked whether the value was within a predetermined range, and if it was within the range, it was determined that it was an alignment mark.

Therefore, in FIG. 6(D), it is determined that the position of MXI is the center position of the alignment mark, and similarly, it can be determined that MYI is the center position in the Y direction as well.

By the way, in the actual semiconductor printing process, various wafers are used and the steps for forming alignment marks are not constant. Therefore, the detection pattern as shown in FIG. 6(A) may be changed to that shown in FIG. 7(B) depending on the type of wafer or its level difference.

In many cases, the S/N ratio becomes poor as shown in (C), and the binarization pattern in the X direction becomes as shown in FIG. 7(D). In such a case, in order to detect a more accurate position, it is insufficient to perform a matching process with the actual mark width PM, and if a pattern different from the alignment mark, such as an actual element, dust, etc. I conclude that it is.

Further, even when there is no mark, depending on the slice level setting value, the bias component may be binarized to have the same width as the actual mark width, which may cause false detection.

Therefore, a position detection method according to another embodiment of the present invention that takes this point into consideration will be described with reference to FIGS. 8 and 9. The present invention attempts to accurately detect the alignment mark and measure its position for any type or condition of the wafer by using an alignment mark whose cumulative concentration distribution has multiple peak values. be.

An example of the alignment mark of the present invention is a cross-shaped notch turn as shown in FIG. It is a mark that is cut out or left behind. Therefore, when this mark is illuminated, only the engraved and dented portions will have high brightness. Therefore, when the density of this mark is added in the X direction and the Y direction, the density distributions shown in FIGS. 8(B) and 8(C) are obtained.

A feature of the density distributions in FIGS. 8(B) and 8(C) is that, as is clear from the figures, there are two peak values for the alignment mark. When binarization is performed with an appropriate slice level SL2 in the X direction, Fig. 8(D)
become that way. The mark width in the X direction of this mark is the distance between the center positions of the two peak values, that is, XR3-XL3', as shown in Figure 8 (D).
The center of this pre-alignment mark in the x direction is given by NX2=(XR3-XL3)/2. MY2 is similarly rounded in the Y direction. When using this mark, if the type of sea urchin/\- or the size of the step is different,
For example, the gain of the video signal obtained is shown in Fig. 8(B), (
Suppose that it is smaller than C) and becomes as shown in FIGS. 9(B) and (C:). At this time, SL in the X direction
Even if the pattern when binarized with 3 as the slice level becomes as shown in Figure 9 (D), the mark width is the center position interval of the two peak values, that is, XR4-XL
4, so it is not much different from XR3-XL3 in FIG. 8(D).

Therefore, even if the type of wafer or the size of the step forming the mark changes, the width of the alignment mark can be measured as a constant value. Therefore, it becomes possible o) to distinguish the alignment mark from other patterns, and the mark center coordinates MX3 and MY3 in both the x and 7 directions can be determined.

Also, as mentioned above, when measuring the pre-alignment mark interval value, if it is derived as the interval between the center positions of the two peaks, the slice level setting range can be widened to some extent during the binarization process. Even if it is changed, the mark interval value does not change so much as to affect the matching process that follows, so that the appropriate setting of the slice level can be speeded up.

Next, a position detection method for determining the optimum slice level when measuring the position of the alignment mark shown in FIG. 8(A) according to still another embodiment of the present invention will be described. First, problems with the conventional method will be explained.

According to the conventional method, the added density data of the detection pattern is binarized into 0" and °1" with a certain slice level as the initial setting value, and the number of "1pa" parts measured at that time and the expected t ” (In the case of this mark, the number of parts shown in Figure 8 (
As is clear from D), the reference number is 2) for comparison. If the number of measurements is greater than the reference number, it is determined that the bias portion has been sliced, the slicing level is increased, and the measurement is performed again (see FIG. 10(A)).

■If the number of measurements was less than the reference number, it was determined that not all of the marked portion had been sliced, the slicing level was lowered, and the process was performed again (No. 10).
(see figure (B)).

However, if the S/N ratio of the video signal is small as shown in Fig. 1θ (C), the initial value of the slice level will be set around the /x value, and the number of l'' portions will be 1. In this case, if the binarization process sequence of the conventional method is followed, the slice level search direction will be incorrect.

Therefore, in consideration of the above points, the position according to the embodiment of the present invention is proposed in which the binarized data is judged not only from the viewpoint of the number of 1" parts but also from the viewpoint of the sum of the widths of the l"' parts. The detection method will be explained. The following detailed explanation will be given in accordance with the flowchart of FIG. 11. In step 6 111, when an addition start command is issued from the microprocessor, addition of the image signals in the X direction and the Y direction is started, respectively, as described above. The microprocessor waits in step 112 for the completion of addition, and when the addition of a predetermined number of frames is completed, the process proceeds to step 113. In step 113, the microprocessor searches for the maximum and minimum values of the image density data stored in the addition memory. The above-mentioned peak value is derived from these values, and in step 114, the initial value of the slice level is set at, for example, 50% of the peak value.

Next, in step 115, the slice level value and the contents of the addition memory are sequentially compared in size, and if the former is larger than the latter, it is converted to 0'', and vice versa, it is converted to 1''.

Conventionally, as the next step, as shown in 117, there is a process of measuring the number of 1pa and checking whether the value is within the allowable range.If it is outside the allowable range, the value is The next slice level is determined and re-measurement is performed. However, as described above, a malfunction occurs in the case as shown in FIG. 10(C).

Therefore, in the present invention, step 11 is performed before the above step.
A process of checking the sum of the signal widths of the "1" portion of G is executed. According to this process, in the case of FIG. 10(C), the sum of the signal widths of the "1" portion is outside the allowable range,
Further, in step 118, it is determined that the width is larger than the reference width, and it is possible to proceed to an appropriate process such as the slice level UP process in step 119. In addition, Fig. 10 (A)
In this case, since the signal width is still larger than the standard allowable width, the process proceeds to step 119, the slice level UP process. In the case of Fig. 10 (B), on the other hand, it is small, so step 1
The process proceeds to slice level DOWN processing at step 20.

As mentioned above, it is not the number of parts of l″, but “1”.
The search direction of the slice level is determined correctly by measuring the sum of the widths of the parts, so step 11 is performed again.
The processing time when returning to step 5 and re-measuring can be shortened.

If the slice level can be set so that the sum of the signal widths of the "i" part falls within the allowable range, the process proceeds to step 117 where the number of signals "1'" is checked. If so, the process proceeds to step 121, and it is determined whether the number of "l" signals is greater or less than the reference number. If it is greater than the reference number, the process proceeds to step 119 to increase the slice level, and if it is small, the process proceeds to step 120 to decrease the slice level.

If step 7 117 is also within the allowable range following step 1 IEi, for example, as described above, in the X direction, measure the mark width shown as (XR3-XL3) in FIG. 8. , it is determined whether or not the step is matched to the actual mark width. If it is determined that the detected mark is an alignment mark, the process proceeds from step 123 to step 124, where the center position of the mark is measured.

Further, if matching is not performed in step 122, it is determined that the mark is not an alignment mark, and step 125 is performed.
Proceed to. In this case, it is assumed that no alignment mark exists within the field of view, and the process proceeds to the process of searching for an alignment mark. By performing the above processing in the X and Y directions, it is possible to reliably and quickly determine whether the detected pattern is an alignment mark, and to accurately determine the center position coordinates.

[Effects of the Invention] As described above, according to the position detection method according to the present invention, the X coordinate of a mark can be determined from two-dimensional image data.

In a device that detects the Y coordinate, by using an alignment marker whose integrated density distribution has multiple peak values, the detection process can be performed accurately even for various types of wafers or differences in the steps forming marks. , and it is possible to do it quickly.

In addition, even if there is a pattern other than the alignment mark in the detection field of view, such as on an actual device, it is possible to accurately identify and measure the alignment mark, and even when the S/N ratio of the video signal is poor, the alignment mark can be detected even when the S/N ratio of the video signal is poor. can be detected and measured with high detection rate and high accuracy.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the external appearance of a printing apparatus according to an embodiment of the present invention, FIG. 2 is a perspective view of an optical system of a television pre-alignment detection system, and FIG. 3 is a block diagram of a television pre-alignment detection circuit. , FIG. 4 is a diagram for explaining the pixel division method of a television screen. Figure 5 (^) is a plan view when the image pickup tube captures only the conventional TV pre-alignment mark, (B),
(C) is a diagram showing the result of adding image signals in the X direction and the Y direction, respectively, and (D) is a diagram showing a binarized signal in the X direction. Figure 6 is the same as Figure 5, but is a diagram when the actual device pattern is also captured, and Figure 7 is a diagram of the 6th
This figure is similar to the figure, but when the S/N ratio of the signal is small. FIG. 8(A) is an f-plane view when the TV pre-alignment mark according to the embodiment of the present invention is captured, and FIG. 8(B) is
, (C) is a diagram showing the result of adding image signals in the X direction and Y direction, respectively, and (D) is a diagram showing the result of adding image signals in the X direction and 2 in the X direction.
It is a diagram converted into a valued signal. FIG. 9 is a diagram similar to FIG. 8, but when the S/N ratio is small. FIG. 10 is a diagram showing a state in which an integrated density value of a television pre-alignment mark and an optimum slice level are searched for in an embodiment of the present invention. FIG. 11 is a flowchart of a position detection method according to an embodiment of the present invention. 31...Video amplifier 32...An converter 3
3.35.37.39...Latch 34.38...Adder 38.40...Memory 41
...Sequence/memory control circuit 42...
Memory control circuit 43... Control register 44... Data bus 45 to 48.53.../<Tuff 48... Clock circuit 50... Memory write address circuit 51... Memory read address circuit 52. 55...Address selector 54...Memory address circuit 56...TV synchronization signal generation circuit 57...X position display register 58...Y position display register 59...Marker display circuit Y'j5↑ Figure 4 (D) Figure 5 Mlx. Figure 6 Figure 7 Figure M1x3 Figure 9 Figure 10

Claims (3)

[Claims] (1) A position detection mark having a plurality of signal peak values is imaged by an imaging means, two-dimensional image data obtained from the imaging means is integrated in the X direction and Y direction, and the integrated data is further binarized. A method for detecting a mark position by detecting a mark position by detecting a peak value of the integrated density, a first step of recognizing the presence of a position detection mark within the imaging field of view by detecting a peak value of the integrated density, determining a slice level from the peak value of the integrated density, A position detection method comprising: a second step of binarizing integrated density data; and a third step of detecting signal intervals of a plurality of signals to determine whether it is a predetermined position detection mark. (2) Image a position detection mark having a plurality of signal peak values using an imaging means, integrate the two-dimensional image data obtained from the imaging means in the X direction and the Y direction, and then binarize the integrated data. A method of detecting a mark position by detecting a mark position includes: a first step of recognizing the presence of a position detection mark within an imaging field of view by detecting a peak value of integrated density; determining a slice level from the peak value of one integrated density; A position detection method comprising: a second step of binarizing integrated density data; and a third step of detecting and adding each of a plurality of signal widths to determine whether it is a predetermined position detection mark. (3) Image a position detection mark having a plurality of signal peak values using the imaging means, integrate the two-dimensional image data obtained from the imaging means in the X direction and the Y direction, and then binarize the integrated data. A method for detecting a mark position by detecting a mark position by detecting a peak value of the integrated density, a first step of recognizing the presence of a position detection mark within the imaging field of view by detecting a peak value of the integrated density, determining a slice level from the peak value of the integrated density, The positioning process consists of a second step of binarizing the integrated density data, and a third step of determining whether or not it is a predetermined position detection mark by detecting the signal intervals of multiple signals and the signal widths of multiple signals. Detection method.