JPS60221877A - Arithmetic unit of figure - Google Patents

Arithmetic unit of figure

Info

Publication number
JPS60221877A
JPS60221877A JP7653684A JP7653684A JPS60221877A JP S60221877 A JPS60221877 A JP S60221877A JP 7653684 A JP7653684 A JP 7653684A JP 7653684 A JP7653684 A JP 7653684A JP S60221877 A JPS60221877 A JP S60221877A
Authority
JP
Japan
Prior art keywords
memory elements
coordinates
memory element
rectangle
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7653684A
Other languages
Japanese (ja)
Inventor
Masaharu Hirayama
正治 平山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7653684A priority Critical patent/JPS60221877A/en
Publication of JPS60221877A publication Critical patent/JPS60221877A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To accelerate substantially checking of overlapping of figures by holding coordinate position information of two and more rectangles and by performing simultaneously the figure arithmetic with respect to each figure data by means of a full function memory element. CONSTITUTION:Plural function memory elements 711-7nn are constituted of two pieces of one bit memory elements 16a and 16b and one bit arithmetic unit 17 as a main component. X and Y address control circuits 5 and 6 input addresses of two points on coordinates, output an address selection signal with respect to the whole area held by coordinates, while X and Y direction registers 8 and 9 hold an OR summed up by contents of the memory elements 711-7nn arrayed two-dimensionally in row and column directions. Coordinate data is written in the memory elements of the function memory elements selected by the circuits 5 and 6 out of the memory elements 711-7nn, and coordainte position information of two and more rectangles is held. The figure arithmetic is simultaneously performed with the aid of a full function memory element.

Description

【発明の詳細な説明】 〔発明の技術分野〕 1 この発明は個々の図形要素が矩形で宍現される図形
に対する演算を行なう図形演算装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] 1. The present invention relates to a graphic calculation device that performs calculations on a graphic whose individual graphic elements are represented by rectangles.

〔従来技術〕[Prior art]

従来この種の図形演算装置としては第1図に示すものが
あった。以下は図形演算の中で複数の矩形に負なり合う
部分があるか否かを判定する図形演算装置を例にして説
明する。第1図において、11〜14はそれぞれ矩形l
の始点、終点、矩形2の始点、終点の(X y)座標を
格納するレジスタ、21〜24は2つの座標値を入力し
てその大小を判定する比較器、31〜34は前記比較器
21〜24によって比較した結果を示す比較出力、4は
前記比較出力31〜34の全体の論理積をとった重aフ
ラグである。
A conventional graphic arithmetic device of this type is shown in FIG. In the following, a graphic arithmetic device that determines whether or not a plurality of rectangles have mutually negative portions in a graphic arithmetic operation will be described as an example. In FIG. 1, 11 to 14 each represent a rectangle l.
21 to 24 are comparators that input two coordinate values and determine their magnitude; 31 to 34 are the comparators 21; -24 is a comparison output indicating the comparison result, and 4 is a multi-a flag obtained by taking the AND of all the comparison outputs 31-34.

次に第1図の動作について以下に説明する。ここで各固
形要素は始点と終点のCX−y) II標で衣わされる
矩形であるとし、終点のx、yMk標ともそれぞれ始点
のx、y座標よシも大きいとする。2つの矩形間で重な
シあう部分があるかどうかの演算を行なう場合、矩形1
の始点、終点の(x−y)座標はレジスタ11.12に
また、矩形2の始点。
Next, the operation shown in FIG. 1 will be explained below. Here, it is assumed that each solid element is a rectangle surrounded by CX-y) II marks at the start point and the end point, and the x and yMk marks at the end point are each larger than the x and y coordinates of the start point. When calculating whether there is an overlapping portion between two rectangles, rectangle 1
The (x-y) coordinates of the starting point and ending point of rectangle 2 are also stored in registers 11 and 12.

終点の(x−y)座標はレジスタ13.14に格納され
る。矩形lと矩形2とが京なルあり部分をもつための条
件は矩形2の終点の1,7座標とも、それぞれ矩形lの
始点のX、7座標よりも大きく、かつ、矩形lの終点の
1,7座標は、それぞれ矩形2の始点のx、y座標よシ
も大きい事になる。
The (x-y) coordinates of the end point are stored in register 13.14. The conditions for rectangle l and rectangle 2 to have a quadrature square part are that the 1st and 7th coordinates of the end point of rectangle 2 are larger than the X and 7 coordinates of the start point of rectangle l, respectively, and the end point of rectangle l is The 1st and 7th coordinates are also larger than the x and y coordinates of the starting point of rectangle 2, respectively.

上記の各X、7座標の位置を演算で確認するために、4
個の比較器21〜24に各矩形の始点及び終点の!、7
座標を入力して比較演算を行なう。
In order to confirm the position of each of the above X, 7 coordinates by calculation, 4
The starting point and ending point of each rectangle are input to the comparators 21 to 24! ,7
Input coordinates and perform comparison calculations.

その結果、上記の条件を満足した場合に各比較出力31
〜34がそれぞれ真の状態を示し、前記4個の比較出力
31〜34の論理積を重複フラグ4とすれば、この重複
フラグの真偽によって矩形1と矩形2に重複があったか
否かを判定できることになる。
As a result, if the above conditions are satisfied, each comparison output 31
34 respectively indicate a true state, and the logical product of the four comparison outputs 31 to 34 is set as the overlap flag 4, it is determined whether there is an overlap between rectangle 1 and rectangle 2 based on the truth or falsehood of this overlap flag. It will be possible.

以上のように従来の図形演算装置では2つの矩形の重な
シを判定するためには、それぞれの始点。
As described above, in conventional graphic arithmetic devices, in order to determine whether two rectangles overlap, each starting point is used.

終点の(x−y)座標をレジスタに入力し、4個の比較
演算を行ない、その結果をまとめる事によって矩形の重
な)判定を行なってまたため、k個の矩形データが互い
に重複する部分があるかどうかを判定するためには、上
記の判定処理をに7回行なう必要があシ、矩形データに
の値が大きい時には膨大な判定時間を必要とするという
欠点があった。
Input the (x-y) coordinates of the end point into the register, perform four comparison operations, and summarize the results to determine if the rectangles overlap. In order to determine whether or not there is, it is necessary to perform the above-mentioned determination process seven times, and when the value of the rectangular data is large, a huge amount of determination time is required.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、各1ピツトの記憶能力をもつ2次
元配列メモリを2面有し、図形要素の始点、および終点
の(x−y)座標を与えることによって、座標に対応す
るメモリ部分への書込みを行なう機能と、2つの2次元
配列メそりの対応するlビットに対するビット処理能力
を付加することによシ、図形要素間の′xLaのチェッ
クや各種の図形演算を行なう図形演算装置を提供するこ
とを目的としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and has two two-dimensional array memories each having a storage capacity of one pit. y) By adding the function of writing to the memory part corresponding to the coordinates by giving the coordinates and the bit processing capacity for the corresponding l bits of two two-dimensional array arrays, it is possible to write between graphic elements. It is an object of the present invention to provide a graphic arithmetic device that checks 'xLa and performs various graphic arithmetic operations.

〔発明の実施例〕[Embodiments of the invention]

以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

図中、第1図と同一の部分は同一の符号をもって図示し
た第2図において、Is、16はそれぞれ矩形の始点、
終点のX座標、および始点、終点の1座標を格納するレ
ジスタ、5は2つのX座標を入力しこの2つのX座標値
にはさまれる領域に対するXアドレス選択信号を出力す
るXアドレス制御回路、6は2つのy座標を入力しこの
2つの1座標値にはさまれる領域に対するYアドレス選
択信号を出力するYアドレス制御回路、111〜7nn
紘機能メモリ素子、8鉱機能メモリ素子711〜″7n
nからのX方向に伝搬されるデータを保持するためのX
方向レジスタ、9は機能メ七す素子111〜7nnから
のY方向に伝搬されるデータを保持するためのY方向レ
ジスタ、10は機能メモリ中にある2つの記憶素子のい
ずれかを相愛するメモリ選択線、1lla〜11n& 
は機能メモリ中にある記憶素子のA側メモリのX方向ア
ドレスを決定するためのX人アドレス選択線、111b
〜11mbは機能メモリ中にある記憶素子のB側メそす
のX方向アドレスを決定するためのXBアドレス選択線
、121〜12mは機能メモリ中にある記憶素子のY方
向アドレスを決定するYアドレス選択線、1301〜1
3El11は簿能メモリ素子711〜7nnからY方向
にデータを伝えるためのXデータ伝搬線、1410〜1
わ■は機能メモリ素子111〜7nnからX方向にデ\
−夕を伝えるためのYデータ伝搬線、15Aは機能メそ
す711〜7nn(DhJJ作を制御する機能指定線で
ある。また、第3図において、71jは1行j列目にあ
る機能メモリを示し、11,16bは各1ピツトずつの
記憶素子、171i2つの1ビツト入力を受付け、各種
の演算を行なって1ピツトの出力を発生するビット演算
器、1liaはXAアドレス選択線、111bはXBア
ドレス選択緑、12jaYアドレス選択線、13(1−
1)J、 131jはXデータ伝搬線、141(J−1
)、 141JはYデータ伝搬線、151〜154は機
能指定線でそれぞれ、リセット腺2人書込み線、8畳込
み線、演算機能指定線である。
In FIG. 2, the same parts as in FIG.
A register that stores the X coordinate of the end point and one coordinate of the start point and the end point; 5 is an X address control circuit that inputs two X coordinates and outputs an X address selection signal for the area sandwiched between the two X coordinate values; 6 is a Y address control circuit that inputs two y coordinates and outputs a Y address selection signal for the area sandwiched between the two 1 coordinate values; 111 to 7nn;
Hiro functional memory element, 8-mine functional memory element 711~''7n
X to hold data propagated in the X direction from n
A direction register 9 is a Y direction register for holding data propagated in the Y direction from the functional elements 111 to 7nn, and 10 is a memory selection for selecting either of the two storage elements in the functional memory. Line, 1lla~11n&
111b is an X-person address selection line for determining the X-direction address of the A-side memory of the storage element in the functional memory;
~11mb is an XB address selection line for determining the X-direction address of the B-side memory of the storage element in the functional memory, and 121-12m is a Y address for determining the Y-direction address of the storage element in the functional memory. Selection line, 1301-1
3El11 is an X data propagation line for transmitting data from memory elements 711 to 7nn in the Y direction, 1410 to 1
wa■ is the direction from the functional memory elements 111 to 7nn in the X direction.
-Y data propagation line 15A is a function designation line for controlling the function memory 711 to 7nn (DhJJ production). , 11 and 16b are storage elements each having one pit, 171i is a bit arithmetic unit that accepts two 1-bit inputs, performs various operations and generates a 1-bit output, 1lia is an XA address selection line, and 111b is an XB Address selection green, 12jaY address selection line, 13(1-
1) J, 131j is the X data propagation line, 141 (J-1
), 141J is a Y data propagation line, and 151 to 154 are function designation lines, which are a reset gland two-person write line, an 8-convolution line, and an arithmetic function designation line, respectively.

次に第2崗及び第3図に示す図形演算装置の動作につい
て説明する。ここ゛で各図形要素は矩形の始点と終点の
(x−y)座標であられされ、そのX。
Next, the operation of the graphic arithmetic device shown in the second embodiment and FIG. 3 will be explained. Here, each graphic element is represented by the (x-y) coordinates of the starting point and ending point of the rectangle, and its X.

y値は図形演算装置に含まれる機能メモリ集子の個数に
対応して1からntでの値をとるものとする。動作の開
始に先立って、リセット線151によって全機能メモリ
素子711〜7nn中の2つの記憶素子16a、16b
はすべてリセットしておく。2つの矩形間で重なシアう
部分があるがどうかの演算を行なう場合、まず最初の矩
形に対する始点、終点の(x−y)座標をレジスタ15
.16にロードする。これらのx、y座標値はそれぞれ
Xアドレス制御回路5、Yアドレス制御回路6に転送さ
れ、各x、y座標の始点、終点にはさまれる領域に対応
するXA、XB及びYアドレス選択線111a 〜1l
na t 111b 〜l1nb + 121〜12n
が真の値をとる。但し、この時、Xアドレス制御回路5
に転送されているメモリ選択線1oの値に応じてXAア
ドレス選択m 1t1a〜11na 、またはXBアド
レス選択線111b〜1lnbのいずれが≠(選択され
る。夫々3組のアドレス選択線とも同行、同列の機能メ
モリ素子111〜7nnに対しては同一の信号線によっ
て接続されているため、入力された矩形の始点、終点の
座標に対応するすべての機能メそす素子71JはX方向
のアドレス選択k 111a 〜11naまたは111
b 〜11nbとYアドレス選択線121〜12nの両
方が真の値となシ、この結果、機能メモリTlj内のア
ドレス選択線に対する論理積回路によって2個ある1ピ
ット記憶素子16a、15bのいずれかがセットされる
。たとえは矩形の始点、終点の座標が(3゜s) + 
(617)でメモリ選択線10がA面を指定している時
、12組の機能メモリ素子735,736゜737’、
745,746,747,755,756゜757.7
65,766.767が前記XA、XB。
It is assumed that the y value takes a value from 1 to nt corresponding to the number of functional memory collections included in the graphic processing device. Prior to the start of operation, two storage elements 16a, 16b among the full-function memory elements 711-7nn are activated by the reset line 151.
Reset everything. When calculating whether there is an overlapping shearing part between two rectangles, first store the (x-y) coordinates of the starting point and ending point for the first rectangle in register 15.
.. 16. These x, y coordinate values are transferred to the X address control circuit 5 and Y address control circuit 6, respectively, and the XA, XB, and Y address selection lines 111a corresponding to the areas sandwiched between the starting point and ending point of each x, y coordinate are transferred. ~1l
na t 111b ~ l1nb + 121 ~ 12n
takes a true value. However, at this time, the X address control circuit 5
Depending on the value of the memory selection line 1o transferred to the Since the functional memory elements 111 to 7nn are connected by the same signal line, all the functional memory elements 71J corresponding to the coordinates of the input rectangular start and end points are connected to the address selection k in the X direction. 111a to 11na or 111
b ~ 11nb and the Y address selection lines 121 ~ 12n are both true values, and as a result, the AND circuit for the address selection lines in the functional memory Tlj selects either one of the two 1-pit storage elements 16a, 15b. is set. For example, the coordinates of the starting point and ending point of a rectangle are (3°s) +
When the memory selection line 10 specifies the A side in (617), 12 sets of functional memory elements 735, 736° 737',
745,746,747,755,756°757.7
65,766.767 are the above XA and XB.

Yの各アドレス選択線によって選択され、前記機能メモ
リ素子135〜767の中のAltllの記憶素子1e
aがセットされる。次に2番目の矩形に対しても同様に
始点、終点の座標をレジスタ15゜16に入力し、この
座標に対応するすべての機能メモリ素子71Jを選択す
る。この時、メモリ選択線10に最初のものと異なる値
をセットする事によシ、機能メモリ素子71j中の使用
していない方の記憶素子16bをセットする拳ができる
The memory element 1e of Altll among the functional memory elements 135 to 767 is selected by each address selection line of Y.
a is set. Next, the coordinates of the start point and end point of the second rectangle are similarly input into the registers 15 and 16, and all functional memory elements 71J corresponding to these coordinates are selected. At this time, by setting a value different from the first value to the memory selection line 10, it is possible to set the unused memory element 16b among the functional memory elements 71j.

以上の動作により矩形lに対応する図形は機能メモリ素
子71jOA側記憶累子16&に、また他の矩形2に対
してii、B側記憶素子16bにビット対応に記憶され
ているため、この図形演算装置の全機能メそす素子11
1〜7nnに対して、演算機能指定線154に論理積、
Big−込み線に真を指定して機能メモリ索子′111
〜7nnのピット演算器11を動作させる事によシ、A
側記憶素子16aの内容とB111l記憶素子16bの
内容との論理積をとった結果をB側記憶素子16bにセ
ットする。
As a result of the above operations, the figure corresponding to the rectangle 1 is stored in the functional memory element 71j, the OA side storage element 16&, and for the other rectangle 2, ii, and the B side storage element 16b, in a bit-corresponding manner. Element 11 for all functions of the device
For 1 to 7nn, logical product is applied to the arithmetic function designation line 154,
Specify true for the Big-blind line and set the functional memory index '111
By operating the ~7nn pit calculator 11, A
The result of the logical product of the contents of the side storage element 16a and the contents of the B111l storage element 16b is set in the B side storage element 16b.

この動作により2つの矩形が特定の点で重なシ合ってい
る場合には、その点に対応する機能メモリ素子71jの
両方の記憶素子16&、16bが真にセットされている
ことになシ、上記の演算を行なった結果として、Bll
!l記憶累子16素子真の値が保持されることになる。
If the two rectangles overlap at a specific point due to this operation, it means that both memory elements 16&, 16b of the functional memory element 71j corresponding to that point are set to true. As a result of performing the above calculation, Bll
! The true value of 16 elements of the l storage element will be held.

従って、全機能メモリ素子111〜7nnのB側艷憶素
子16bの内容を調べる事によって矩形図の重なシ結果
を調べる事ができる。このためには矩形の始点と終点と
して、この図形演算装置の全機能メモリ素子711〜7
nnを指定するようにレジスタ15に1とn。
Therefore, by checking the contents of the B side storage elements 16b of the full-function memory elements 111 to 7nn, it is possible to check the overlapping results of the rectangular diagrams. For this purpose, all functional memory elements 711 to 7 of this graphic arithmetic unit are used as the starting and ending points of the rectangle.
1 and n in register 15 to specify nn.

レジスタ16に0と0をセットし、メモリ選択線10に
B側を指定するように指示すればすべてのXBアドレス
選択線111b〜11nbは真となる。
By setting 0 and 0 in the register 16 and instructing the memory selection line 10 to specify the B side, all the XB address selection lines 111b to 11nb become true.

この時、一番端のXデータ伝搬線1301〜130nに
すべて偽の状態をセットすれば、各機能メモリ素子71
jの内部において、Xデータ伝搬線13(1−1)j 
の内容とB側記憶素子16bの内容との論理和がとられ
Xデータ伝搬線131Jとして出力されるため、最後の
Xデータ伝搬1113nl〜13nnには各X方向ごと
に全機能メモリ集子111〜7anのB stu記憶累
子素子b(2)Ltj理和をとったものがあられれ、こ
の結果がX方向レジスタ8にセットされる。従ってこの
X方向レジスタ8の内容がすべて偽であるかどうかを判
定する事によって2個の矩形に1複部があったかどうか
が判定できる。もし、1個でも偽でないものかあった場
合には、その対応する列に重複部分があった牛が示され
るため、この場合には上記のX方向のデータ伝搬と同様
に、レジスタ16にlとn、レジスタ15に0とOl一
番端Yデータ伝搬線1410〜14nOにすべて偶の状
態をセットすれは、全機能メモリ素子711〜7nnの
B側記憶素子16bの内容をX方向ごとに論理和をとっ
て結果がY方向レジ子夕8にセットされる。従って、X
方向レジスタ8とY方向レジスタ9によって指定される
場所に重複部分がある事が判明する。
At this time, if all the endmost X data propagation lines 1301 to 130n are set to a false state, each functional memory element 71
Inside j, the X data propagation line 13(1-1)j
Since the logical sum of the contents of the B-side storage element 16b and the contents of the B-side storage element 16b is taken and outputted as the X data propagation line 131J, the final X data propagation lines 1113nl to 13nn have full-function memory collections 111 to 111 for each X direction. The sum of B stu storage element b(2)Ltj of 7an is obtained, and this result is set in the X direction register 8. Therefore, by determining whether the contents of this X-direction register 8 are all false, it is possible to determine whether two rectangles have one or more copies. If there is even one item that is not false, the cows that have duplicated parts in the corresponding column are indicated, so in this case, as with the data propagation in the X direction, register 16 is By setting 0 to the register 15 and an even state to the end Y data propagation lines 1410 to 14nO, the contents of the B side storage element 16b of the full function memory elements 711 to 7nn are logically stored in each X direction. The sum is calculated and the result is set in the Y-direction register 8. Therefore, X
It turns out that there is an overlapping portion at the location specified by the direction register 8 and the Y direction register 9.

2個の矩形に対する重複部分がなく、3番目の矩形に対
してこれら2個の矩形間の重複を調べるときには、矩形
lが保持されている機能メモリ素子71jのA側記憶素
子16mに加えて、矩形20図形データもこのA II
I記憶素子16mにセットする。従ってA側記憶素子1
6mには矩形lと矩形2の両方の図形データが保持され
た状態になる。
When there is no overlap between two rectangles and a third rectangle is checked for overlap between these two rectangles, in addition to the A-side storage element 16m of the functional memory element 71j that holds rectangle l, Rectangle 20 figure data is also this A II
Set in I memory element 16m. Therefore, A side storage element 1
6m holds the graphic data of both rectangle 1 and rectangle 2.

この時には矩形3のデータを機能メモリ素子71JのB
 fIQ記憶素子16bに前記データをセットして、前
記したと同様の演算を行なう事によシ、矩形l。
At this time, data of rectangle 3 is stored in B of functional memory element 71J.
By setting the data in the fIQ storage element 16b and performing the same calculation as described above, a rectangle l is created.

2に対する矩形30重複テエククを1回の演算で行なう
。以下、xiがないと判定された矩形データを順次機能
メモリ素子7ijOA側記憶素子に追加した状態で次の
矩形とのTL複チェックを行っていけばよい。
The rectangle 30 overlap test for 2 is performed in one operation. Thereafter, the TL double check with the next rectangle may be performed while the rectangular data determined to have no xi are sequentially added to the functional memory element 7ijOA side storage element.

なお、上記実施例では機能メそり素子71jの構成をn
行れ列としたが任意の大きさの構成が可能であシ、また
、この構成と各矩形データの(x−y)座標値が直接対
応できない場合でも、x、yアドレス制御回路5,6に
適当な定数を加減、または乗除する事によって適当に1
クピングしてもよい。また、各矩形データを機能メモリ
素子T1jの記憶素子16m、16bに格納する場合、
この矩形に適当な定数によって拡大、縮少、シフト。
In the above embodiment, the structure of the functional mesori element 71j is n.
Although it is arranged in rows and columns, a configuration of any size is possible, and even if this configuration does not directly correspond to the (x-y) coordinate values of each rectangular data, the x, y address control circuits 5 and 6 1 by adding, subtracting, multiplying or dividing by an appropriate constant.
You can also cupping. Furthermore, when storing each rectangular data in the memory elements 16m and 16b of the functional memory element T1j,
Expand, reduce, and shift this rectangle using an appropriate constant.

X軸、Y軸対象等の演算を行なった結果によってアドレ
ス選択線を指定してもよい。また、上記実施例では機能
メモリ素子71jのビット演算装置として論理積だけを
示したが論理和、否定、排他的論理和等の各種演算機能
を付加してもよいし、演算結果を一時的に保持するレジ
スタを付加してもよい。
The address selection line may be specified based on the result of calculations for X-axis, Y-axis, etc. Further, in the above embodiment, only the logical product is shown as the bit operation device of the functional memory element 71j, but various operational functions such as logical sum, negation, and exclusive logical sum may be added, and the calculation result can be temporarily used. A register to hold the data may be added.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれは図形演算装置を、2個
の記憶素子とビット演算器を含む機能メモリを2次元的
に配置し、矩形の形状を示す始点と終点の(x−y)座
標値からその範囲に含まれるすべての機能メモリを選択
する回路を付加するように411成したので、従来に個
の図形データに対してに7回かかった図形の重複チェッ
クが、k回のくシ返しで可能となシ、大@に高速化でき
る効果がある。
As described above, the present invention provides a graphic arithmetic device in which functional memories including two storage elements and a bit arithmetic unit are arranged two-dimensionally, and the (x-y) 411 was created by adding a circuit that selects all functional memories included in the range from the coordinate value, so the duplicate check for figures that conventionally required seven times for each figure data was reduced to k times. This has the effect of greatly speeding up the process, which is possible with return.

【図面の簡単な説明】[Brief explanation of the drawing]

ta1図は従来の固形演算装置を示す構成図、第2図は
この発明の一実施例による図形演算装置の全体構成図、
第3図はこの一実施例の中で使われる機能メモリの回路
図でおる■ 5・・・Xアドレス制御回路、6・・・Yアドレス制御
回路、111〜7nn・・・機能メモリ素子、8・・・
X方向レジスタ、S・・・Y方向レジスタ、10・・・
メモリ選択i、16&、16b・・・記憶素子、17・
・・1ピツト演算器。 特許出願人 三菱電機株式会社
Figure ta1 is a configuration diagram showing a conventional solid-state arithmetic device, and FIG. 2 is an overall configuration diagram of a graphic arithmetic device according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a functional memory used in this embodiment. 5...X address control circuit, 6...Y address control circuit, 111-7nn...functional memory element, 8 ...
X direction register, S...Y direction register, 10...
Memory selection i, 16&, 16b...Storage element, 17.
...1 pit calculation unit. Patent applicant Mitsubishi Electric Corporation

Claims (1)

【特許請求の範囲】 2個の1ピツト記憶素子と1ビツト演算器とを主要素と
して構成する複数の・機・能メモリ素子と。 座標上の2点のアドレス値を入力し、その座標値の間に
紘さまれる全領域に対するアドレス選択信号を出力する
Xアドレス制御回路及びYアドレス制御回路と、2次元
的に配置された前記複数の機能メモリ素子中の前記記憶
素子の内容を行方向および列方向の全体に論理和をとっ
た結果を保持するX方向レジスタ及びY方向レジスタと
を有し、前記2次元的に配置された機能メモリ素子のう
ち、Xアドレス制御回路、及びYアドレス制御回路の両
Aから選択される機能メモリ素子の記憶素子への座標デ
ータの畳込みを行なうことにより、2つ以上の矩形の座
標位置情報を保持し、各1形データに対する図形演算を
前記全機能メモリ素子を用いて同時に行なえるようにし
た拳を%徴とする図形演算装置。
[Scope of Claims] A plurality of functional memory elements configured with two 1-bit storage elements and a 1-bit arithmetic unit as main elements. an X-address control circuit and a Y-address control circuit that input address values of two points on coordinates and output address selection signals for the entire area spread between the coordinate values; and the plurality of points arranged two-dimensionally. The two-dimensionally arranged function has an X-direction register and a Y-direction register that hold the result of ORing the contents of the memory element in the row direction and the column direction, and the function is arranged two-dimensionally. Among the memory elements, coordinate position information of two or more rectangles can be stored by convolving the coordinate data into the memory element of the functional memory element selected from both the X address control circuit and the Y address control circuit A. A graphic arithmetic device having a fist as a symbol, and capable of simultaneously performing graphic arithmetic operations on each one shape data using the full-function memory element.
JP7653684A 1984-04-18 1984-04-18 Arithmetic unit of figure Pending JPS60221877A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7653684A JPS60221877A (en) 1984-04-18 1984-04-18 Arithmetic unit of figure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7653684A JPS60221877A (en) 1984-04-18 1984-04-18 Arithmetic unit of figure

Publications (1)

Publication Number Publication Date
JPS60221877A true JPS60221877A (en) 1985-11-06

Family

ID=13607988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7653684A Pending JPS60221877A (en) 1984-04-18 1984-04-18 Arithmetic unit of figure

Country Status (1)

Country Link
JP (1) JPS60221877A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010063173A (en) * 1999-03-16 2010-03-18 Hamamatsu Photonics Kk High-speed vision sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010063173A (en) * 1999-03-16 2010-03-18 Hamamatsu Photonics Kk High-speed vision sensor

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