JPS60220645A - Data transmission system - Google Patents

Abstract

PURPOSE:To discriminate easily an instruction, to which a device responds, even in case of disturbance of the sequence of instructions and responses by including data indicating contents of the instruction in response data to the instruction of one device from the other device. CONSTITUTION:When an IC card 1 is inserted to an IC card reading/writing part 20, a write instruction and data are supplied to a CPU41 of the reading/writing part 20 from a CPU11 of a card handling machine. The CPU41 checks whether received write instruction and data are correct or not; and if they are correct, data and the instruction are supplied to a CPU3 of the card 1, and response data indicating the check result and data indicating the instruction to this response data are outputted to the CPU11. Then, the CPU11 finds that response data to the write instruction is transmitted back from the IC card reading/writing part 20 and correct transmission is performed. The CPU3 checks whether the instruction and data are transmitted correctly or not; and if they are transmitted correctly, the CPU stores them in a memory 4 and outputs data indicating the check result to the CPU41.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transmission system for transmitting data between, for example, an IC card, an IC card reading/writing unit, and a digital converter.

[Technical background of the invention and its problems]

Recently, automatic transaction devices or home banking systems in financial institutions have data memories that cannot be easily read for data security reasons.
When data is transmitted between the IC card reading/writing section and the IC card, response data (response) from the IC card to a command (command) from the IC card reading/writing section is simply response data. Therefore, if the sequence of commands from the IIc card reading/writing section and response data from the IC card is disrupted due to an interface abnormality, etc., it is possible to identify which command the current response data corresponds to and display the table. Rita Rita.

[Purpose of the invention]

This invention was made in view of the above-mentioned circumstances, and its purpose is that even if the sequence of the command from one device and the response data from the other device to the one device in response to this command is disrupted, The object of the present invention is to provide a data transmission method that can easily identify which command response data corresponds to.

[Summary of the invention]

Door/7'1 Decoy H3 In response to a command from one device, response data output from the other device includes data indicating the content of the command.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an IC card as a portable electronic device. The surface of this IC card 1 has a connection section 2.
are provided, for example, a plurality of terminals 21,...
It is composed of 28. Terminal 21 is for operating power supply voltage (-5V), terminal 22 is for grounding, terminal 2
3 is for a clock signal, a terminal 24 is for a reset signal, terminals 25 to 2[gamma] are for data input/output, and a terminal 2B is for a power supply voltage (-1-21V) for data writing.

Also, inside the IC card 1, as shown in FIG.
The unit (unit) s, a control program, a password, data, etc. are recorded, and is composed of a data memory 4 constituted by E2FROM or FROM, an interface circuit 5, and a RAM 6 for data processing. Each of the above parts is composed of an IC chip and is provided on one substrate. Furthermore, the interface circuit 5 and the connection section 2 are wired.

Furthermore, a fixing recess (or hole) 2 is provided on the surface of the IC card 1.

The CPU 3 is adapted to output data indicating the command and response data as shown in FIG. 3 in response to a command from a writer/reader (not shown).

Examples of the above response data include r OK J, "z? property error", etc., and data indicating the command includes commands, parts of commands, encrypted versions of commands, serial numbers, etc. There is.

4 and 5 show the configuration of the IC card handling machine 10 according to the present invention. 011 is a CPU (Central Processing Unit) that controls the entire system.
, IJ is an input means for inputting data such as a key date, 13 is a CRT display device, 14 is a ROM (read only memory) in which a control program is stored, and 15 is a RAM (random memory) in which data is stored.
16 is a dot printer that outputs various print data; 12 is a floppy disk device that stores and reproduces data on a floppy disk 19 inserted from the floppy disk insertion slot 18; 20
is an IC card reading/writing section. The above CPU 11 is I
A reader/writer in the CC card reader/writer 20 (not shown)
It outputs an instruction and data corresponding to the instruction.

The IC card reading/writing unit 20 reads the data in the memory of the IC chip 2 on the IC card 1 inserted from the card insertion slot 2, or writes the data in the memory, and issues the card. It is connected to the main body of the machine by a cable 22. That is, as shown in FIG. 6, a transport nozzle 31 for transporting the IC card 1 inserted from the card insertion slot 21 is provided. A rotatable transport roller 32 is positioned between the top and bottom of the
are provided in pairs. The pair of conveyor rollers 32 are provided at equal intervals along the conveyance base 3. Each of these transport rows 23
The distance from the center of the card 2 to the center of the adjacent transport roller 32 has the width dimension in the card transport direction. (IC card 1 is transported) f 3 is transport guide 3
3.

Further, the CP in the IC card 1 is placed on the transport guide 33.
A reader/writer 34 is arranged to exchange data with the US. This reading/writing device 34 is electrically connected to the connecting section 2.

As shown in FIG. 7, the reading/writing device 34 includes a CPU 41 that controls the whole, a ROM 42 in which a control program is stored, a RAM 43 for data storage, an interface circuit 44 for the IC card 1, and an interface circuit 44 for the IC card 1. It is constituted by a connect section 45 connected to the connect section 2 of the card 1 and an interface circuit 46 for the card handling machine 10 and connected to the CPU J 1.

The CPU 4J outputs an instruction and data corresponding to the instruction to the IC card 1 via the interface circuit 44 and the connection section 45, and outputs the instruction and data corresponding to the instruction to the IC card 1.
In response to a command from the interface circuit 46, data indicating the command and response data are output as shown in FIG.

Further, when the IC card 1 is loaded into the IC card reading/writing unit 20 and data is being transmitted, the pin 8 and the recess 7 of the IC card 1 engage with each other as shown in FIG.
IC card 1 is designed not to come out. This makes it possible to correct low-level positional deviations, and also
It is possible to prevent the C card 1 from being removed.

Next, the data transmission system of the present invention in such a configuration will be explained. For example, now, the user inserts the IC card 1 into the card insertion slot 21 of the IC card reading and loading section 20. Then, the connecting portion 2 of the IC guard 1 and the connecting portion 46 are electrically connected. At this time, the pin 8 and the hole 7 engage with each other, and the IC card 1 is fixed.

In this state, a write command and data are sent from the CPU iJ to the CPU via the interface circuit 46.
Supplied to U41. Then, the CPU 11 checks whether the received write command and data are correct.

If the data and write command have been transmitted correctly, the data and write command are sent to the CPU 3 via the interface circuit 44, the connection section 46, the connection section 2, and the interface circuit 5.
supply to. Further, the CPU 41 sends response data indicating the result of the above-mentioned check and data indicating an instruction for the response data, for example, data as shown in FIG.
Output to 11. As a result, the CPU Jz transfers the response data to the write command to the IC card reading/writing unit 20.
On the other hand, the CPU 3 to which the write command and data have been supplied checks whether the data have been transmitted correctly. If the data has been transmitted correctly, the CPU S causes the data memory 41 to store the data in accordance with the supplied write command. The CPU 3 also receives response data indicating the results of the above checks and data indicating an instruction for the response data.
For example, the data shown in FIG. 3 is output to the CPU 41. Thereby, the CPU 41 determines whether the response data to the write command has been returned from the IC card 1 and whether the data has been transmitted correctly.

Further, when another transmission error or an error occurs during instruction execution, the contents of the data error indicating the instruction are sent back in the same manner as described above.

Therefore, operations can be performed using a kind of automatic recovery function without stopping the device in the data transmission section 2-.

〔Effect of the invention〕

As described in detail above, according to the present invention, even if the sequence of a command from one device and response data from the other device to the command is disrupted, the response data is not related to which command. It is possible to provide a data transmission method that can easily identify whether the

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 is an external perspective view of an IC card, FIG. 2 is a block diagram schematically showing the configuration of the electric circuit of the IC card, and FIG. A diagram showing an example of data indicating a command and response data, FIG. 4 is an external perspective view of the card handling machine, FIG. 5 is a schematic diagram of the card handling machine, and FIG. 6 is a diagram of the reading/writing section. They are a sectional view showing a schematic structure and a block diagram schematically showing the structure of a seventh reading/writing device. 1...IC card, 2...Connection part, 3...C
P.U. 4...Data memory, 5...Interface circuit, +rutm 16. ,,TI'-h--km
It... CPU, 20...Reading/writing section, 33... Reading/writing device, 41... CPU, 44.46... Interface circuit, 45... Connecting section. . Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Giant EWR4Q>* x Horizontal Figure 4 0 Figure 5 Figure 6 Dying

Claims (1)

[Claims] A data transmission method for outputting response data from another device to one device in response to a command from one device, characterized in that a means is provided for adding data indicating the content of the command to the response data. .