JPS6022034U - Offset adjustment circuit after digital conversion - Google Patents
Offset adjustment circuit after digital conversionInfo
- Publication number
- JPS6022034U JPS6022034U JP11389783U JP11389783U JPS6022034U JP S6022034 U JPS6022034 U JP S6022034U JP 11389783 U JP11389783 U JP 11389783U JP 11389783 U JP11389783 U JP 11389783U JP S6022034 U JPS6022034 U JP S6022034U
- Authority
- JP
- Japan
- Prior art keywords
- adjustment circuit
- digital conversion
- offset adjustment
- offset
- adder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案のディジタル変換後のオフセット調整回
路の一実施例を示す回路図、第2図はS/D変換器の変
換テーブルの説明図、第3図は2進4ビツト加算器のブ
ロックタイアゲラムとその機能表の説明図である。
1・・・方位シンクロ、2・・・S/D変換器、3・・
・オリフィス設定器、4・・・プルアップ抵抗器、5と
6・・・加算器、7・・・増巾器、訃・・発光半導体、
9・・・電流制限抵抗器、10・・・交流電源、11・
・・加算ビット端子。Fig. 1 is a circuit diagram showing an embodiment of the offset adjustment circuit after digital conversion of the present invention, Fig. 2 is an explanatory diagram of a conversion table of an S/D converter, and Fig. 3 is a diagram of a binary 4-bit adder. FIG. 2 is an explanatory diagram of Blocktiagerum and its function table. 1... Azimuth synchronization, 2... S/D converter, 3...
・Orifice setter, 4...Pull-up resistor, 5 and 6...Adder, 7...Amplifier, 4...Light-emitting semiconductor,
9... Current limiting resistor, 10... AC power supply, 11.
...Addition bit terminal.
Claims (4)
れる変換器出力とオフセット設定器の設定出力を入力し
て2進数の加算を行うとともに加算値の最下位ビットに
1″を加える動作を行う加算器と、この加算器の出力信
号の各ビットの1″の位置を明示する指示手段と、この
指示手段の表示を見て上記設定出力の各ビットの1″又
は0″の位置を選定する上記オフセット設定器とからな
るディジタル変換後のオフセット調整回路。(1) An adder that inputs the converter output from which the analog signal is converted by the digital converter and the setting output of the offset setter, performs binary addition, and adds 1'' to the least significant bit of the added value. and an instruction means for specifying the position of 1'' of each bit of the output signal of the adder, and the offset for selecting the position of 1'' or 0'' of each bit of the setting output by looking at the display of this instruction means. Offset adjustment circuit after digital conversion consisting of a setting device.
チを利用する実用新案登録請求の範囲第1項記載のディ
ジタル変換後のオフセット調整回路。(2) The offset adjustment circuit after digital conversion according to claim 1, wherein a switch is used for each bit as the offset setting device.
する発光半導体と電流制限抵抗器を利用する実用新案登
録請求の範囲第1項記載のディジタル変換後のオフセッ
ト調整回路。(3) The offset adjustment circuit after digital conversion according to claim 1, which utilizes a light emitting semiconductor and a current limiting resistor for displaying the output signal of the adder as the indicating means.
圧を示す表示計を利用する実用新案登録請求の範囲第1
項記載のディジタル変換後のオフセット調整回路。(4) Utility model registration claim 1 which utilizes a display meter that indicates the voltage of the output signal of the adder as the indicating means.
Offset adjustment circuit after digital conversion as described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11389783U JPS6022034U (en) | 1983-07-22 | 1983-07-22 | Offset adjustment circuit after digital conversion |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11389783U JPS6022034U (en) | 1983-07-22 | 1983-07-22 | Offset adjustment circuit after digital conversion |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6022034U true JPS6022034U (en) | 1985-02-15 |
Family
ID=30263486
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11389783U Pending JPS6022034U (en) | 1983-07-22 | 1983-07-22 | Offset adjustment circuit after digital conversion |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6022034U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01214590A (en) * | 1988-02-23 | 1989-08-28 | Oji Paper Co Ltd | Side run winding core and its usage |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147517A (en) * | 1980-04-17 | 1981-11-16 | Mitsubishi Electric Corp | Analog-to-digital conversion circuit |
-
1983
- 1983-07-22 JP JP11389783U patent/JPS6022034U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56147517A (en) * | 1980-04-17 | 1981-11-16 | Mitsubishi Electric Corp | Analog-to-digital conversion circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01214590A (en) * | 1988-02-23 | 1989-08-28 | Oji Paper Co Ltd | Side run winding core and its usage |
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