JPS6022034U

JPS6022034U - Offset adjustment circuit after digital conversion

Info

Publication number: JPS6022034U
Application number: JP11389783U
Authority: JP
Inventors: 淡路　孝一郎
Original assignee: 株式会社トキメック
Priority date: 1983-07-22
Filing date: 1983-07-22
Publication date: 1985-02-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案のディジタル変換後のオフセット調整回
路の一実施例を示す回路図、第２図はＳ／Ｄ変換器の変
換テーブルの説明図、第３図は２進４ビツト加算器のブ
ロックタイアゲラムとその機能表の説明図である。１・・・方位シンクロ、２・・・Ｓ／Ｄ変換器、３・・
・オリフィス設定器、４・・・プルアップ抵抗器、５と
６・・・加算器、７・・・増巾器、訃・・発光半導体、
９・・・電流制限抵抗器、１０・・・交流電源、１１・
・・加算ビット端子。Fig. 1 is a circuit diagram showing an embodiment of the offset adjustment circuit after digital conversion of the present invention, Fig. 2 is an explanatory diagram of a conversion table of an S/D converter, and Fig. 3 is a diagram of a binary 4-bit adder. FIG. 2 is an explanatory diagram of Blocktiagerum and its function table. 1... Azimuth synchronization, 2... S/D converter, 3...
・Orifice setter, 4...Pull-up resistor, 5 and 6...Adder, 7...Amplifier, 4...Light-emitting semiconductor,
9... Current limiting resistor, 10... AC power supply, 11.
...Addition bit terminal.

Claims

[Scope of utility model registration request]

(1) An adder that inputs the converter output from which the analog signal is converted by the digital converter and the setting output of the offset setter, performs binary addition, and adds 1'' to the least significant bit of the added value. and an instruction means for specifying the position of 1'' of each bit of the output signal of the adder, and the offset for selecting the position of 1'' or 0'' of each bit of the setting output by looking at the display of this instruction means. Offset adjustment circuit after digital conversion consisting of a setting device.

(2) The offset adjustment circuit after digital conversion according to claim 1, wherein a switch is used for each bit as the offset setting device.

(3) The offset adjustment circuit after digital conversion according to claim 1, which utilizes a light emitting semiconductor and a current limiting resistor for displaying the output signal of the adder as the indicating means.

(4) Utility model registration claim 1 which utilizes a display meter that indicates the voltage of the output signal of the adder as the indicating means.
Offset adjustment circuit after digital conversion as described in section.