JPS60218852A - Resin sealed hybrid integrated circuit - Google Patents
Resin sealed hybrid integrated circuitInfo
- Publication number
- JPS60218852A JPS60218852A JP7401384A JP7401384A JPS60218852A JP S60218852 A JPS60218852 A JP S60218852A JP 7401384 A JP7401384 A JP 7401384A JP 7401384 A JP7401384 A JP 7401384A JP S60218852 A JPS60218852 A JP S60218852A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- tin
- resin
- semiconductor chip
- metal piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は出力段の半導体チップを錫−アンチモン半田で
固着し、完全な気密封止を施すことなく出力段の寿命を
向上させた樹脂封止型集積回路に関するものである。[Detailed Description of the Invention] Industrial Application Field The present invention is a resin-sealed type in which the output stage semiconductor chip is fixed with tin-antimony solder to improve the life of the output stage without completely hermetically sealing it. It concerns integrated circuits.
＃央例の構成）−その間頚占
近年、機器の小型化のために高密度の実装が行われ混成
集積回路が多く利用されるようになってきた。特に出力
段の半導体チップは大出力化の傾向に伴い多量の熱を発
生するために、その実装には高信頼度が要求され軟質の
比較的融点の高い半田による固着と気密封止が多く利用
される様になってきた。#Central configuration) - Interval In recent years, high-density packaging has been carried out to miniaturize devices, and hybrid integrated circuits have come into widespread use. In particular, semiconductor chips in the output stage generate a large amount of heat as the output tends to increase, so high reliability is required for their mounting, so fixing with soft solder with a relatively high melting point and hermetic sealing are often used. It's starting to look like it's being done.
以下に従来の出力段の半導体チップを実装した混成集積
回路について説明する。A hybrid integrated circuit mounting a conventional output stage semiconductor chip will be described below.
第１図は従来の出力段の半導体チップを実装した混成集
積回路の断面図であシ、１は良熱伝導性の金属板、３は
半田付可能な導電路、２は導電路３を金属板１に接着す
る良熱伝導性の絶縁物と成シ得る樹脂、４は良熱伝導性
の金属片、６は出力段の半導体チップ、７は半導体チッ
プ６を金属片４に固着させるだめの鉛系半田、８は半導
体チップを保護するチップコート材、５は金属片４を導
電路３に半田付するだめの鉛−錫系半田である。Figure 1 is a cross-sectional view of a hybrid integrated circuit mounted with a conventional output stage semiconductor chip. 1 is a metal plate with good thermal conductivity, 3 is a solderable conductive path, and 2 is a conductive path 3 made of metal. 4 is a metal piece with good thermal conductivity, 6 is a semiconductor chip of the output stage, and 7 is a resin for fixing the semiconductor chip 6 to the metal piece 4, which is bonded to the plate 1. 8 is a lead-based solder; 8 is a chip coating material for protecting the semiconductor chip; and 5 is a lead-tin-based solder for soldering the metal piece 4 to the conductive path 3.
９は中空部を設けた蓋体、１ｏは蓋体９の中空部に充填
される充填物、１１は金属板１、樹脂２、導電路３から
成る混成集積回路基板と蓋体９の接着部である。なお、
封止法の種類に応じて金属封止の場合は蓋′＃−９に金
属、充填物１ｏに不活性ガス、接着部１１に半田又は低
融点ガラス等の材料が用いられる。又、接着部１１は抵
抗溶接によって形成される場合がある。Reference numeral 9 denotes a lid body with a hollow portion, 1o a filler filled in the hollow portion of the lid body 9, and 11 a bonded portion between the lid body 9 and a hybrid integrated circuit board consisting of a metal plate 1, a resin 2, and a conductive path 3. It is. In addition,
Depending on the type of sealing method, in the case of metal sealing, metal is used for the lid '#-9, inert gas is used for the filler 1o, and materials such as solder or low melting point glass are used for the adhesive part 11. Further, the adhesive portion 11 may be formed by resistance welding.
又、樹脂封止の場合は、蓋体９に樹脂、充填物１０に注
型樹脂、接合部１１に注型と同時に接着される樹脂が用
いられる。In the case of resin sealing, a resin is used for the lid 9, a casting resin for the filler 10, and a resin that is bonded at the same time as the casting for the joint 11.
以上のように構成された混成集積回路について、以下そ
の動作を説明する。The operation of the hybrid integrated circuit configured as described above will be described below.
まず出力段の半導体チップ６が発熱する。次に、その熱
は伝導によシ鉛系半田７、金属片４、鉛−錫系半田６、
導電路３、樹脂２、金属板１を経て放熱されるが、この
とき鉛系半田７は、金属片４と半導体チップ６との熱膨
張係数の差によって生ずるせん断歪と、蓋体９、充填物
１ｏ、接着部１１の欠陥から侵入する酸素、水分、半導
体チップで生ずる熱によって起こる酸化とにより脆化が
促進され鉛系半田７の周辺部から応力腐食割れが起こシ
、クラックが進行し半導体チップ６は熱暴走し破壊する
。以上によって出力段の半導体チップ６の動作寿命が決
定され、その寿命を向上させるために蓋体９、充填物１
ｏ、接着部１１から構成される封止には完全な気密性が
必要であった。First, the semiconductor chip 6 in the output stage generates heat. Next, the heat is transferred by conduction, such as lead-based solder 7, metal piece 4, lead-tin solder 6,
Heat is radiated through the conductive path 3, the resin 2, and the metal plate 1. At this time, the lead-based solder 7 is exposed to shear strain caused by the difference in coefficient of thermal expansion between the metal piece 4 and the semiconductor chip 6, the lid 9, and the filling. Object 1o, embrittlement is promoted by oxygen and moisture entering through defects in the adhesive part 11, and oxidation caused by heat generated in the semiconductor chip, and stress corrosion cracking occurs from the periphery of the lead-based solder 7, and the crack progresses, causing the semiconductor to deteriorate. Chip 6 undergoes thermal runaway and is destroyed. The operating life of the semiconductor chip 6 in the output stage is determined by the above, and in order to improve the life, the lid 9 and the filler 1 are
o. The sealing made up of the adhesive portion 11 required complete airtightness.
しかしながら上記の従来の構成では、金属片４と半導体
チップ６との固着に酸化を起こし易い鉛系半田７を用い
、封止の周囲長がバイポーラＩＣ等と比較すると非常に
長く、多量の熱を発生するだめに、中空部を樹脂で充填
した場合でも前記基板と樹脂の間に熱による応力、経時
変化等で封止に欠陥が発生し混成集積回路での完全な気
密封止を得られず、長寿命化が実現できないと−う大き
な問題点を有していた。However, in the conventional configuration described above, lead-based solder 7 that easily oxidizes is used to bond the metal piece 4 and the semiconductor chip 6, and the circumferential length of the seal is very long compared to bipolar ICs, etc., and a large amount of heat is generated. Even if the hollow part is filled with resin, defects may occur in the sealing between the substrate and the resin due to stress due to heat, changes over time, etc., and a complete hermetic seal cannot be obtained in the hybrid integrated circuit. However, there was a major problem in that it was not possible to achieve a long service life.
発明の目的
本発明は上記従来の問題点を解消するもので半導体チッ
プを金属片に固着させるだめの半田として酸化しにくい
錫−アンチモン半田を用い、完全な気密封止を必要とせ
ずに長寿命を得ることのできる混成集積回路を提供する
ことを目的とする。Purpose of the Invention The present invention solves the above-mentioned conventional problems, and uses tin-antimony solder, which does not easily oxidize, as the solder for fixing a semiconductor chip to a metal piece, thereby achieving a long service life without requiring complete hermetic sealing. The object of the present invention is to provide a hybrid integrated circuit that can obtain the following.
発明の構成
本発明は、良熱伝導性の混成集積回路基板と、この基板
に半田付される出力段の半導体チップを錫−アンチモン
半田で固着させシリコンゴムでチップコートした金属片
と、前記基板に樹脂によって接着される中空部を設けた
樹脂製の蓋体とを備えた混成集積回路であり、半導体チ
ップと金属片との固着に酸化が著しく少ない錫−アンチ
モン半田を用い、さらにこの半田に固着時の熱によって
薄い酸化被膜を生成し半田表面を不活性にすることによ
り完全な気密封止を必要とせずに出力段の半導体チップ
の寿命を大幅に伸ばすことのできるものである。Structure of the Invention The present invention comprises a hybrid integrated circuit board with good thermal conductivity, a metal piece having an output stage semiconductor chip soldered to the board fixed with tin-antimony solder and chip-coated with silicone rubber, and the board. It is a hybrid integrated circuit equipped with a lid made of resin with a hollow part that is bonded with resin, and tin-antimony solder with extremely low oxidation is used to secure the semiconductor chip and the metal piece. By generating a thin oxide film using the heat generated during bonding and making the solder surface inactive, it is possible to significantly extend the life of the output stage semiconductor chip without requiring complete hermetic sealing.
実施例の説明
第２図は本発明の一実施例における出力段の半導体チッ
プを実装した混成集積回路の断面図を示すものである。DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a sectional view of a hybrid integrated circuit in which an output stage semiconductor chip is mounted according to an embodiment of the present invention.
第２図において１２は半導体チップ６を金属片４に固着
させるだめの錫−アンチモン半田、１３は樹脂製の蓋体
、１４は空気である。In FIG. 2, 12 is tin-antimony solder for fixing the semiconductor chip 6 to the metal piece 4, 13 is a resin lid, and 14 is air.
金属片、６は鉛−錫系半田、６は半導体チップ、８はシ
リコンゴムのチップコート材、１１は接着部で、これら
は従来の構成と同じものである。The metal piece, 6 is lead-tin solder, 6 is a semiconductor chip, 8 is a silicone rubber chip coating material, and 11 is an adhesive part, which are the same as the conventional structure.
以上のように構成された本実施例の混成集積回路につい
て以下その動作を説明する。まず半導体チップ６が発熱
する。次にその熱によシ半導体チップ６と金属片４との
熱膨張係数の差から錫−アンチモン半田１２にせん断歪
が生じる。そのせん断歪は錫〜アンチモン半田１２と半
導体チップ６との接合面の端部で最大となるが、錫−ア
ンチモン半田１２が酸化しにくい特性を持っていること
と、錫−アンチモン半田１２の表面に酸化被膜を生成し
不活性にしたことにより蓋体１３、接着部１１から侵入
する酸素、水分又は空気１４に含まれる酸素による酸化
を著しく軽減し、応力腐食割れの発生を満足させるだめ
の一要素を排除したことと、錫−アンチモン半田１２の
高温における降伏応力が鉛系半田に比較して約７０％大
きくせん断歪による応力を容易に弾性領域内で吸収させ
る＞１−＋Ａ＋４火フ＞１−ｕ−片凌柑１ ＋’−７亜
１１ ＋命を著しく向上することができる。The operation of the hybrid integrated circuit of this embodiment configured as described above will be explained below. First, the semiconductor chip 6 generates heat. Next, due to the heat, shear strain occurs in the tin-antimony solder 12 due to the difference in thermal expansion coefficient between the semiconductor chip 6 and the metal piece 4. The shear strain is maximum at the edge of the bonding surface between the tin-antimony solder 12 and the semiconductor chip 6, but this is due to the fact that the tin-antimony solder 12 has a property of being difficult to oxidize, and the surface of the tin-antimony solder 12 By forming an oxide film on the surface and making it inert, oxidation caused by oxygen, moisture, or oxygen contained in the air 14 entering from the lid body 13 and the adhesive part 11 is significantly reduced, which is one of the measures to satisfy the problem of stress corrosion cracking. In addition, the yield stress of the tin-antimony solder 12 at high temperatures is approximately 70% larger than that of lead-based solder, and the stress due to shear strain can be easily absorbed within the elastic region>1-+A+4 fire>1 -u-Kataryokan1 +'-7A11 +Can significantly improve life.
以上のように本実施例によれば、半導体チップ６と金属
片４との固着に酸化しにくい錫−アンチモン半田１２を
使用し、表面に酸化被膜を生成し不活性にし、応力腐食
割れの一要素を排除したことによシ気密封止を不要とし
、蓋体１３と金属板１、樹脂２、導電路３から成る混成
集積回路基板との接着部１１をエポキシ系の樹脂による
接着で容易に行なうことが可能であり、蓋体１３は機械
的な保護と取付けのためのフランジ部とを兼ねる作用を
し、樹脂１１に空孔等欠陥が生じても機械的強度を満足
すれば、充分品質、信頼度を確保でき、高度な設備導入
、多量の樹脂材料を不要とし、設備の簡素化による工数
の削減、工程歩留りの向上を可能とし、長寿命の混成集
積回路を低コストで容易に得ることができる。さらに錫
−アンチモン半田１２固有の物性として半田中に含まれ
る金属ガスの量が鉛系半田に比較し一桁少ないため、半
導体チップ６を金属片４に固着する際に発生する気泡等
の欠陥がなく、又、熱伝導度も鉛系半田より２倍優れて
おシ、電力損失に基づく緒特性および信頼度を著しく向
上させ、特に出力段を含む混成集積回路の不良発生率を
大幅に減少させることができる。As described above, according to this embodiment, the tin-antimony solder 12, which is difficult to oxidize, is used to bond the semiconductor chip 6 and the metal piece 4, and an oxide film is formed on the surface to make it inert, thereby preventing stress corrosion cracking. By eliminating the elements, there is no need for airtight sealing, and the bonding part 11 between the lid body 13 and the hybrid integrated circuit board consisting of the metal plate 1, resin 2, and conductive path 3 can be easily bonded with epoxy resin. The lid body 13 functions as a flange for mechanical protection and attachment, and even if defects such as holes occur in the resin 11, as long as the mechanical strength is satisfied, the quality is sufficient. , it is possible to ensure reliability, introduce advanced equipment, eliminate the need for large amounts of resin materials, simplify equipment, reduce man-hours, improve process yield, and easily obtain long-life hybrid integrated circuits at low cost. be able to. Furthermore, as a physical property unique to the tin-antimony solder 12, the amount of metal gas contained in the solder is one order of magnitude lower than that of lead-based solder, so defects such as air bubbles that occur when the semiconductor chip 6 is fixed to the metal piece 4 are reduced. In addition, the thermal conductivity is twice as good as that of lead-based solder, which significantly improves the electrical characteristics and reliability based on power loss, and in particular significantly reduces the failure rate of hybrid integrated circuits including the output stage. be able to.
なお、本実施例では半導体チップを金属片に錫−アンチ
モン半田で固着したが、これは半導チップを混成集積回
路基板の導電路上に直接固着させてもよい。この場合は
半導体チップの電力損失に変動が少なく比較的小さい場
合に限られるが、金属片を必要としないため工数、材料
の削減および大幅な小型軽量化が実現できる。In this embodiment, the semiconductor chip is fixed to the metal piece with tin-antimony solder, but the semiconductor chip may be directly fixed onto the conductive path of the hybrid integrated circuit board. In this case, the variation in power loss of the semiconductor chip is limited to cases where the power loss is relatively small, but since no metal piece is required, it is possible to reduce the number of man-hours and materials, and to achieve a significant reduction in size and weight.
発明の効果
本発明は出力段の半導体チップと金属片との固着に錫−
アンチモン半田を設けたことにより、固着した半田の応
力腐食割れの発生を満足させるだめの酸化を排除し、高
温での降伏応力を向上させ気密封止を必要とせずに長寿
命を実現することができ、さ−らに半導体チップの固着
時に発生する気泡がなく、熱伝導が優れていることがら
信頼度を著しく向上できる。また気密封止を不要とした
ため、混成集積回路基板に蓋体をエポキシ樹脂で接着す
る簡素な作業によシ容易に自動化を可能とし、生産コス
トの低減、工数の削減、工程歩留りの向上など、数々の
優れた効果を得ることのできる混成集積回路を実現でき
るものである。Effects of the Invention The present invention uses tin to fix the semiconductor chip and the metal piece in the output stage.
By providing antimony solder, it is possible to eliminate the oxidation that would otherwise cause stress corrosion cracking of stuck solder, improve the yield stress at high temperatures, and achieve a long life without the need for hermetic sealing. Furthermore, since there are no bubbles generated when the semiconductor chip is fixed, and the heat conduction is excellent, reliability can be significantly improved. In addition, since airtight sealing is not required, the simple process of bonding the lid to the hybrid integrated circuit board with epoxy resin can be easily automated, resulting in lower production costs, fewer man-hours, and improved process yields. It is possible to realize a hybrid integrated circuit that can obtain a number of excellent effects.
第１図は従来の混成集積回路の断面図、第２図は本発明
の一実施例における混成集積回路の断面図である。
１・・・・・・金属板、２・・・・・・絶縁樹脂、３・
・・・・・導電路、４・・・・・・金属片、５・・・・
・・鉛−錫系半田、６・旧・・半導体チップ、７・・・
・・・鉛系半田、８・・川・チンプコート材、９・・・
・・・蓋体、１ｏ・・・・・・充填物、１１・・・・・
・接着部、１２・・・・・・錫−アンチモン半田、１３
・旧・・樹脂製蓋体、１４・・・・・・空気。
代理人の氏名 弁理士 中 尾 敏 男 はが１名第１
図
窮 ２ 図FIG. 1 is a sectional view of a conventional hybrid integrated circuit, and FIG. 2 is a sectional view of a hybrid integrated circuit according to an embodiment of the present invention. 1...Metal plate, 2...Insulating resin, 3.
...Conducting path, 4...Metal piece, 5...
...Lead-tin solder, 6.Old...semiconductor chip, 7...
・・・Lead-based solder, 8... River chimp coat material, 9...
... Lid body, 1o ... Filling, 11 ...
・Adhesive part, 12...Tin-antimony solder, 13
・Old...Resin lid body, 14...Air. Name of agent: Patent attorney Toshio Nakao (1st person)
Illustration 2
Claims (1)
れた半田付可能な金属箔の導電路を設けた混成集積回路
基板と、この基板の導電路に半田付される出力段の半導
体チップを錫−アンチモン半田で固着させ半導体チップ
と半田固着部をシリコンゴムでチップコートした良熱伝
導性の金属片と、前記基板に樹脂によって接着される中
空部を設けた樹脂製の蓋体とを備えたことを特徴とする
樹脂封止型混成集積回路。A hybrid integrated circuit board with conductive paths made of solderable metal foil insulated by a thermally conductive resin on a highly thermally conductive metal plate, and an output stage semiconductor that is soldered to the conductive paths on this board. A metal piece with good thermal conductivity in which the chip is fixed with tin-antimony solder and the semiconductor chip and the solder fixed part are chip-coated with silicone rubber, and a resin lid body with a hollow part that is bonded to the substrate with resin. A resin-sealed hybrid integrated circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7401384A JPS60218852A (en) | 1984-04-13 | 1984-04-13 | Resin sealed hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7401384A JPS60218852A (en) | 1984-04-13 | 1984-04-13 | Resin sealed hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60218852A true JPS60218852A (en) | 1985-11-01 |
Family
ID=13534784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7401384A Pending JPS60218852A (en) | 1984-04-13 | 1984-04-13 | Resin sealed hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60218852A (en) |
-
1984
- 1984-04-13 JP JP7401384A patent/JPS60218852A/en active Pending
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