JPS60216575A - Semicondutor device - Google Patents

Abstract

PURPOSE:To enable the removal of the following resistance from a memory cell by a method wherein a high-resistance connecting the collector of a trasistor (Tr) to the emitter is formed of the base region. CONSTITUTION:A low-specific-resistance N type buried layer N<+>BL and a high- specific-resistance N type epitaxial layer N-EP form the collectors of Trs Q0, Q0', and it also acts as the base of a P-N-P TrQ3. The P<+> region connected to the X terminal and the P<+> region connected to the B terminal are connected with a P<-> region forming the high-resistance RC1. Both the P<+> regions connected to the X and B terminals act as the emitter and the collector of the TrQ3, respectively. Such a construction enables the substantial removal of high-resistance from a memory cell circuit and can reduce the occupation area of a chip.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device ftK. A memory circuit suitable for a semiconductor integrated circuit will be described below as an example.

The first memory cell using bipolar transistors
A configuration as shown in the figure is known. The memory cell in the figure is a current switching type, and has two data lines yLD1.
．． Read transistor Ql, QO1 information holding transistor Ql', QO' whose emitter is connected to LDO
, load resistance RCI.

ReO, a constant current circuit 5 through which information retention current IST flows;
It consists of a speed-up switching barrier diode or ordinary pn junction diodes DI, DO connected between the word line XI and the collector of QltQO. The above memory cell resistors RCI, RCO and diode D1. The common connection point of DO is connected to the word line driving transistor QXI via the word line x1,
The common connection point of transistors Q1' and QO' is the holding current I
It is connected to a constant current circuit 5 through which ST flows. The above data line LD1. Connected to the LDO are a constant current source circuit 3.4 through which the read current IR flows, a drive circuit (transistor QS1, resistor R1), (transistor QSO, resistor RO) that receives voltage VREF.

In the above circuit, information is held by turning on either the information holding transistor Ql' or QO'. A constant current circuit 5 supplies a holding current IST to the transistor Ql' or QO'. During the information retention period, the potential of the word line X1 is set to a low level by the transistor QXI,
The base potential of the transistor Q11QO is the transistor QSI of the drive circuit.

It is lower than the base potential of QSO. the result,
Transistor Q1. QO is in an off state.

When reading information, the base potential of the transistor Ql' or QO' in the on state of the memory cell becomes higher than the base potential of the transistors QSI and QSO of the drive circuit, and the base potential of the transistor QO' in the off state becomes higher.
Or the base potential of Ql' is the transistor QSI, Q
The potential of the word line X1 is set to a high level so that it is lower than the base potential of SO. As a result, either transistor Q1 or QO of the memory cell is turned on. The current IR of the constant current circuit 3 flows to the transistor QSI or the transistor Q1 according to the stored contents of the memory cell, and the current of the constant current circuit 4 similarly flows to the transistor QO or QSO. As a result, transistor QSI
Alternatively, a voltage is generated in the collector resistor R1 or RO of the QSO in accordance with the stored content of the memory cell.

When writing information, a potential difference is set between the base potentials of transistors QSI and QSO according to the write information. Due to this potential difference, the current IR of the constant current circuit 3 or 4 flows to the transistor Q1 or QO,
One of them is forcibly turned on.

In this memory cell, since the diodes DO and DI clamp the collector potential of the transistors Ql and QO, the read current IR can be increased, and high-speed reading and writing can be performed. Since this is done through the emitter of the transistor, the sense can be configured with a current switching circuit, and E CL (Emi
Because it has advantages such as good compatibility with CoupledLogic circuits, it is currently widely used as a memory cell in bi-porch RAM.

Currently, most of the high-speed bipolar e-memories in widespread use have a density of 1,024 bits or less per chip. The need for bipolar mesoris of 4.096 bits or more has increased. When the conventional memory cell shown in FIG. 4 is used as a memory of 4,096 bits or more, the following problem occurs. When increasing the degree of integration per chip of a conductor integrated circuit device (IC), it is usual to increase the degree of integration while keeping the power consumption per chip the same as before (usually, for example, about 500 mW/chip). be. This is an I that stores one chip.
This is because the allowable power consumption per chip is limited because the C package is usually a digital aluminum line with 14 to 18 pins.

Therefore, when increasing integration, the overall power consumption is usually set to approximately the same value as in the past. Therefore, the power consumption per bit of the memory circuit must be reduced. The IK bit (1,02
4 bits)/chip memory, the holding current I
For example, ST has a value of 25 μA to 50 μA/bit,
The entire 1,024 bits will result in a value of approximately 25mA to 50mA. If this value is held constant and a memory of 4,096 bits/chip is realized, a holding current of 6 μA to 12 μA or less is required per bit.

When reducing the holding current in this way, in order to give an appropriate holding operating potential to the transistors Ql and QO of the mesori cell, the resistance values of the collector resistors RCI and RCO should be set to a high resistance value, for example, a voltage of about 100 Ω. required to do so.

However, when attempting to increase the integration of the above circuit by reducing the holding current as described above, it becomes difficult to read information as described below.

For example, if the transistor QO' of the mesoricell is on,
It is assumed that Ql' is in an off state and information is read through QO. At this time, the read current IR is 0.5 mA, and the current amplification rate hFl of the transistor QO is 5 mA.
0, the base current of transistor QO is 10μA
(=0.5mA150). This base current is 1
A voltage drop is caused across the collector resistor RCI of 00KΩ, and as a result, the base potential of the transistor QO is lowered.

If the diode D1 were not present, a voltage drop of 1V would occur across the resistor RCI, but since the diode DI is present, a voltage drop of 0.8V, which matches the forward voltage of the resistor RCI, would occur. Therefore, the potential of node ■C1 is VC1=VX
1-0.8 (V). On the other hand, the collector potential ■CO of the turned-on transistor QO is clamped by the diode DO, so that VCO=VX1-0.8 (V), and VCl-VCO. That is, if it is assumed that QO is on, Ql is also on. As a result, without destroying the contents of the memory cells,
It becomes impossible to design such that all read current IR flows from QO.

In the case of IK bit memory, the value of RCI is about 15Ω, so VC1 = VX1 - 0.15 (V) VCO = VX1 - 0.8 (V), and since vct > vco, normal reading is possible. becomes possible.

As can be seen from the above, the conventional memory cell shown in FIG. 1 uses a clamp diode DO.

Although it has the advantage that the read current can be increased due to the function of Dl, if the holding current is set below a certain level and a device with a large bit capacity is designed, it has the disadvantage that the read current cannot be increased.

The structure of the memory cell as described above is based on the 1976 IEE
E International 5olid -8t
ate C1rcuitsConferenclp,
188-p., 189.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device t having a variable resistance element applied to a memory cell, which can obtain a large read current even when the holding current is small and the collector resistance is large.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 shows a memory cell circuit to which the present invention is applied.

The memory cell circuit shown in FIG. 2 differs from the conventional memory cell shown in FIG.
np) transistor Q2. The reason is that Q3 is added.

By adding this pnp transistor, it is possible to design a smaller holding current and a larger read current. The rationale is as follows.

It is now assumed that transistor QO is on and read current IR flows from transistor QO to data line LDO. In this case, the collector resistance RCO is large,
Also, since the read current IIL is thick t''-, the collector resistance R
The potential difference between both terminals of CO tends to exceed the a-direction voltage of the clamp diode DO, for example JtfO18v. As a result, the clamp ito' DO works, VXI-
Clamp operation is performed so that VCO4-0.8V.

On the other hand, the transistor Q3 is turned on because the voltage between its base and emitter minus the voltage between the terminals of the resistor RCO is 0.8 . At this time, the collector current of transistor Q3 flows in parallel with resistor RCI. A car that did
The base current supplied to QO is equal to the current through RCI and Q
The current becomes the sum of the collector current of 101 and the collector current of 101, and the potential difference between both ends of 101 decreases significantly. Therefore, even if the read current IR is made large, the potential difference (vxi-MCI) can be made small, and the desired purpose can be achieved.

In the memory cell circuit shown in Figure 2, the forward direction of the diode DI is the same as the forward direction between the base and emitter of the transistor Q2, and the same as the forward direction between the 4feK diode DO and the base and emitter of the transistor Q3. It is. Therefore, the clamp diodes DO and DI can be removed from the circuit of FIG. The memory cell circuit of FIG. 3 does not use a separate clamp diode. In Figure 3, the clamp diode D of Figure 2
The functions of O and D1 are transistors Q3 and Q, respectively.
An emitter-base PN junction of 2 takes its place.

Conventionally, a memory cell has been proposed in which the resistors RCO and RCI are removed from the mesori cell circuit shown in Fig. 3, but the characteristics are greatly influenced by the common emitter current amplification rate h□ of the transistor. For these reasons, it was difficult to put it into practical use. In the memory cell circuit of FIG. 3, the collector resistor RCO.

The presence of RCI provides operational stability.

In the memory of semiconductor integrated circuits, when a large number of bits are integrated on one chip, the number of elements in the memory cell circuit increases, and the area occupied by the chip increases accordingly, resulting in an increase in chip size and manufacturing cost. leading to an increase in The memory cell circuits shown in FIGS. 2 and 3 have a configuration in which a pnp) transistor is added to the memory cell circuit of FIG. , RC1 as an integral structure. As a result, the area occupied by the memory cell circuits shown in FIGS. 2 and 3 can be approximately equal to the area occupied by the conventional memory cell shown in FIG.

FIG. 4 shows half the circuit of the conventional memory cell shown in FIG. One memory cell shown in FIG. 1 can be formed by connecting the C and B terminals of two of these circuits, and also connecting the X terminals and the EST terminals. FIG. 4BK shows a cross-sectional view of the circuit in the same figure when it is configured as a semiconductor integrated circuit (hereinafter abbreviated as IC) made of oxide film insulation. N"BL is an N-type buried layer, and together with the NW epitaxial layer (N-BP), becomes the collector of transistors QO and QO'. The P+ layer near the two emitters EST and ER is QO and QO'
It acts as a base for the base, and the outlet for the base is B.

The P+ layer between the B terminal and the X terminal acts as a collector resistance RCI. The diode DO uses a diode between the P layers directly under the X terminal. By forming the constituent elements of the memory cell as one unit in this manner, the area occupied by the memory cell can be reduced. Note that the collector terminal C is the fourth
Although not shown in Figure B, N
The high concentration layer of the mold brings it out onto the chip surface.

Figures 5 to 7 are drawings of an example IC constituting the memory cell circuit shown in FIGS. 2 and 3. The unit structure of FIG. 5B, which shows the a-a' cross section of FIG. 7, includes half of the constituent elements of the memory cell circuit of FIGS. 2 and 3, as shown in FIG. 5. .

That is, in FIG. 5B, the low resistivity N-type buried layer N"
BL and high resistivity Nff1 epitaxial layer N-EP
constitutes the collector of QO, QO', which is also the collector of PNP
It also serves as the base of transistor Q3. The P+ region connected to the X terminal and the P+ region connected to the B terminal have high resistance R.
The P″″″ region forming the CI is connected.
Both the P+ regions connected to the terminal and the B terminal serve as the emitter and collector of the PNP transistor Q3, respectively. Further, the diode DO is formed of a P+ region connected to the X terminal and an N-EP region, but the region is substantially formed by the base-emitter junction of the transistor Q3.

Figures 7 to 7D are pattern diagrams of an IC in which a plurality of memory cells each consisting of a pair of unit structures are arranged. Unit configurations U110 and Ull constitute a pair, and similarly U120 and U 121 *U210 and U211. U
220 and U221 each form a pair.

In the plan view of FIG. 7, only the semiconductor junction patterns of each unit structure are shown by solid lines. In this figure, the same reference numerals as in FIG. 5B indicate the same semiconductor regions.

In the partially exploded plan view of FIG. 7B, solid lines indicate the pattern of contact holes formed in the thin oxide film 4' on the semiconductor region of each sitting configuration. That is, the electrode EST in FIG. 5B
, ER, B, X and C, contact hole A/1
3 to 17 are provided. In FIG. 7B, as is clear from FIG. 5B, a thick oxide film is disposed on the side surface of the collector region 7, and this thick oxide film remains even when a contact hole is formed in a thin oxide film. Therefore, there is no problem even if there is a portion of the contact hole 17 that extends beyond the collector region 7, as shown in FIG. The pattern of the human conductor region in FIG. 7 is shown by a broken line in the upper part of FIG.

The partially expanded plan view of FIG. 7C shows a wiring pattern and a pattern of through holes provided in the electrode 5111. The dashed line on the upper side of FIG. C and the solid line on the developed part on the lower right side indicate the wiring pattern, and the solid line on the upper side indicates the contact hole. Unit configuration U120 depending on each wiring
electrodes B, X, and C of unit configuration U121
are connected correspondingly. Similarly, unit structure U2
20 and U221 are connected to each other. Unit composition U12
The electrodes ER of 1 and U221 are connected to the wiring LD12, and similarly the electrodes of KU120 and U220 are connected to the wirings I and DO2.

The partially expanded plan view of Figure 7 shows the wiring pattern of the second layer. Arrangement 1VX1 connects to electrodes X of unit configurations U120 and U121 via through holes 20, and
2 are connected to the electrodes EST of the unit structures U120 and U121 through through holes 18 and 19, respectively.

Unit configuration UIIO and Ull memory cells and Ul 20
and U121 memory cells are placed in the same place, and U120
The memory cells U121 and U220 and U221 are arranged in the same column. Memory cells in the same row are commonly connected to word line VXI, and memory cells in the same row are connected to data lines LD12. Commonly connected to LD02.

The ICs of the above embodiments are fabricated by oxide island isolation techniques as described above.

For this purpose, first prepare a Pya silicon single crystal substrate 1,
On the surface thereof, antimony is selectively diffused as an Nll impurity to form a low resistivity N-type buried layer. A silicon epitaxial layer is then formed over the entire surface. An oxidation-resistant mask made of SL@N is selectively formed on this epitaxial layer. A thick selective oxide film is formed by heating in an oxidizing atmosphere. After removing the oxidation resistant isk,
A thin oxide film is formed on the exposed surface of the epitaxial layer by thermal oxidation. A photoresist film having 11c8 holes above the portion where the P clear region 5.6 (FIG. 5B) is to be formed is formed on the substrate including the epitaxial layer, and this photoresist film is used as a mask for impurity ion implantation. Boron ions are implanted into the epitaxial layer through the openings in the photoresist film and through the thin oxide film.

The resist film is removed, and boron ions are implanted at a low concentration into the entire surface of the substrate. As a result, a high resistance region IO is formed on the surface of the epitaxial layer between P-type regions 5 and 6, which is immediately connected to these regions 5 and 6.

A silicon oxide film is formed on the substrate surface by KCVD, and then the oxide film on the epitaxial layer 7', which will be used as a collector contact region, is removed by photoetching. Phosphorus is diffused into this layer 7' as an NW impurity.

The oxide film on the portions where the emitter regions 8, 9 (FIG. 5B, FIG. 7) will be formed is selectively removed, and arsenic is diffused into the surface of the Pa1 base region 5 through the openings. form 9.

Contact holes 13 to 17 (FIG. 7B) are opened in the oxide film,
Form aluminum wiring/electrodes with a thickness of 1 μm (Fig. 7C).

A silicon oxide film 11 is formed on the entire surface of the substrate including the electrodes by the CVD method, and contact holes 18 to 18 are formed in this oxide film 11.
19 (FIG. 7C).

Second layer aluminum wiring vX1, VX2.

12 (FIG. 7D).

As is clear from Figure 5B, there is a high resistance RCI.

PNP transistor Q3 and diode DO can be formed as an integral structure, and the high resistance RCI of FIG.

It is clear that the footprint is not increased compared to the diode DO and the diode DO. In this way, the memory cell circuit of the present invention has the advantage that it has superior characteristics and occupies approximately the same area as the conventional memory cell circuit.

FIG. 8 is a circuit diagram of another embodiment of a memory circuit to which the present invention is applied. This embodiment corresponds to the memory port shown in FIG. 2 in which capacitors C2 and C3 are provided between the emitters of transistors Q2 and Q3. These capacitors C2 and C3 are set up from Ruko and Ni.
7-) It is possible to make the collector potential ■co or MCI respond quickly to changes in @VXI, and it is expected that the circuit speed will increase and the operating margin of the memory cell will increase. Cross-sectional views of embodiments in which the present memory circuit is configured as a semiconductor integrated circuit are shown in FIGS. 9 to 11, respectively. In either case, capacitors C2 and C3 are connected to P
NP) is formed as a junction capacitance between the bases and emitters of transistors Q2 and Q3, and is configured to increase the junction capacitance.

In the embodiment shown in FIG. 9, N''B is used as a buried layer of NW conductivity type.
L(1) and N" B L (2+ are provided.N"
Arsenic (As) or antimony (S), which has a small diffusion coefficient, is used as a conductive impurity to constitute BL (1).
b), and phosphorus (P) with a large diffusion coefficient is used for N"BL (21). Due to these differences in impurities, subsequent heat treatments such as selective oxidation and emitter diffusion
Phosphorus of BL(2+ diffuses quickly into the silicon substrate and epitaxial layer. As a result, N'' B L(2+ becomes
It will come into contact with the P+ layer connected to the terminal, and the N”
A large junction capacitance C3 is formed between the BL(21) and the P+ layer 6.

In the embodiment shown in FIG. 10, the P+ layer 6 connected to the X terminal is formed with a deeper junction depth than the P layer connected to the B terminal, and the N
“It is in contact with the BL layer.

The embodiment of FIG. 11 includes another P+ layer P for forming a capacitor
By providing (2) and forming it in contact with the P+ layer and N''BL layer connected to the X terminal,
forming a capacitor.

Next, the present invention will be described.

FIG. 12 shows the high resistance RCI and transistor Q3 of the mesoricell shown in FIG. 5A.

Figure A shows a circuit diagram, and Figure B is an integrated version of Figure A, in which a high resistor and a transistor are integrated into a small footprint. This integral construction is the essence of the invention.

The equivalent resistance between E and 0 of the device shown in FIG. 12 shows the value of RO when carriers are not injected from the emitter or collector of the transistor QO, but if carriers are injected from the emitter, for example, The value is extremely low. This is illustrated in figure C. That is, the semiconductor device of FIG. 12B can be used as a variable resistor and occupies a small area, so it is suitable for semiconductor integrated circuits.

An application example of this variable resistance device is shown below.

FIG. 13 shows a part of the memory circuit. Transistor Q5
Q8 is a driver circuit for the memory cell row, and when both input signals IO and II are at low level, Q5. The common collector point X1 of Q6 becomes high level, and the transistor Q8
drives 9 and selects a memory cell row. Input signal IO, II
When either or both of them are at a high level, the potential at point X1 is at a low level, and Q8 keeps the memory cell row at a low level, leaving it in a non-selected state. That is, transistors Q5#Q6. Q7 is input IO.

Perform step 1 decoding. When a mesori circuit integrates a large number of bits, the current flowing through one memory cell is
As LL, n ICELL flowing to n cells flows to driver Q8. Therefore, the pace of Q8 is
If the forward current amplification rate of is hFI, then n-ICELL/
A current called hFE flows. Since this base current flows through a relatively large resistor R1, a potential difference is generated across R1,
Moreover, this value is large. This potential difference is caused by the transistor Q
The potential at the X1 point varies depending on the hFIC of 8. As a result, the operating margin of the memory circuit is reduced.

The driver circuit shown in FIG. 14 was devised as a measure against the above problem. Since the resistor RIKPNP) transistor Q9 is connected in parallel and its base is driven by the resistor R2 and the collector of the transistor Q7, when the point X1 becomes high level, a current of 1 flows through Q7, The potential at point A7 becomes a low level, and if the values of R2 and 11 are selected appropriately, Q9 can be turned on. Then, R1
The current flowing through Q9 will be shunted, and the equivalent impedance seen across R1 will become significantly smaller, reducing it to the base current of Q8, and the high-level potential drop at point X1 will become small.

The driver circuit in FIG. 14 is Q7. If R1 and Q9 are formed as a single structure as shown in FIG. 15, the occupied area can be reduced and it is suitable for large scale integration.

Figure 16 shows a modification of the dry nozzle circuit shown in Figure 14, with P
NP) is equipped with a transistor QIO, and when changing the human 7 points from a low level to a high level, only R2 is provided (Ql
Since the accumulated charge in the base of Q9 is removed through O, high-speed switching can be expected. However, in the circuit shown in Figure 16, when the potential at point X1 becomes low, the transistor QIO base-emitter diode acts as a clamp diode, so it does not drop below approximately 0.8 volts, so the amplitude at point X1 is ,There is a limit.

Although the circuits shown in FIGS. 14 and 16 are used as drivers for memory cell circuits, it goes without saying that they can be widely used as ordinary current switching type logic circuits. An example is shown in FIG.

At this time, it is clear from the above description that R901, Q903 and Q902 can be formed as an integral structure, or that R902, Q904 and Q902 can be formed as an integral structure.

Shown in FIG. 18 is a modification of the circuit of FIG. 17, with transistors Q903. This is the ultimate case where the emitter current amplification rate of Q904 is made small and no transistor operation is performed, and Q903. Q904 is a diode D1001. D1
It becomes 002. This circuit consists of resistors R100I and R1002
Although the impedance seen from both ends of is not variable,
Diode D1001. The clamping effect of D1002 is
Limit saturation of transistors Q100I and Q1002,
Enables high-speed switching. This circuit also has R100
I, Dlool and Q1002 as a monolithic structure,
Also R1002. D1002 and Q100I can be formed as a unitary structure.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional memory circuit, and FIG. 2 is a circuit diagram of a conventional memory circuit. Figure 3 is a circuit diagram of the memory circuit of the embodiment, Figure 4 is a circuit diagram of a circuit that constitutes half of the memory circuit of Figure 1, and Figure 4B is an IC version of the circuit in Figure A. A cross-sectional view of
Figure 5 is a circuit diagram of a circuit that constitutes half of the memory circuits in Figures 2 and 3, Figure 5B is a cross-sectional view of the circuit in Figure A when it is integrated into an IC, and Figure 6 is a circuit diagram of a circuit that constitutes half of the memory circuits in Figures 2 and 3. Figure B is a cross-sectional view of the IC in the middle of manufacturing; Figure 7 is a plan view for explaining the IC that constitutes the memory circuit; Figures 9, 10, and 11 are cross-sectional views of the circuit in Figure 9 as an IC, Figure 12A is a circuit diagram of a variable impedance circuit, and Figure 12B is an IC similar to the circuit in Figure A. FIG. 12C is a characteristic curve diagram of the circuit shown in FIG. 12A, FIG. 13 is a circuit diagram of a part of the memory circuit, and FIG. Fig. 15 is a cross-sectional view of the circuit shown in Fig. 14 when integrated into an IC, Fig. 16 is a circuit diagram of a memory circuit of another embodiment, and Figs. 17 and 18 are circuits of current switching circuits of the respective embodiments. It is a diagram. DI, Do...clamp diode, RCI. RCO...Resistance, Ql, Ql'', QO, QO',
Q2. Q3...transistor, VXI...word line,
LDI, LDO...data line, IST...holding current. Figure 1 Figure 2 Figure 3 Figure 4 Figure A Figure 4 B Figure 5 A R Figure 5 B Figure 6 Figure 7 Figure A Figure 7 B Figure 7 C Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 fl (t) Figure 12 A 0 Figure 12 6 Figure 12 C Figure 13 (b) Figure 15 Figure 16

Claims (1)

[Claims] 1. Two impurity layers of the same conductivity type are used as the emitter and collector of a transistor, respectively, and an impurity layer of a conductivity type opposite to that of the two impurities is in contact with these two impurity layers. The base, the emitter and collector impurity layers are connected by a resistor made of an impurity layer of the same conductivity type as these, the pace of the transistor is used as a control terminal, and the emitter and collector are connected to both terminals of a variable resistance element, respectively. semiconductor devices. Margin below