JPS6021522A - Formation of resist pattern - Google Patents

Formation of resist pattern

Info

Publication number
JPS6021522A
JPS6021522A JP58128912A JP12891283A JPS6021522A JP S6021522 A JPS6021522 A JP S6021522A JP 58128912 A JP58128912 A JP 58128912A JP 12891283 A JP12891283 A JP 12891283A JP S6021522 A JPS6021522 A JP S6021522A
Authority
JP
Japan
Prior art keywords
resist
cooling
baking
temperature
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58128912A
Other languages
Japanese (ja)
Other versions
JPH0546091B2 (en
Inventor
Kei Kirita
桐田 慶
Yoshihide Kato
加藤 芳秀
Toshiaki Shinozaki
篠崎 俊昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58128912A priority Critical patent/JPS6021522A/en
Publication of JPS6021522A publication Critical patent/JPS6021522A/en
Publication of JPH0546091B2 publication Critical patent/JPH0546091B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16Coating processes; Apparatus therefor
    • G03F7/168Finishing the coated layer, e.g. drying, baking, soaking

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To form efficiently and quickly a high precision resist pattern by executing at least either one of the the baking and cooling of resist at a pressure which is lower than the atmospheric pressure. CONSTITUTION:A resist film is applied on a substrate to be processed (step 1) and such substrate with resist film is housed in a reduced pressure vessel at a pressure lower than the atmospheric pressure, it is then subjected to the resist baking for the specified period at the specified temperature Tb (step 2). Next, the resist film is uniformly cooled for the entire part until the final cooling temperature Tc while the cooling period or cooling speed are controlled in a reduced pressure vessel (step 3). Thereafter, this resist is irradiated selectively with an electromagnetic wave in the specified wavelength or particle beam having the specified energy (step 4). Such irradiated area is developed and rinsed (step 5). Thereby, a resist pattern can be formed. Where the baking is carried out under a reduced pressure condition, vaporization of resist solvent can be accelerated and the time required for resist baking can be curtailed and where the resist is cooled under the reduced pressure condition, dispersion of cooling speed resulting from natural circulation of ambient can be reduced.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、高精度のレジストノリ―ンを形成する方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming highly accurate resist lines.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

超I,8 Iを初めとして、平導体素子の集積度が高ま
るにつれて、微細にして且つ高精度のパターン形成技術
が散水されている。このため、許容される寸法精度は非
常に厳しいものとなり、最先端分野では6インチ口マス
ク或いは5インチ径ウエハ内で3σ≦0.1〔μm〕(
但し、σはウェハの平均寸法値に対するばらつきを示す
)の寸法精度が要求されている。また、量産ラインで使
用されるためにはマスク間或いはウェハ間での寸法変動
を3σく0.15Cμm〕に抑えることが必要であシ、
一方量産効果を高めるために、レジストの感度としては
高いものが要求されている。しかし、一般に高感度のレ
ジストは解像性が劣るため所望の・Pターン寸法精度を
得ることが困難であり、逆に高解像性を有するレジスト
は低感度であるために量産ラインにおいて高スループツ
トが得られない等の問題があった。
As the degree of integration of flat conductor elements increases, including super I and 8 I, techniques for forming fine and highly accurate patterns are being developed. For this reason, the permissible dimensional accuracy is extremely strict, and in the most advanced fields, 3σ≦0.1 [μm] (
However, a dimensional accuracy of σ (σ indicates variation with respect to the average dimensional value of the wafer) is required. In addition, in order to be used on a mass production line, it is necessary to suppress the dimensional variation between masks or between wafers to 3σ (0.15 Cμm).
On the other hand, in order to increase the effectiveness of mass production, high sensitivity resists are required. However, in general, high-sensitivity resists have poor resolution, making it difficult to obtain the desired P-turn dimensional accuracy; conversely, high-resolution resists have low sensitivity, making it difficult to achieve high throughput on mass production lines. There were problems such as not being able to obtain

第1図は従来技術によるレジスト・ぞターy形成プロセ
スを示すフローチャートである。まず、被処理基板上に
周知の回転塗布法により所定の膜厚にレジストを塗布す
る。次いで、塗布溶媒の除去並びにレジストと基板との
密着性を向上させるために、オープン等を用いレジスト
に応じた所定の温、度(T、)でレジストのベーク(シ
リベーク)を行ガう。この後、オープンから取シ出され
たレジスト膜付被処理基板を大気中で支持台にて自然放
冷することにより、室温まで20〜30分かけて冷却す
る。冷却の完了したレジスト膜付被処理基板に対して、
レジストの種類に応じた所定の照射量で所定波長域の電
磁波、例えば紫外光或いは所定エネルギーの粒子線、例
えば電子線を選択的に照射する。その後、現像・リンス
処理工程を経て所望のレジストパターンが形成されるこ
とになる。
FIG. 1 is a flowchart showing a resist layer formation process according to the prior art. First, a resist is applied to a predetermined thickness on a substrate to be processed by a well-known spin coating method. Next, in order to remove the coating solvent and improve the adhesion between the resist and the substrate, the resist is baked (silibake) at a predetermined temperature and degree (T) depending on the resist using an open method or the like. Thereafter, the resist film-coated substrate taken out from the opening is allowed to cool naturally on a support stand in the atmosphere, and is cooled to room temperature over 20 to 30 minutes. For the processed substrate with resist film that has been completely cooled,
Electromagnetic waves in a predetermined wavelength range, such as ultraviolet light, or particle beams with a predetermined energy, such as electron beams, are selectively irradiated with a predetermined dose depending on the type of resist. Thereafter, a desired resist pattern is formed through a development and rinsing process.

ところで、上述した自然放冷中の被処理基板−にのレジ
スト膜について、ある時点における膜面全体の温度分4
11紮赤外線放射温度計によって不発EllJ者婚が調
べたところ、第2図に示すような結果が得られた。なお
、この場合の自然冷却に先立つ(−り時の温度T、は・
−16’ 0 [℃]であった。第2図において、レジ
スト膜付被処理基板21の中央部」こ方(A点)では温
度が高く(冷却のされ方が遅く)、中心領域(B点)を
経て下方(C点)に進むにつれて温度が低く(冷却のさ
れ方が速く)なっている。なお、図中の各曲線は等混線
である。第3図は第2図のA 、 R。
By the way, regarding the resist film on the substrate to be processed during the natural cooling described above, the temperature of the entire film surface at a certain point is 4.
When the misfired EllJ was examined using a 11-cell infrared radiation thermometer, the results shown in Figure 2 were obtained. In addition, in this case, prior to natural cooling (the temperature T at the time of cooling is
-16'0 [°C]. In FIG. 2, the temperature is high (cooling is slow) at the center of the resist film-coated substrate 21 (point A), and moves downward (point C) through the center region (point B). As the temperature increases, the temperature becomes lower (cooling speed becomes faster). Note that each curve in the figure is an equicross line. Figure 3 shows A and R in Figure 2.

C各点における時間に対する温度変化を示したもので、
曲線3 Z 、 、’? 2・、33は夫々A−,B。
C shows the temperature change over time at each point,
Curve 3 Z, ,'? 2. and 33 are A- and B, respectively.

C点に対応する冷却特性である。A点とB点の最大温度
差は15〔℃〕程度、A点とC点の最大温度差は3o 
cc:+程度であった。これらの湯度測定はレジスト膜
」二の被測”定部分に熱電対を接飾させて行なった。こ
のような温度分布(冷却速度むら)が生じる原因として
は、自然放冷中破処理基板が支持台等の上に立てられて
いるだめに、熱放散による雰囲気の自然対流が基板面に
沿って上向きに起シ易いこと、及び基板下方部が支持台
により熱を奪われ易いこと等が考えられる。また、本発
明者等は上記レジスト膜付被処理基板の冷却時の温度分
布と照射・現像処理後のレジストパターンの寸法精度と
の関係について着目し、第2図の温度測定点A、B、C
領域における形成・ぞターンの寸法を測定したところ、
本来例えば2〔μm〕の同寸法であるべきパターンにB
点において0.1〔μm) 、 C点において0.2〔
μm〕程度の誤差が生じており、レジスト膜付基板の冷
却時の温度分布と形成されるレジストパターンの寸法分
布とが、レジストの感度分布を通して完全に対応してい
ることを確認した。
This is the cooling characteristic corresponding to point C. The maximum temperature difference between points A and B is about 15 [℃], and the maximum temperature difference between points A and C is 3o
cc: It was about +. These hot water temperature measurements were carried out by attaching a thermocouple to the part to be measured of the resist film.The cause of this temperature distribution (uneven cooling rate) is that the partially damaged substrate is left to cool naturally. Because the board is placed on a support stand, etc., natural convection of the atmosphere due to heat dissipation tends to occur upward along the board surface, and the lower part of the board is likely to lose heat due to the support stand. In addition, the present inventors focused on the relationship between the temperature distribution during cooling of the resist film coated substrate and the dimensional accuracy of the resist pattern after irradiation and development processing, and determined the temperature measurement point A in FIG. ,B,C
When we measured the dimensions of the formation/zooturn in the area,
B to a pattern that should originally have the same size of, for example, 2 [μm]
0.1 [μm) at point C, 0.2 [μm] at point C
It was confirmed that the temperature distribution during cooling of the resist film-coated substrate and the size distribution of the formed resist pattern completely corresponded to each other through the sensitivity distribution of the resist.

したがって、ノ!ターン寸法むらのない高精度のレジス
ト/f、ターンを得るには、レジストベーク後基板面内
で温度分布を生ぜしめ々い様な均一な、冷却が不可欠で
あることJが判った。
Therefore, no! It has been found that in order to obtain highly accurate resist/f and turns with uniform turn dimensions, extremely uniform cooling is essential, which causes temperature distribution within the substrate surface after resist baking.

−1方、発明者等がベーク後のレジストの冷却速度とレ
ジストの感度との関係に着目し、種々5− 実験・研究を重ねた結束、従来のプロセスにより長時間
かけて冷却されたレジストの感度は低いが、レジストを
ベータしたのち急速に冷却した場合のレジスト感度は飛
躍的に高まることを見出した。さらに、ベーク後のレジ
スト膜の冷却過程を制御することにより、レジストの感
度を再現性良く任意の値に変化させ得ることも見出した
。そして、これらのプロセスを経たレジストの解像性は
、レジスト本来の・!ターン解像性に比べて、いささか
も劣化していないことも確認している。また、従来のレ
ジストベークは大気中にて行っていたので、ベークの主
目的であるレジスト溶媒の蒸発に長時間を要することが
判明した。
On the other hand, the inventors focused on the relationship between the cooling rate of the resist after baking and the sensitivity of the resist, and after conducting various experiments and research, they found Although the sensitivity is low, it has been found that when the resist is beta-ized and then rapidly cooled, the sensitivity of the resist increases dramatically. Furthermore, we have also discovered that by controlling the cooling process of the resist film after baking, it is possible to change the sensitivity of the resist to any desired value with good reproducibility. The resolution of the resist that has gone through these processes is the same as the resist itself! We have also confirmed that there is no deterioration in the slightest compared to the turn resolution. Furthermore, since conventional resist baking was performed in the atmosphere, it was found that it took a long time to evaporate the resist solvent, which is the main purpose of baking.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、高精度のレジスト・臂ターンを効率良
く且つ迅速に形成することができ、・臂ターン形成のス
ループット向上等に寄与し得るレジストパターン・形成
方法を提供することにある。
An object of the present invention is to provide a resist pattern/forming method that can efficiently and quickly form a highly accurate resist/arm turn, and that can contribute to improving the throughput of forming the arm turn.

−6= 〔発明の概要〕 本発明の骨子は、レジストのベーク及び冷却の少くとも
一方を常圧よシ低い圧力下(1気圧未満9で行うことに
ある。
-6= [Summary of the Invention] The gist of the present invention is to perform at least one of baking and cooling the resist under a pressure lower than normal pressure (less than 1 atmosphere 9 ).

本発明によるレジスト・ヤターン形成の基本的プロセス
の概要を第4図に示す。まず、被処理基板上にレジスト
膜を塗布形成する。次いで、このレジスト膜付基板を1
気圧より低い圧力下の減圧容器中に収納し、所定の温度
T、にて所定の時間レジストベークを行う。次いで、上
記減圧容器内で冷却時間若しくは冷却速度を制御しなが
ら最終冷却温度T。までのレジスト膜全体に亘る均一な
冷却を行う。しかるのち、このレジストに対し所定波長
の電磁波若しくは所定エネルギの粒子線を選択的に照射
し、これを現像・リンス処理することによ如レジストパ
ターンを形成する。
FIG. 4 shows an outline of the basic process of forming a resist pattern according to the present invention. First, a resist film is applied and formed on a substrate to be processed. Next, this resist film coated substrate was
The resist is stored in a reduced pressure container under a pressure lower than atmospheric pressure, and resist baking is performed at a predetermined temperature T for a predetermined time. Next, the final cooling temperature T is achieved while controlling the cooling time or cooling rate in the vacuum vessel. Uniform cooling is performed over the entire resist film. Thereafter, this resist is selectively irradiated with electromagnetic waves of a predetermined wavelength or particle beams of a predetermined energy, and is developed and rinsed to form a resist pattern.

すなわち本発明は、被処理基板上にレジストを塗布し、
ベークしたのち冷却し、さらに所定波長の電磁波若しく
は所定エネルギの粒子線を該レジストに選択的に照射し
、現像処理を施すことによりレジスト・譬ターンを形成
する方法において、上記レジストのベーク及び冷却の少
くとも一方を常圧より低い圧力下で行うようにした方法
である。
That is, the present invention applies a resist onto a substrate to be processed,
In a method of forming a resist pattern by baking and cooling the resist, selectively irradiating the resist with electromagnetic waves of a predetermined wavelength or particle beams of a predetermined energy, and performing a development process, the above resist is baked and cooled. This is a method in which at least one of the steps is carried out under a pressure lower than normal pressure.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、レジストのベークを減圧下で行うこと
により、レジスト溶媒の蒸発を促進させることができ、
これによりレジストベークに要する時間の大幅な短縮を
はかり得る。また、レジストの冷却を減圧下で行うこと
によシ、算囲気の自然対流に起因する冷却速度むら発生
を著しく低減することができ、これによシレジヌト・母
ターンの高精度化をはかり得る。さらに、レジストのベ
ーク及び冷却を減圧下で行うことにより、レジスト膜面
へのダスト付着が低減され、その結果所望のレジストパ
ターンが高歩留りで得られる。
According to the present invention, by baking the resist under reduced pressure, evaporation of the resist solvent can be promoted,
This can significantly reduce the time required for resist baking. In addition, by cooling the resist under reduced pressure, it is possible to significantly reduce the occurrence of uneven cooling rate due to natural convection of the surrounding air, and thereby it is possible to improve the precision of resists and master turns. Furthermore, by baking and cooling the resist under reduced pressure, dust adhesion to the resist film surface is reduced, and as a result, a desired resist pattern can be obtained with a high yield.

また、冷却時間若しくは冷却速度を制御しながら、ベー
ク温度T、から最終冷却温度T。までのレジスト冷却を
均一に行うことによシ、レジストの電磁波若しくは粒子
線照射に対する感度を、その解像性を劣化させることな
く、大幅に高めることができる。したがって、低感度の
レジストでも本発明の方法によって解像性を劣化させる
ことなく高感度化され、電磁波若しくは粒子線による照
射処理時間を短縮することができる。
Also, while controlling the cooling time or cooling rate, the temperature can be changed from the bake temperature T to the final cooling temperature T. By uniformly cooling the resist up to this point, the sensitivity of the resist to electromagnetic waves or particle beam irradiation can be greatly increased without deteriorating its resolution. Therefore, even a low-sensitivity resist can be made highly sensitive by the method of the present invention without deteriorating its resolution, and the time for irradiation treatment with electromagnetic waves or particle beams can be shortened.

しかも、本発明によれば、ベーク後のレジスト膜が膜全
体にわたって均一に冷却されるほか、レジスト膜面が粗
面化することもないので、被処理基板上全体に亘って寸
法ばらつきの少ない極めて高精度のレジスト・リーンを
形成することができる。
Moreover, according to the present invention, the resist film after baking is cooled uniformly over the entire film, and the resist film surface is not roughened, so that it can be processed with very little dimensional variation over the entire substrate to be processed. High precision resist lean can be formed.

〔発明の実施例〕[Embodiments of the invention]

〈実施例1〉 本実施例ではポリ(2,2,2−ト!j フルオロエチ
ル−α−クロロアクリレート)よシなるポジ型電子線感
応レジストを用いた場合のレジストパターン形成方法に
ついて述べる。まず、上記レジストを周知の回転塗布法
によシ被処理基板上9− に塗布する。このとき、塗布膜厚は0.3〜l〔μm〕
程度でよいが、ここでは0.8〔μm〕としだ。
<Example 1> In this example, a method for forming a resist pattern using a positive electron beam sensitive resist such as poly(2,2,2-t!j fluoroethyl-α-chloroacrylate) will be described. First, the resist described above is applied onto the substrate to be processed 9- by a well-known spin coating method. At this time, the coating film thickness is 0.3 to 1 [μm]
It may be about 0.8 [μm] here.

被処理基板としては、平導体ウェハやガラス基板等積々
あるが、ここでは金属膜付ガラス基板を用いた。次に、
後述するようなレジスト処理装置を用いて、レジスト膜
のベーク、冷却処理を行なった。ベーク温度T、は、上
記レジストのガラス転移温度T、 (〜133℃)を越
える140〜190(℃〕程度でよいが、ここでは18
0〔℃〕とした。また、ベーク時のレジスト膜付被処理
基板を取シ巻く圧力は約0.1気圧とし、この状態での
レジストベークを約10分間行なった。ベーク時間は更
に短縮できるが、本実施例では取シ敢えず10分間とし
た。次いで、べ一り温度Tbから最終冷却温度Tcまで
の冷却を冷却時間(冷却速度)を変えて行った。本実施
例では上記温度Tcを室温とした。ベーク温度Tbから
室温Toまでの冷却時間は、例えば030分、05分、
01分、010秒、05秒となるように冷却処理を操作
した。第5図はこれらの冷却10− 処理時における基板温度変化について示したものである
。いずれの冷却処理においても、レジスト膜の冷却は膜
面全体に亘って均一になされた。なお、冷却時のレジス
ト膜付基板を取シ巻く周囲の圧力は0.0001気圧と
した。これらのベーク・冷却プロセスを経た夫々のレジ
スト試料について電子線感度特性を調べた結果、第6図
に示す夫々に対応する感度曲線が得られた。
Although there are many types of substrates to be processed, such as flat conductor wafers and glass substrates, a glass substrate with a metal film was used here. next,
The resist film was baked and cooled using a resist processing apparatus as described below. The baking temperature T may be approximately 140 to 190 (°C), which exceeds the glass transition temperature T, (~133°C) of the above resist, but here it is 180°C.
The temperature was set to 0 [°C]. Further, the pressure surrounding the substrate to be processed with the resist film during baking was approximately 0.1 atm, and resist baking was performed in this state for approximately 10 minutes. Although the baking time can be further shortened, it was set to 10 minutes in this example. Next, cooling was performed from the plate temperature Tb to the final cooling temperature Tc while changing the cooling time (cooling rate). In this example, the temperature Tc was set to room temperature. The cooling time from the baking temperature Tb to the room temperature To is, for example, 030 minutes, 05 minutes,
The cooling process was operated so that the time was 01 minutes, 010 seconds, and 05 seconds. FIG. 5 shows changes in substrate temperature during these cooling steps. In both cooling treatments, the resist film was cooled uniformly over the entire film surface. Note that the pressure surrounding the resist film-coated substrate during cooling was 0.0001 atm. As a result of examining the electron beam sensitivity characteristics of each of the resist samples subjected to these baking and cooling processes, sensitivity curves corresponding to the respective resist samples shown in FIG. 6 were obtained.

第6図の特性は、前記夫々のベーク、冷却プロセスを経
たレジスト膜に加速電圧20 [keV]の電子線を照
射後、室温でメチルイソブチルケトン(MIBK) :
イソノロビルアルコール(IPA)=7:3現像液で1
0分間の現像処理、次いでIPA液にて30秒間のリン
ス処理を施こして得られたものである。Tcが■〜■の
夫々のベーク、冷却プロセスに対応するレジスト感度(
膜厚残存率ゼロとなる場合の電子性照射量)は■4 X
 10−6(に/y++” ]、■2 X 10−’ 
[:φ2〕、■9 X 10−’ (07m” )、■
5×10−6〔C/crn2〕、■3 X 10−’ 
(C/2m2)であった。なお、従来のベーク(180
℃)→自然放冷(室温まで)プロセスを経て、上記同様
の電子線照射、現像、リンス処理を施こした場合の上記
レジストの感度は〜4 X 10−6[C/cvn”J
である。
The characteristics shown in FIG. 6 are as follows: After irradiating the resist film that has undergone the respective baking and cooling processes with an electron beam at an accelerating voltage of 20 [keV], methyl isobutyl ketone (MIBK) is heated at room temperature.
Isonorovir alcohol (IPA) = 7:1 with 3 developer
This was obtained by developing for 0 minutes and then rinsing with IPA solution for 30 seconds. Resist sensitivity (corresponding to each baking and cooling process with Tc from ■ to ■)
Electronic irradiation dose when the film thickness residual rate is zero) is ■4
10-6(ni/y++" ], ■2 X 10-'
[:φ2], ■9 X 10-' (07m”), ■
5×10-6 [C/crn2], ■3 X 10-'
(C/2m2). In addition, conventional bake (180
℃) → Natural cooling (to room temperature) process, followed by electron beam irradiation, development, and rinsing treatment as above, the sensitivity of the above resist is ~4 x 10-6 [C/cvn"J
It is.

一方、上記したプロセスと同様の減圧ベーク、減圧冷却
を程こしたレジスト膜付基板(金属膜付6インチロガラ
ス基板)の周辺部分を除く全面へ、20’ [lc・■
]電子線描画装置を用いて上記■〜■の場合の夫々に対
応する照射量で選択的ノ4ターン照射を行ない、室温に
おけるB I BK7I PA(7/3 )現像、TP
Aリンス処理を行なってレジストパターンを形成した。
On the other hand, 20' [lc・■
] Using an electron beam lithography system, selective 4-turn irradiation was performed at the irradiation dose corresponding to each of the above cases ① to ②, and B I BK7I PA (7/3) development and TP at room temperature were performed.
A resist pattern was formed by performing A rinsing treatment.

これ等レジストパターンの解像性はすべて良好であった
。また、例えば線幅05〜2.0 〔μm〕の範囲のレ
ジストパターンの寸法制度を測定評価した結果、いずれ
かの場合のレジストパターンもすべて高精度で基盤面内
の寸法変動誤差3σ(0,1(μm〕を十分に満足する
ものであった。
The resolution of these resist patterns was all good. Furthermore, as a result of measuring and evaluating the dimensional accuracy of resist patterns in the line width range of 05 to 2.0 [μm], the resist patterns in either case were all highly accurate and had a dimensional variation error of 3σ (0, 1 (μm).

〈実施例2〉 本実施例では、レジストとしてポリメチルメタクリレー
トを用いた。その他の条件は先に説明した実施例1と略
同じである。ベーク温度Tbは、本レジストのガラス転
移温度Tg〜110〔℃〕を越えた1 80 [:℃)
に設定した。レジストベーク時の基板周囲の圧力は0.
3気圧とし、レジストベーク時間は10分間とした。レ
ジスト膜冷却時の基板周囲の圧力は約0.0002気圧
で、冷却は実施例1と同様に、’][’b−+ T、に
至る冷却時間として030分、05分、01分、010
秒、■5秒を選んだ。これらのレジスト試料に加速電圧
20 (keV)の電子線照射後、室温で13分間のM
I BK現像、30秒間のIPAリンスを行なって、夫
々の感度特性を調べた。その結果、冷却プロセスに対応
するレジスト感度は夫々■9 X 10−’[C/m2
:]、(i) 6.5 X 10−’(C7j’z” 
、)、■5 X 10−6(07m” )、■3.5 
X 10−’(C/rnZ)、■2.5 X 1 o−
6[:c/crn”)でありた。なお、従来のベーク(
160℃)→自然放冷(室温まで)を経て、上記と同じ
照射、現像、リンス効果を施こした場合の上記レジスト
の感度は〜1×10−5〔C/rn2〕程度である。
<Example 2> In this example, polymethyl methacrylate was used as the resist. Other conditions are substantially the same as in Example 1 described above. The bake temperature Tb is 180 [:°C] which exceeds the glass transition temperature Tg of this resist ~110 [°C]
It was set to The pressure around the substrate during resist baking is 0.
The pressure was 3 atm, and the resist bake time was 10 minutes. The pressure around the substrate during cooling of the resist film was approximately 0.0002 atm, and the cooling was performed in the same manner as in Example 1, with cooling times of 030 minutes, 05 minutes, 01 minutes, and 010 minutes to reach ']['b-+T.
I chose 5 seconds. After irradiating these resist samples with an electron beam at an accelerating voltage of 20 (keV), M was applied at room temperature for 13 minutes.
IBK development and IPA rinsing for 30 seconds were performed to examine the sensitivity characteristics of each. As a result, the resist sensitivity corresponding to the cooling process is 9 x 10-' [C/m2
: ], (i) 6.5 X 10-'(C7j'z"
), ■5 X 10-6 (07m”), ■3.5
X 10-'(C/rnZ), ■2.5 X 1 o-
6[:c/crn”).In addition, conventional baking (
When the same irradiation, development, and rinsing effects as above are applied after allowing the resist to cool naturally (to room temperature) (160°C), the sensitivity of the resist is approximately 1×10 −5 [C/rn2].

一方、上記したプロセスと同様の減圧ベーク、減圧冷却
を施こしたレジスト膜付基板(金属膜付6インチロガラ
ス基板)の周辺部分を除く全面へ、20 (k@y)電
子線描画装置を用いて、上記■〜■の場合の夫々に対応
する照射量で選択的・母ターン照射を行ない、室温にお
けるMIBK現像、IPAリンヌ処理を施こしてレジス
トパターンを形成した。すべての基板上全体に亘シ、レ
ジストパターンの解像性は良好であった。また、実施例
1と同様に線幅0.5〜2.0〔μm〕の範囲のレジス
トパターンの寸法精度を測定評価した結果、何れの場合
のレジス)/4ターンもすべて高精度で、基板面内の寸
法変動誤差はすべて3σ(0,1(μm〕であった。
On the other hand, a 20 (k@y) electron beam lithography system was applied to the entire surface of the resist film-coated substrate (6-inch glass substrate with metal film), which had been subjected to vacuum baking and vacuum cooling in the same manner as in the process described above, except for the peripheral area. Selective master turn irradiation was carried out using the above-mentioned irradiation dose corresponding to each of cases ① to ②, MIBK development at room temperature and IPA Linne treatment were performed to form a resist pattern. The resolution of the resist pattern was good over all the substrates. In addition, as in Example 1, as a result of measuring and evaluating the dimensional accuracy of the resist pattern in the line width range of 0.5 to 2.0 [μm], all of the resist patterns in the range of 0.5 to 2.0 [μm] had high precision in all cases. All in-plane dimensional variation errors were 3σ (0.1 (μm)).

なお、本発明の主眼は、レジスト膜のベーク温度Tbか
ら室温付近までの冷却時間(冷却速釦を均一に制御する
こともさることながら、べ一り・冷却の少くとも一方を
減圧下で行うことにある。レジストのベーク・冷却プロ
セスヲ減圧=14− 下で行う理由は、基板へのダスト付着を極力抑制させる
こともさることながら、ベーク時のレジスト照射の迅速
蒸発や、ベーク・冷却時の熱対流に起因するレジスト膜
面の温度分布むらの発生を抑えて膜面全体に亘ってベー
ク・冷却を均一になさんがためである。
The main focus of the present invention is to control the cooling time from the bake temperature Tb of the resist film to around room temperature (not only to uniformly control the cooling speed button, but also to perform at least one of the baking and cooling under reduced pressure). The reason why the resist baking and cooling process is performed under reduced pressure = 14 - is to suppress dust adhesion to the substrate as much as possible, as well as to prevent rapid evaporation of the resist irradiation during baking and to reduce the pressure during baking and cooling. This is to prevent uneven temperature distribution on the resist film surface caused by thermal convection and to ensure uniform baking and cooling over the entire film surface.

また、上記実施例方法を用いれば、例えば糧槓のレジス
ト照射(露光)装置の性能に適合するように、レジスト
の感度を任意に且つ均一に設定することができる。本発
明者等の研究結果によると、ベーク温度Tbから室温付
近までの冷却時間を短く(冷却速度を大きく)すればす
るほどレジストの感度は向上することが判っている。逆
に、冷却時間を述ばす(冷却速度を小さくする)とレジ
ストの感度は下がることが判っている。したがって、情
況に応じて、上記実施例とは異なる冷却時間(冷却速度
)を設定して、レジストの感度を所望の値に設定できる
ことは云うまでもない。また、上記実施例では二種類の
レジストに関してのレジストハターン形成例について述
べたが、レジストの種類、レジス[・膜が被着される基
板材刺、レジストの溶媒、現像液、さらにはベーク温度
等についても上述した実施例に限定されるものではなく
、公知の種種の材料、現像液及びベーク温度についても
本発明の効果が達成されることを確認している。
Further, by using the method of the above embodiment, the sensitivity of the resist can be arbitrarily and uniformly set to match the performance of, for example, a resist irradiation (exposure) device. According to the research results of the present inventors, it has been found that the shorter the cooling time from the bake temperature Tb to around room temperature (the higher the cooling rate), the more the sensitivity of the resist improves. On the contrary, it is known that the sensitivity of the resist decreases when the cooling time is increased (the cooling rate is decreased). Therefore, it goes without saying that depending on the situation, the sensitivity of the resist can be set to a desired value by setting a cooling time (cooling rate) different from that of the above embodiment. In addition, in the above embodiment, an example of resist pattern formation regarding two types of resists was described, but the type of resist, the substrate material to which the resist film is attached, the solvent of the resist, the developer, and even the baking temperature, etc. It has been confirmed that the effects of the present invention are not limited to the above-mentioned embodiments, and that the effects of the present invention can be achieved using various known materials, developing solutions, and baking temperatures.

また、レジストの露光方法についても、上述した電子線
以外に光線、X線、イオンビーム等の所定波長域の電磁
波や所定エネルギーの粒子線を用いても本発明の意図す
る効果が得られる。
Furthermore, as for the resist exposure method, in addition to the above-mentioned electron beam, electromagnetic waves in a predetermined wavelength range such as light beams, X-rays, and ion beams, or particle beams with a predetermined energy can be used to obtain the effects intended by the present invention.

まだ、ベーク・冷却時の基板を取り巻く周囲圧力の設定
についても上述の実施例で述べた値に限定されるもので
はない。ベーク時の圧力はレジスト中の溶媒がベータ時
に突沸若しくは突出しない範囲で可及的に小さく設定す
ればよく、冷却時の圧力は更に小さくする方が処理容器
内の残留ガスに因る熱対流を抑制する上で望ましい。
However, the setting of the ambient pressure surrounding the substrate during baking and cooling is not limited to the values described in the above embodiments. The pressure during baking should be set as low as possible so that the solvent in the resist does not bump or protrude during beta, and the pressure during cooling should be set even lower to reduce thermal convection caused by residual gas in the processing container. Desirable for suppression.

〈実施例3〉 次に、本発明方法を実施するのに適合するレジスト処理
装置の一例について第7図を参照して説明する。第7図
の装置は、例えば基板に対するレジスト塗布から露光前
までの一連の工程を全自動処理する装置の一部で、レジ
ストのべ−り・冷却を担うものである。図中71はべ一
り・冷却処理容器で、この容器7)の対向する側壁には
開閉パルプ72a、72bがそれぞれ設けられている。
<Embodiment 3> Next, an example of a resist processing apparatus suitable for carrying out the method of the present invention will be described with reference to FIG. 7. The device shown in FIG. 7 is a part of a device that fully automatically processes a series of steps from, for example, resist application to a substrate to before exposure, and is responsible for baking and cooling the resist. In the figure, reference numeral 71 denotes a baking/cooling treatment container, and opening/closing pulps 72a and 72b are provided on opposite side walls of this container 7), respectively.

処理容器71の底部には支持台73が設けられ、この支
持台73上にレジスト膜74付基板75が載置されるも
のとなっている。支持台73の内部には複数の冷却用冷
媒通孔76が画一的に設けられており、支持台73の上
方には加熱ヒータ77が載置されている。
A support stand 73 is provided at the bottom of the processing container 71, and a substrate 75 with a resist film 74 is placed on this support stand 73. A plurality of cooling refrigerant passage holes 76 are uniformly provided inside the support base 73, and a heater 77 is placed above the support base 73.

また、処理容器71の土壁部には圧力制御用管77が設
けられている。
Further, a pressure control pipe 77 is provided in the clay wall of the processing container 71.

前工程でレジスト膜74が塗布形成された被処理基板7
5は、開閉パルプ7−2gを介して容器71内の支持台
73上に載置される。次いで、圧力制御用管78を通し
て容器71内の圧力を1気圧よシ低い所定の圧力に設定
し、ヒータ17− 77により所定温度T、にて所定時間レジストのベーク
を行う。ベーク後、容器71内の圧力を更に下げ、冷媒
通孔76に流量及び温度等が制御された冷媒を循環させ
て、支持台73−Fの基板75をその下面から均一に冷
却する。この場合、基板75と支持台73とが良好な熱
接触をなしていることが必要である。冷却処理終了後、
容器71内の圧力を大気圧に戻し、開閉パルプ7Zbを
介して基板75を容器71内に取り出す。この後、基板
75は次工程の処理部へ搬送される。
A substrate to be processed 7 on which a resist film 74 has been applied and formed in the previous process.
5 is placed on the support stand 73 in the container 71 via the openable pulp 7-2g. Next, the pressure inside the container 71 is set to a predetermined pressure lower than 1 atmosphere through the pressure control pipe 78, and the resist is baked at a predetermined temperature T for a predetermined time using the heater 17-77. After baking, the pressure inside the container 71 is further lowered, and a refrigerant whose flow rate and temperature are controlled is circulated through the refrigerant passage 76 to uniformly cool the substrate 75 of the support base 73-F from its lower surface. In this case, it is necessary that the substrate 75 and the support base 73 have good thermal contact. After the cooling process is finished,
The pressure inside the container 71 is returned to atmospheric pressure, and the substrate 75 is taken out into the container 71 via the opening/closing pulp 7Zb. Thereafter, the substrate 75 is transported to a processing section for the next step.

なお、本装置は枚葉式の処理方法を採用しているので、
状況によっては減圧ベーク・昇圧冷却器の部分における
処理時間が長くなって、他の部分との処理時間のバラン
スを崩し、高スループツト化がはかれない場合も生じ得
る。このような場合には、該減圧ベーク・昇圧冷却器を
例えばサークル状若しくは並列状に複数個配置し、他の
部分の処理時間及びベーク・冷却処理時間を考慮した適
正な遅延時間を設定して、サ18− −クル的若しくは並列的にベーク・冷却処理を行なうこ
とにより、装置全体としての高スループツト化をはかる
ことが可能である。さらには、減圧ベーク・昇圧冷却器
を所定許容範囲内で大型化し、該部分だけをパッチ処理
方式にすることもできる。また、レジスト膜ベーク後の
冷却手段として、レジスト膜面全体に温度及び流量が均
一制御された冷風を吹き付けるようにしてもよい。この
場合の冷却は、減圧状態の容器7Z内の圧力を大気に戻
すプロセスと併用させることができる。
Please note that this device uses a single-wafer processing method, so
Depending on the situation, the processing time in the vacuum baking/boosting cooler section may become long, which may upset the balance of processing times with other sections, making it impossible to achieve a high throughput. In such a case, arrange multiple decompression baking/boosting coolers, for example in a circle or in parallel, and set an appropriate delay time that takes into account the processing time of other parts and the baking/cooling processing time. By performing the baking and cooling processes in cycles or in parallel, it is possible to increase the throughput of the entire apparatus. Furthermore, it is also possible to increase the size of the vacuum bake/boost cooler within a predetermined allowable range and apply a patch processing method to only this part. Furthermore, as a cooling means after baking the resist film, cold air whose temperature and flow rate are uniformly controlled may be blown onto the entire surface of the resist film. Cooling in this case can be combined with a process of returning the pressure inside the reduced pressure container 7Z to the atmosphere.

その他、本発明の要旨を逸脱しない範囲で、種々変形し
て実施することができる。
In addition, various modifications can be made without departing from the gist of the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のレジストパターン形成工程を概略的に示
す流れ作業図、第2図は従来工程におけるレジストベー
ク後の被処理基板の各点の温度変化の様子を等温曲線で
示す模式図、第3図は前記温度変化の様子を時間対温度
曲線で示す特性図、第4図は本発明によるレジストパタ
ーン形成工程を概略的に示す流れ作業図、第5図はレジ
スト冷却速度を示す特性図、第6図はレジスト感度を示
す特性図、第7図は本発明方法に適合するレジスト処理
装置の一例を示す断面図で4る。 7I・・・処理容器、12m、72b・・・開閉パルプ
、73・・・支持台、74・・・レジス)[,7,5・
・・基板、76・・・1媒通孔、7r・・・ヒータ、7
8・・・圧力制御用管。 出願人代理人 弁理士 鈴 江 武 彦ゴー 1 一−4メ@礪し
Figure 1 is a flowchart schematically showing a conventional resist pattern forming process, Figure 2 is a schematic diagram showing isothermal curves of temperature changes at various points on the substrate after resist baking in the conventional process; 3 is a characteristic diagram showing the state of the temperature change as a time vs. temperature curve, FIG. 4 is a flow chart schematically showing the resist pattern forming process according to the present invention, and FIG. 5 is a characteristic diagram showing the resist cooling rate. FIG. 6 is a characteristic diagram showing resist sensitivity, and FIG. 7 is a sectional view showing an example of a resist processing apparatus suitable for the method of the present invention. 7I...Processing container, 12m, 72b...Opening/closing pulp, 73...Support stand, 74...Regis) [,7,5...
...Substrate, 76...1 medium hole, 7r...heater, 7
8...Pressure control pipe. Applicant's agent Patent attorney Suzue Takehiko Go 1 1-4 Me@Tsuboshi

Claims (3)

【特許請求の範囲】[Claims] (1)被処理基板上にレジストを塗布し、ベークしたの
ち冷却し、さらに所定波長の電磁波或いは所定エネルギ
の粒子線を上記レジストに選択的に照射し、現像処理を
施すことによりレジストハターンを形成する方法におい
て、前記レジストのベーク及び冷却の少くとも一方を常
圧より低い圧力下で行うことを特徴とするレジストツヤ
ターン形成方法。
(1) A resist pattern is formed by applying a resist onto a substrate to be processed, baking it, cooling it, selectively irradiating the resist with an electromagnetic wave of a predetermined wavelength or a particle beam of a predetermined energy, and performing a development process. A method for forming a resist glossy turn, characterized in that at least one of baking and cooling the resist is performed under a pressure lower than normal pressure.
(2) 前記レジストの冷却として、冷却時間若しくは
冷却速度を制御しながら、ベーク温度T。 から最終冷却温度Tまで均一に行うことを特徴とする請
求 ターン形成方法。
(2) As for cooling the resist, the baking temperature T is controlled while controlling the cooling time or cooling rate. A method for forming billed turns, characterized in that the process is carried out uniformly from to a final cooling temperature T.
(3) 前記レジストの冷却を急冷により行なうことを
特徴とする特許請求の範囲第1項記載のレジストパター
ン形成方法。
(3) The resist pattern forming method according to claim 1, wherein the resist is cooled by rapid cooling.
JP58128912A 1983-07-15 1983-07-15 Formation of resist pattern Granted JPS6021522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58128912A JPS6021522A (en) 1983-07-15 1983-07-15 Formation of resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58128912A JPS6021522A (en) 1983-07-15 1983-07-15 Formation of resist pattern

Publications (2)

Publication Number Publication Date
JPS6021522A true JPS6021522A (en) 1985-02-02
JPH0546091B2 JPH0546091B2 (en) 1993-07-13

Family

ID=14996435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58128912A Granted JPS6021522A (en) 1983-07-15 1983-07-15 Formation of resist pattern

Country Status (1)

Country Link
JP (1) JPS6021522A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717645A (en) * 1983-01-19 1988-01-05 Tokyo Shibaura Denki Kabushiki Kaisha Method and apparatus for forming resist pattern
JPS63107116A (en) * 1986-10-24 1988-05-12 Fujitsu Ltd Resist baking method
US4777116A (en) * 1985-10-22 1988-10-11 Kuraray Co., Ltd. Method for manufacturing phase gratings of a combination pattern-refraction modification type
JPS63161803U (en) * 1987-04-10 1988-10-21
JPS63259559A (en) * 1987-04-16 1988-10-26 Hitachi Condenser Co Ltd Pattern forming method for printed circuit board
JPH01133621U (en) * 1988-02-29 1989-09-12
KR100369571B1 (en) * 1994-12-28 2003-04-10 도레이 가부시끼가이샤 Coating method and coating device
US8053174B2 (en) 2003-02-05 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for wiring
CN104204550A (en) * 2012-03-23 2014-12-10 萱场工业株式会社 Hydraulic cylinder

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717645A (en) * 1983-01-19 1988-01-05 Tokyo Shibaura Denki Kabushiki Kaisha Method and apparatus for forming resist pattern
US4777116A (en) * 1985-10-22 1988-10-11 Kuraray Co., Ltd. Method for manufacturing phase gratings of a combination pattern-refraction modification type
JPS63107116A (en) * 1986-10-24 1988-05-12 Fujitsu Ltd Resist baking method
JPS63161803U (en) * 1987-04-10 1988-10-21
JPS63259559A (en) * 1987-04-16 1988-10-26 Hitachi Condenser Co Ltd Pattern forming method for printed circuit board
JPH01133621U (en) * 1988-02-29 1989-09-12
KR100369571B1 (en) * 1994-12-28 2003-04-10 도레이 가부시끼가이샤 Coating method and coating device
US8053174B2 (en) 2003-02-05 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for wiring
US8460857B2 (en) 2003-02-05 2013-06-11 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for wiring
CN104204550A (en) * 2012-03-23 2014-12-10 萱场工业株式会社 Hydraulic cylinder

Also Published As

Publication number Publication date
JPH0546091B2 (en) 1993-07-13

Similar Documents

Publication Publication Date Title
KR860002082B1 (en) Forming method and apparatus of resistor pattern
JPH0257334B2 (en)
JPS6021522A (en) Formation of resist pattern
US4897337A (en) Method and apparatus for forming resist pattern
JPS60176236A (en) Resist processing device
JPH061759B2 (en) Method of forming resist pattern
JPS59132618A (en) Method and apparatus for forming resist pattern
JPH0480531B2 (en)
JPH0586642B2 (en)
JPS61147528A (en) Resist treating device
JPS60157225A (en) Resist pattern forming method
JPS60178626A (en) Formation of resist pattern and resist treater
EP0185366B1 (en) Method of forming resist pattern
JPS61180438A (en) Treating device for resist
JPS60117626A (en) Forming method of resist pattern and processing device for resist
JPH0142624B2 (en)
JPH0465524B2 (en)
JPS61147527A (en) Formation of resist pattern
JPS60157224A (en) Resist pattern forming method and resist treating apparatus
JPH045258B2 (en)
JPS60157223A (en) Resist pattern forming method and resist treating apparatus
JPH0464171B2 (en)
JPS60117625A (en) Forming method of resist pattern and processing device for resist
JPS6042829A (en) Formation of resist pattern
JPS60263431A (en) Forming method for resist pattern