JPS6021479A - Alarm timepiece - Google Patents

Abstract

PURPOSE:To put the multialarm functions to work by performing an audio signal with a fixed time range to enable the confirmation of an alarm setting time. CONSTITUTION:As the output time coincides with the current time, an audio data of a month counter 10 is fed to an audio signal generation circuit 68 which outputs an audio signal in voice through a signalling circuit 32 and then, a voice data of an ROM72 is fed to the circuit 68 to perform an audio signalling. Likewise, an audio data of a date counter 8 is fed to the circuit 68 while an audio data of the ROM72 is fed to the circuit 68 to output a specific voice. The operation of an audio circuit 58 ends and after 24hr, the same operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm clock, and particularly to one capable of prompting confirmation of alarm time setting.

In recent years, watches have been provided with a so-called alarm function that not only gives a notification every preset hour on the hour, but also gives a notification at a time arbitrarily set by the user.

As for the alarm function, a multi-alarm function has been proposed in which multiple alarm times can be set, and these watches are very convenient as they make it easy to manage personal time.

However, the above-mentioned alarm function, especially the multi-alarm function, has not been used very often in the past.

In other words, except for the alarm notification of the alarm clock, the alarm time to be set generally changes every day, and users, especially busy people who use the multi-alarm function, cannot set the alarm time. We forget.

The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide an alarm clock that does not remind the user to set the alarm time.

In order to achieve the above object, the present invention is characterized in that it is changeable and provides an audio notification to confirm the alarm time setting every 24 hours. The preferred embodiment will now be fully described.

FIG. 1 is a circuit block diagram of an alarm clock to which the present invention is applied.

The high frequency pulse outputted from the reference signal generator 2 is frequency-divided by a frequency dividing circuit 4, and a pulse train with a period of 1 second is supplied to a time counter 11 consisting of an hour counter 11, a day counter 81 and a month counter 10. .

The clock signal from the clock counter 11 is supplied to the display 14 via the decoder/driver 12 to display the time and date.

The current time signals 6a and 6b of the time counter 6 are still supplied to the coincidence detection circuit 16 and are constantly compared with the set alarm time. That is, the first alarm setting circuit 18 is connected to the -number output circuit 16. The alarm time signal set to the second alarm setting circuit 20 and the third alarm setting circuit 22 is also supplied, and when any of the alarm time signals and the current time signal match, a matching signal is supplied to the ring stop switch 23. The signal is supplied to the alarm signal generation circuit 25 via the AND gate 24. Therefore, if the ring stop switch 23 is in the closed state, an alarm signal is supplied from the alarm signal generation circuit 25 via the OR gate 26 to the notification circuit 32 consisting of the amplifier 28 and the speaker 30, and an alarm sound is notified. By opening to
You can stop the alarm sound notification. Therefore, each time the alarm time set in the alarm setting circuit 17 arrives, if the ring stop switch 23 is in the closed state, the notification circuit 32 will issue an alarm sound.

On the other hand, the output of the mode changeover switch 34 is supplied to a mode changeover circuit 36 composed of a ring counter or the like, and the output state of the mode changeover circuit 36 is changed over each time the switch 34 is operated. The outputs 36a-36e of the mode switching circuit 36 are supplied to AND gates 38-46, respectively, and the output of the correction switch 48 is also supplied to the AND gates 38-46.

That is, by operating the mode changeover switch 34, the output 36'
When the value is 1rHJ, the AND gate 38 is in an open state, and the correction signal from the correction switch 48 can be supplied to the first alarm setting circuit 18, so that the alarm time of the setting circuit 18 is set. Next, when the mode selector switch 34 is operated, the output 36b becomes "H" and the AND gate 40 is opened. In this case, the alarm time of the second alarm setting circuit 2 () is set by operating the correction switch 48. Ru.

Thereafter, each time the mode changeover switch 34 is operated, the AND gates 42 and 44 are opened, and the alarm time of the third alarm setting circuit 22 and the current time of the time counter 6 are respectively set by operating the correction switch 48.

The output of the AND gate 46 is output to an audio circuit 58 which will be described later.
The output time for outputting the operation start signal for Q operation is supplied to a settable setting circuit 50, and the setting circuit 50 is changed by operating the correction switch 48 when the output 36e is "1". In this embodiment, the AND gate 46 and the correction switch 48 constitute a changing means, and the correction switch 48 can also set an alarm time.The output time signal set in the setting circuit 50 is a combination of this signal, the current time signal, and the total time. It is supplied to a coincidence detection circuit 52 that constantly compares the output time signal, and when the output time signal and the current time signal coincide, the coincidence signal is supplied to a trigger circuit 54 to prompt the generation of a single pulse operation start signal.

In this embodiment, the above-mentioned setting circuit 50. - The operation start signal generation circuit 56 is composed of the number output circuit 52 and the trigger circuit 54.

On the other hand, the audio circuit 58 that starts operating when the operation start signal is output is a quinary counter 60. Delay circuit 62. Flip-flop (hereinafter referred to as FF) 64, AND gate 6
6. The audio signal generation circuit 68 is composed of an 8° switching circuit 70 and an audio data ROM 72, and will be described in detail below.

The data input terminal of the switching circuit 70 is supplied with audio data from a day counter 8, a monthly counter 10, and an audio data ROM 72, and corresponds to the count value of the quinary counter 60, which is simultaneously supplied to the control terminal of the switching circuit 70. The generated audio data is supplied to the audio signal generation circuit 68. That is, when the output 60a is "H", the audio data of the month counter 10 is output, and when the output 60'b is "H", the audio data is RO, M7.
The audio data from the output cuff 2a is output from the output 60c or ra.
At JO time, the audio data of day counter 8 and output 60
When d is "H", the audio data from the output cuff 2b of the voiced data ROM 72 is supplied to the audio signal generation circuit 68. The audio signal generation circuit 68 generates audio RO based on the audio data.
A start address and an end address for accessing a digital signal stored in M (not shown) are determined, and an analog audio signal is entirely formed based on the digital signal accessed by the address pulse and sent through an OR gate 26. The signal is supplied to the notification circuit 32.

Further, the operation start signal from the operation start signal generation circuit 56 is 5.
It is supplied to the set terminal S of the FF 64 via the reset terminal R of the forward counter 60 and the delay circuit 62. and F
The Q output of F64 is supplied to an AND gate 66, and via this AND gate 66, the address pulse φσ from the frequency dividing circuit 4 is supplied to the clock input terminal φ of the audio signal generation circuit 68. When the address is counted by the end address ox, an end signal is generated at the output 68a and supplied to the clock input terminal φ of the quinary counter 60, and the counter 60 is incremented by one step. The final count output 60e of the quinary counter 60 is supplied to the reset terminal R of the FF 64.

The operation will be explained below using the time chart shown in FIG.

First, when the output time and the current time match, an operation start signal is generated at the output 54a, which causes the output 60a to rHJ
At the same time, the output 60e becomes "L", the reset of the FF 64 is released, and the audio data of the month counter 10 is supplied to the audio signal generation circuit 68. Thereafter, a delayed operation start signal is also generated at the output 62a, the Q output of the FF 64 becomes rHJ, and the address pulse φ is applied to the audio signal generation circuit 68.
・Supply. As a result, an audio signal is supplied to the notification circuit 32, and a sound of "7", for example, is announced.

Then, when the end signal is generated at the output 68a, the quinary counter 60 is incremented by one step and the output 60b becomes rHJ. At this time, the audio data in the output cuff 2a of the audio data ROM 72 is supplied to the audio signal generation circuit 68 and becomes "month". Audio will be announced. Similarly, when the output 60c becomes ``rn'', the audio data of the day counter 8 is supplied to the audio signal generation circuit 68 and, for example, the audio ``7J'' is announced. The data is supplied to the audio signal generation circuit 68, and a voice message saying "It's Sunday. Please set the scheduled time." is announced. Then, when the end signal is generated at the output 68a, the quinary counter 60 is set to 1.
It is stepped and the output 60e becomes rHJ, and the Q output of the FF 64 becomes "L". Therefore, the supply of the address pulse φ is stopped, and the operation of the audio circuit 58 is completed. and 24
After a period of time, the operation start signal is output again and the audio circuit 58 operates in the same manner, and thereafter operates every 24 hours.

As described above, according to this embodiment, the operation start signal generation circuit 56
When the operation start signal is output from , the audio circuit 58 is activated and [Y/N]. Since the user is notified of the scheduled time by voice over a certain period of time, the user can set the schedule for the day without forgetting.

Furthermore, the operation start signal for operating the audio circuit 58 can be easily changed, and the audio circuit 58 can be activated at a time of the user's preference.
It has the effect of being able to operate 8. Furthermore, in this embodiment, since the date is also notified at the time of the voice notification, it becomes like a calendar, and has the effect of making it easier to set the alarm time.

As explained above, the present invention prevents the user from forgetting to set the alarm time by giving a voice notification of a fixed duration that is changeable and that allows the user to confirm the alarm time setting every 24 hours. In this way, the alarm function, especially the multi-alarm function, is utilized.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an alarm clock to which the present invention is applied. FIG. 2 is a time chart showing the operation of the audio circuit 58 according to FIG. 1. 17... Alarm setting circuit, 25... Alarm signal generation circuit, 32... Notification circuit, 46... AND gate 48.
- Correction switch 56...operation start signal generation circuit, 58...audio circuit. that's all

Claims (1)

[Claims] (1) An alarm setting circuit that can set at least one alarm time, an alarm signal generation circuit that generates an alarm signal when the set value of the alarm setting circuit matches the current time, and an alarm signal generation circuit that generates an alarm signal when the alarm signal is supplied. an alarm clock having a notification circuit that operates to notify an alarm sound, an audio circuit that supplies an audio signal of a certain time width to the notification circuit for confirming the alarm time setting, and the audio circuit every 24 hours. An operation start signal generation circuit that outputs an operation start signal for operating the operation start signal, and a changing means that can change the time at which the operation start signal is output are provided. Features an alarm clock.