JPS60214128A - Automatic threshold value adjusting circuit - Google Patents

Automatic threshold value adjusting circuit

Info

Publication number
JPS60214128A
JPS60214128A JP59071618A JP7161884A JPS60214128A JP S60214128 A JPS60214128 A JP S60214128A JP 59071618 A JP59071618 A JP 59071618A JP 7161884 A JP7161884 A JP 7161884A JP S60214128 A JPS60214128 A JP S60214128A
Authority
JP
Japan
Prior art keywords
reference voltage
input
circuit
level
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59071618A
Other languages
Japanese (ja)
Inventor
Yuji Ogawa
小川 裕士
Katsuhiko Oimura
老邑 克彦
Kazuaki Urasaki
浦崎 一明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Tateisi Electronics Co
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tateisi Electronics Co, Omron Tateisi Electronics Co filed Critical Tateisi Electronics Co
Priority to JP59071618A priority Critical patent/JPS60214128A/en
Publication of JPS60214128A publication Critical patent/JPS60214128A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/062Setting decision thresholds using feedforward techniques only

Abstract

PURPOSE:To adjust a threshold value with high accuracy by providing a reference voltage lower than a non-signal level of an input signal and a reference voltage higher than the signal level and holding the peak of an intermediate level between the low reference voltage and the input signal to process the result. CONSTITUTION:The 1st reference voltage outputted from a reference voltage source 11 is lowered than the non-signal level of a point A applied and the 2nd reference voltage at a point C is set while being increased for the share. The intermediate level between voltages between points A, B is subjected to peak hold by a peak hold circuit 12, a voltage at an output point D and a voltage at the point C are applied to an inverting input of a comparator 14 and the input signal is applied to a noninverting input of the comparator 14. The comparator 14 is provided with transistors (TRs) 15, 16, 17, the TRs 16, 17 are connected in parallel and the voltage at the points D, C is inputted individually. Thus, even if an error of fluctuation exists in the non-signal input level and the reference voltage, since the effective input level at the inverting input of the comparator 14 is not so much spaced away from an ideal value, the threshold value with high accuracy is obtained.

Description

【発明の詳細な説明】 (イ)発明の分野 この発明は、光伝送の受信回路等に使用される自動しき
い値調整(ATC)回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of the Invention The present invention relates to an automatic threshold adjustment (ATC) circuit used in an optical transmission receiving circuit or the like.

(ロ)発明の背景 一般に、光伝送の受信回路においては、種々のレベルの
入力信号からきれいな受信データの出力波形を得るため
に、入力信号のレベルに応じてしきい値を変化させるA
TC回路が使用される。
(B) Background of the Invention In general, in optical transmission receiving circuits, in order to obtain a clean output waveform of received data from input signals of various levels, a threshold value is changed according to the level of the input signal.
A TC circuit is used.

従来より使用されるATC回路を、第1図に示している
。このATC回路は、入力信号iの電圧レベル(A点の
)と基準電圧源1のB点から出力される電圧の差電圧を
抵抗R1、R2で2に分割し、ピークホールド回路2で
ピークホールドし、この出力をオア回路3を介して比較
器4の(=)入力端に加える一方、基準電圧源1の点C
より、点Bよりも大なる基準電圧を出力し、この基準電
圧をオア回路3を介して比較器4の(−)入力端に加え
るようにし、しきい値電圧を比較器4に与えている。こ
のATC回路においては、B点の基準電圧を無信号時の
A点のレベルと同値となるように設定しており、入力信
号がある値より小さい間は、ピークホールド回路2の出
力すなわちD点のレベルが0点の基準電圧よりも小さい
ので、この間は比較器4の(−)入力端に0点の一定レ
ヘルの基準電圧がオア回路3を介して加えられ、入力信
号があるレベルを越えると、ピークボールド回路2の出
力が0点の基準電圧を越えるので、このピークホールド
値がし°きい値電圧としてオア回路3を介して比較器4
の(−)入力端に入力される。このピークホールド回路
2の出力は、入力信号レベルの上昇とともに大きくなる
ので、入力信号があるレベルを越えると、入力信号に応
したしきい値が比較器4に入力されることになる。
A conventionally used ATC circuit is shown in FIG. This ATC circuit divides the difference voltage between the voltage level of input signal i (at point A) and the voltage output from point B of reference voltage source 1 into two parts using resistors R1 and R2, and holds the peak using peak hold circuit 2. This output is applied to the (=) input terminal of the comparator 4 via the OR circuit 3, while the point C of the reference voltage source 1 is applied to the (=) input terminal of the comparator 4.
Therefore, a reference voltage greater than point B is output, and this reference voltage is applied to the (-) input terminal of the comparator 4 via the OR circuit 3, thereby providing a threshold voltage to the comparator 4. . In this ATC circuit, the reference voltage at point B is set to be the same value as the level at point A when there is no signal, and while the input signal is smaller than a certain value, the output of peak hold circuit 2, that is, point D Since the level of is lower than the reference voltage at the 0 point, during this period, the constant level reference voltage at the 0 point is applied to the (-) input terminal of the comparator 4 via the OR circuit 3, and the input signal exceeds a certain level. Since the output of the peak bold circuit 2 exceeds the reference voltage at the 0 point, this peak hold value is passed through the OR circuit 3 to the comparator 4 as the threshold voltage.
is input to the (-) input terminal of. Since the output of the peak hold circuit 2 increases as the input signal level increases, when the input signal exceeds a certain level, a threshold value corresponding to the input signal is input to the comparator 4.

しかし、この従来のATC回路は、ピークホールド回路
出力と基準電圧のオアを取るのが非常に困難であるとい
う欠点があり、この欠点を解消するため、この出願の発
明者等は、オア回路を用いないATC回路を含む受信回
路を別に出願した。
However, this conventional ATC circuit has the drawback that it is very difficult to OR the peak hold circuit output and the reference voltage.In order to overcome this drawback, the inventors of this application developed an OR circuit. A separate application was filed for a receiving circuit that includes an unused ATC circuit.

この別出願に係るATC回路を第2図に示している。The ATC circuit according to this separate application is shown in FIG.

第2図に示すATC回路は、第1の基準電圧(B点)と
第2の基準電圧源(0点)を出力する基準電圧源11、
電圧分割用の分圧抵抗R1l・R12、ピークホールド
回路12、比較器14を備える点で第1図に示す回路と
同様であるが、オア回路を省略した点、比較器14ば3
個のトランジスタ15.16.17を備え、このうち2
個のトランジスタ16.17は並列接続され、がっ両ベ
ースにピークホールド回路12の出力と基準電圧源11
よりの第2基準電圧を個別に入力している点で特徴を有
するものである。
The ATC circuit shown in FIG. 2 includes a reference voltage source 11 that outputs a first reference voltage (point B) and a second reference voltage source (point 0);
It is similar to the circuit shown in FIG. 1 in that it includes voltage dividing resistors R1l and R12 for voltage division, a peak hold circuit 12, and a comparator 14, but the OR circuit is omitted and the comparator 14 and 3
transistors 15, 16, and 17, of which 2
The transistors 16 and 17 are connected in parallel, and the output of the peak hold circuit 12 and the reference voltage source 11 are connected to both bases.
This method is characterized in that the second reference voltages are input individually.

このATC回路において、入力信号の変化に対する回路
各部の電圧レベルを示すと、第3図の通りとなる。図に
示すように、ピークホールド回路12の出力(D点)の
レベルは、−見すると無信号時にB点と等しく、入力信
号の上昇とともに直線的に上昇するかのようであるが、
比較器14の(−)入力端側には、2個のトランジスタ
16.17が並列に接続されており、その分トランジス
タ15よりも大なる電流が流れるため、実効的な比較器
14の(−)入力端例の入力は破線D゛で示すものとな
る。
In this ATC circuit, the voltage levels of various parts of the circuit with respect to changes in the input signal are shown in FIG. As shown in the figure, the level of the output of the peak hold circuit 12 (point D) is equal to the level of point B when there is no signal when viewed from below, and appears to rise linearly with the rise of the input signal.
Two transistors 16 and 17 are connected in parallel to the (-) input end of the comparator 14, and a larger current flows therethrough than that of the transistor 15, so that the effective (-) ) The input of the input terminal example is shown by the broken line D.

また第3図は、基準電圧、入力電圧に誤差のない場合を
示しているが、実際には無信号詩人カ信号レベルや基準
電圧には誤差があるのが通常であり、これらに誤差があ
る場合の第2図回路の回路各部の電圧レベルを第4図に
示している。同図において、Amax、 Am1nはそ
れぞれ基準電圧に対して入力電圧(A点のレベル)が+
側、−例にずれた場合のピーク値である。Dmaχ、D
minは、それぞれAmax、 Am1nに対応するピ
ークホールド回路12の出力電圧である。またEmax
、、 Eminは実効的な比較器の(−)入力端の入力
であり、D’may 、D’minはそれぞれ軸ax、
、Am1nに対する理想的なピークホールド回路の出力
電圧である。Emax、 EminはD’ max 、
 D’minにより接近することが望ましいが、ここで
はEmaxがD’ maxに比較的近接しているが、l
EminがD’ minにかなり離れている。
Also, Figure 3 shows a case where there is no error in the reference voltage and input voltage, but in reality there is usually an error in the no-signal output signal level and the reference voltage, and there are errors in these. FIG. 4 shows the voltage levels of various parts of the circuit of FIG. 2 in this case. In the same figure, Amax and Am1n each have an input voltage (level at point A) of + with respect to the reference voltage.
This is the peak value when the value shifts to the negative side. Dmaχ,D
min is the output voltage of the peak hold circuit 12 corresponding to Amax and Am1n, respectively. Also Emax
, Emin is the input of the (-) input end of the effective comparator, and D'may and D'min are the axes ax and D'min, respectively.
, Am1n is the ideal peak hold circuit output voltage. Emax, Emin is D' max,
It is desirable to be closer to D'min, but here Emax is relatively close to D'max, but l
Emin is quite far from D'min.

一般的には、人力の振幅に対して上記誤差は無視できる
が、入力信号に対して無信号入力レベルと基準電圧の誤
差が大きい場合には、特にAm1nに対するEminを
よりD’minに近づけることが要請される。
Generally, the above error can be ignored for the amplitude of human power, but if the error between the no-signal input level and the reference voltage is large for the input signal, Emin for Am1n should be closer to D'min. is requested.

(ハ)発明の目的 この発明の目的は、上記に鑑み、ピークボールド回路出
力と基準電圧のオアを比較器の外部で取る必要のない、
しかも無信号入力レベルと基準電圧に誤差が生じても、
精度よ(しきい値を調整し得るATC回路を提供するこ
とである。
(c) Purpose of the Invention In view of the above, the purpose of the present invention is to eliminate the need to OR the peak bold circuit output and the reference voltage outside the comparator.
Moreover, even if there is an error between the no-signal input level and the reference voltage,
The objective is to provide an ATC circuit with adjustable thresholds.

(ニ)発明の構成と効果 上記目的を達成するために、この発明の自動しきい値調
整回路は、ピークホールド電圧を得る分割抵抗の接続さ
れる基準電圧源を無信号入力レベルよりも低く設定する
ようにしている。すなわちこの発明の自動しきい値調整
回路は、入力信号の無信号レベルよりも低い第1の基準
電圧と、この第1の基準電圧よりも高い第2の基準電圧
とを出力する基準電圧源と、前記入力信号と前記第1の
基準電圧の中間レベルを導出する電圧分割手段と、この
電圧分割手段よりの電圧のピーク値を保持するピークホ
ールド回路と、前記入力信号を一方の入力端に受け、他
方の入力端に前記ピークホールド回路の出力と前記第2
の基準電圧を個別に受ける比較器とから構成される装置 この発明の自動しきい値調整回路によれば、比較器の外
部にオア回路を設ける必要がなく、また無信号入力レベ
ルと基準電圧に変動誤差が生じても、比較器のく−)入
力端の★動的な入力レベルが理想値から余り離れないの
で、精度の良いしきい値を得ることができる。
(d) Structure and Effect of the Invention In order to achieve the above object, the automatic threshold adjustment circuit of the present invention sets the reference voltage source connected to the dividing resistor for obtaining the peak hold voltage to be lower than the no-signal input level. I try to do that. That is, the automatic threshold adjustment circuit of the present invention includes a reference voltage source that outputs a first reference voltage that is lower than the no-signal level of an input signal and a second reference voltage that is higher than the first reference voltage. , a voltage dividing means for deriving an intermediate level between the input signal and the first reference voltage, a peak hold circuit for holding the peak value of the voltage from the voltage dividing means, and receiving the input signal at one input terminal. , the output of the peak hold circuit and the second
According to the automatic threshold adjustment circuit of the present invention, there is no need to provide an OR circuit outside the comparator, and it is possible to adjust the no-signal input level and the reference voltage. Even if a fluctuation error occurs, the dynamic input level at the input end of the comparator does not deviate much from the ideal value, so a highly accurate threshold can be obtained.

(ホ)実施例の説明 次に、この発明の実施例について説明する。(e) Description of examples Next, embodiments of the invention will be described.

この発明の1実施例ATC回路の回路構成は、第2図に
示すものと略同様である。
The circuit configuration of an ATC circuit according to one embodiment of the present invention is substantially the same as that shown in FIG.

この実施例回路は、回路各部の電圧レベルを第4図に示
した先願に係る回路に比し、基準電圧源11より出力さ
れる第1の基準電圧すなわちB点の電圧を入力信号の印
加されるA点の無信号入力レベルよりも低くなるように
設定し、その分第2の基準電圧すなわち0点の電圧を持
ち上げている点で特徴を有する。
This embodiment circuit differs in that the voltage level of each part of the circuit is different from that of the circuit according to the prior application shown in FIG. The second reference voltage, that is, the voltage at point 0, is raised by that amount.

このように基準電圧源11の基準電圧を設定することに
より、入力電圧に対する回路各部の電圧レベルは第5図
に示すようになる。
By setting the reference voltage of the reference voltage source 11 in this way, the voltage level of each part of the circuit with respect to the input voltage becomes as shown in FIG.

この図より明らかなように、B点のレベルをより低くす
ることにより、第4図に比べEminがD’minに接
近していることがわかる。逆に、EmaxとD’may
の差が大入力側で大きくなっているが、大入力になれば
ATCレベルの影響は小さくなるので、特にB題はない
As is clear from this figure, by lowering the level at point B, Emin approaches D'min compared to FIG. 4. On the contrary, Emax and D'may
The difference between the two becomes large on the large input side, but as the input becomes large, the influence of the ATC level becomes smaller, so there is no particular B problem.

なお、第2図に示す実施例回路において、比較器のトラ
ンジスタはNPN型を使用し、入力信号は正側に振れる
場合を想定したが、トランジスタはPNP型を使用して
もよいし、また入力信号が負側に振れる場合にも、この
発明が適用できるこというまでもない。
In the example circuit shown in Fig. 2, an NPN type transistor is used for the comparator transistor, and it is assumed that the input signal swings to the positive side. However, a PNP type transistor may be used, and the input signal It goes without saying that the present invention is applicable even when the signal swings to the negative side.

また、比較器のトランジスタはバイポーラトランジスタ
を使用した例を示したが、これに代えてFETを用いて
もよい。FET使用の場合は、実効電位差を上げるのに
チャネル幅を変化させればよい。
Further, although an example is shown in which a bipolar transistor is used as the transistor of the comparator, an FET may be used instead. When using FETs, the channel width can be changed to increase the effective potential difference.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のATC回路を示す回路構成図、第2図は
この発明に先行する発明及びこの発明が実施されるAT
C回路を示す回路構成図、第3図は第2図に示す回路の
入力信号を変化させた場合の回路各部の電圧レベルを示
す図、第4図はこの発明に先行するATC回路において
、無信号入力レベルと基準電圧の誤差を考慮し、入力信
号を変化させた場合の回路各部の電圧レベルを示す図、
第5図はこの発明の実施例ATC回路において、無信号
入力レベルと基準電圧の誤差を考慮し、入力信号を変化
させた場合の回路各部の電圧レベルを示す図である。 11:基準電圧源、12:ピークホールド回路、14:
比較器、R11・R12:分圧抵抗、15・16・17
:トランジスタ。 特許出願人 立石電機株式会社 代理人 弁理士 中 村 茂 信 第1図
FIG. 1 is a circuit configuration diagram showing a conventional ATC circuit, and FIG. 2 is an AT circuit diagram showing an invention prior to this invention and an AT in which this invention is implemented.
FIG. 3 is a diagram showing the voltage level of each part of the circuit when the input signal of the circuit shown in FIG. 2 is changed. FIG. A diagram showing the voltage level of each part of the circuit when the input signal is changed, taking into account the error between the signal input level and the reference voltage.
FIG. 5 is a diagram showing the voltage levels of various parts of the circuit when the input signal is changed in consideration of the error between the no-signal input level and the reference voltage in the ATC circuit according to the embodiment of the present invention. 11: Reference voltage source, 12: Peak hold circuit, 14:
Comparator, R11/R12: voltage dividing resistor, 15/16/17
:Transistor. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)入力信号の無信号レベルよりも低い第1の基準電
圧と、この第1の基準電圧よりも高い第2の基準電圧と
を出力する基準電圧源と、前記入力信号と前記第1の基
準電圧の中間レベルを導出する電圧分割手段と、 この電圧分割手段よりの電圧のピーク値を保持するピー
クホールド回路と、 前記入力信号を一方の入力端に受け、他方の入力端に前
記ピークホールド回路の出力と前記第2の基準電圧を個
別に受ける比較器とからなる自動しきい値調整回路。
(1) a reference voltage source that outputs a first reference voltage lower than the no-signal level of an input signal and a second reference voltage higher than the first reference voltage; a voltage dividing means for deriving an intermediate level of the reference voltage; a peak hold circuit for holding the peak value of the voltage from the voltage dividing means; one input terminal receiving the input signal and the other input terminal receiving the peak hold circuit; An automatic threshold adjustment circuit comprising a comparator that individually receives the output of the circuit and the second reference voltage.
JP59071618A 1984-04-09 1984-04-09 Automatic threshold value adjusting circuit Pending JPS60214128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59071618A JPS60214128A (en) 1984-04-09 1984-04-09 Automatic threshold value adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59071618A JPS60214128A (en) 1984-04-09 1984-04-09 Automatic threshold value adjusting circuit

Publications (1)

Publication Number Publication Date
JPS60214128A true JPS60214128A (en) 1985-10-26

Family

ID=13465813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59071618A Pending JPS60214128A (en) 1984-04-09 1984-04-09 Automatic threshold value adjusting circuit

Country Status (1)

Country Link
JP (1) JPS60214128A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846717A (en) * 1981-09-14 1983-03-18 Nec Corp Pulse shaping circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846717A (en) * 1981-09-14 1983-03-18 Nec Corp Pulse shaping circuit

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