JPS60214033A - Signal generation device - Google Patents

Abstract

PURPOSE:To shift optionally a signal in phase by adding an adder for shifting, shift mode selecting circuit, and storage command generating circuit to the signal generating device. CONSTITUTION:When a shift command signal is not supplied to an input terminal 26, a data switch 21 supplies the contents of the adder to an integrating register 14, whose contents are supplied as an address signal to a waveform storage device 15 to read stored data out of a corresponding address, so that the data is outputted through a DA converter 16 and a low-pass filter 17. When the shift command signal is supplied to the input terminal 26, the storage command generating circuit 24 supplies the signal of the adder 25 for adding to the integrating register 14 through a data switch 21. When a shift in phase is made, an H signal is supplied to an input terminal 25. The adder 23 for shifting adds the output value of the integrating register 14 when the shift signal is supplied to the relative value set in a phase setting register 12 and supplies the sum to the data switch 21.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention can set the initial phase of a signal, and also allows the phase of a generated signal to be shifted to a specific value at any time,
Alternatively, the present invention relates to a digital synthesized signal generator that can be deviated by a certain relative value.

<Description of Prior Art> Fig. 1 shows a patent application filed in 1982-165 previously disclosed by the present applicant.
A professional diagram of a signal generating device that generates a signal from a set initial phase value described in No. 768 is shown.

At the start of operation, the value set in the phase setting register 12 is preset to the preset terminal of the integration register 14.

The value stored in the integration register 14 is supplied to one terminal of the adder 13, and the other terminal is connected to the frequency setting register 11. The stored value of the integration register 14 is added to the adder 13 for each clock signal from the black/7 line terminal 18.
The stored value is then supplied to the waveform memory 15 as an address signal. The waveform memory 15 sends out the data stored at the address corresponding to the output signal from the integration register 14 for each clock signal. A series of digital signals from the waveform memory 15 are converted into analog values by a digital-to-analog converter (hereinafter referred to as a DA converter) 16, smoothed by a low-pass filter 17, and output from an output terminal 19. .

Now, if we set the maximum integrated value of the integration register 14 as 2N, the clock frequency as f8, and the setting value of the frequency setting register 11 as K, then from the output terminal 19, 2゜ and when we set the digital value A in the phase setting register 12. , by dividing one cycle into 2M and storing this in the waveform memory 15, a signal whose initial phase value is advanced by □×360° can be obtained.

However, with the apparatus of FIG. 1, it is not possible to precisely deviate the phase of the signal being generated to a specific value at any given time, or to deviate it by a relative value.

<Object of the Invention> The present invention is capable of setting the initial phase value of a signal, and also of making it possible to accurately deviate the phase of a signal being generated to a certain specific value at any time, or to deviate it by a certain relative value. The purpose of the present invention is to provide a signal generating device that can.

<Summary of the Invention> The present invention adds a deviation adder, a deviation mode selection circuit, and a storage command generation circuit to the signal generation device shown in FIG.
When a deviation command signal is given from the outside, the storage command generation circuit outputs the setting value of the phase setting register, or the setting value of the phase setting register and the output value of the integration register through the deviation adder according to the deviation mode selection signal. The added value of the sum of the sum and the sum is set in the accumulation register.

<Embodiment of the Invention> An embodiment of the invention is not shown in FIG. In the figure, the same parts as in FIG. 1 are indicated by the same symbols. 21 is a data switcher, 22 is a deviation mode selection circuit, 23 is a deviation adder, 24 is a storage command generation circuit, 25 is a deviation mode selection signal input terminal, 2
6 is a deflection command signal input terminal.

The clock signal is written as the integration register 14 and the command generation circuit 2
4 is supplied. When the deviation command signal is not given from the deviation command signal input terminal 26, the data switch 2
1 supplies the contents of the adder 13 to the accumulation register 14. That is, for each clock signal, the contents of the integration register 14 are added by the value set in the frequency register 11.
This signal is supplied to the waveform memory 15 as an address signal, and the data stored at the corresponding address is read out.
A converter 16 converts it into an analog value, and low-pass filter 1
7.

When a deviation command signal is applied from the deviation command signal input terminal 26, the storage command generation circuit 24 gives a control signal to the data switch 21 so as to supply the signal of the deviation adder 23 to the integration register 14.

Here, when the phase is to be shifted to a specific value, the deviation (for example, an L signal is input to the negative mode selection input terminal 25, and the phase setting register 1 is
2 is set to the above specific value. At this time, the deviation mode selection circuit 22 outputs zero, so the value set in the phase setting register 12 is the value set in the deviation adder 23 and the data switch 2.
1 to the integration register 14. Thereafter, the data switch 21 is switched to the adder 13 side and outputs an analog waveform.

When the phase is to be shifted by a relative value, for example, an H signal is set to the shift mode input terminal 25, and the above relative value is set to the phase setting register 12. At this time, the deviation mode selection circuit 22
supplies the output value of the integration register 14 when the deviation command signal is given to the deviation adder 23, and the deviation adder 23 outputs the output value of the integration register 14 when the deviation signal is given. and the relative value set in the phase setting register 12 are added and supplied to the data switch 21. Therefore, the output terminal 19 generates a signal whose phase is advanced by the value set in the phase setting register 12 at the time when the deviation command signal is applied.

When setting the initial phase of a signal, the data switch 21 is switched to the deviation adder 23 side when the signal is generated, and zero is output from the deviation data selection circuit 22.

By doing so, the setting value of the phase setting register 12 is taken into the integration register 14, and initial phase setting is performed. Thereafter, the data switch 21 is switched to the adder 13 side to generate a signal of the frequency set by the frequency setter 11.

The operation of changing the phase of a signal being generated midway will be explained using the timing chart of FIG. 3 and the waveform diagram of FIG. 4. A is a clock signal input from the clock input terminal 18. B is a signal input to the deflection command signal input terminal 26.

C is the output value of the phase setting register 12, for example, the angle θ is set in the phase setting register 12. When 2M is set, waveform 1. This is the amount of data stored in the recording device 15 for one cycle of the stored waveform. Do and Dl are output values of the deviation adder 23. Do is the output value when a signal that shifts the phase to a specific value, for example, an L signal, is applied to the deflection mode signal input terminal 25, and the output of the deflection mode selection circuit 22 is zero, so C
will be equal to 8. Dl is the output value when a signal that shifts the phase by a relative value, for example, an H signal, is applied, and when the deflection command signal I-J is received from the deflection command signal input terminal 26, the signal selection circuit 22 integrates The output value of the register 14 is supplied to the deviation adder 23. Therefore, the output value of the deviation adder 23 is the sum of the output value of the integration register 14 and the setting value of the phase setting register 12. When the deflection command signal P is input from the deflection command signal input terminal 26, 1. The switching control signal E from the program command generation circuit 24 rises, and the data switch 21 supplies the output of the deviation adder 23 to the integration register 14. For example, as shown in FIG. 3F from the integration register 14, f, ,
--, when the deviation command signal P is input while the output values of f n-1, f, , are being generated, the switching control signal E rises and the data switch 21 switches to the deviation adder. 23 is supplied to the integration register 14. This output value F1 is co when the deviation mode signal is an L signal, and becomes fI, +C when it is an H signal. When the clock signal becomes an L signal, the switching control signal also becomes an L signal, and the data switch 21 is switched to the adder 13. From then on, the adder 13 is switched to the adder 13 for each clock signal until a deviation command signal is received. The output value of the integration register 14 and the set value of the frequency setting register 11 are repeatedly added and supplied to the integration register 14 again, and F I, F z , "-'-'-'- are sequentially stored in the waveform memory 15. is supplied to

FIG. 4 shows an output waveform when a deflection command signal is applied when a sine wave is stored in the waveform storage circuit. In A, the initial phase value is 0° and the phase is shifted to a specific value of 0'' at the α point of 90°, and in B, the initial phase value is O
8 points having a phase of 90° are relatively shifted by 90°.

As described above, the phase of the signal being generated can be shifted to a certain specific value at any time, or by a certain relative value.

Note that an address setting section and a random access memory (hereinafter referred to as RAM) are provided as the phase setting register 12, and a plurality of data are stored in the RAM, and desired data is stored in the RAM through the address setting section. You may also specify the address where the address is located.

Also, when a deviation command signal is given, the DA converter 1
6 may be directly output from the output terminal 19 without passing through the low-pass filter 17.

<Effects of the Invention> As explained above, according to the present invention, it is possible not only to set the initial phase of a signal, but also to accurately deviate the phase of a generated signal to a specific value at any time, Alternatively, a signal generator can be obtained which can be deviated by a certain relative value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional signal generator, FIG. 2 is a block diagram of a signal generator according to the present invention, and FIG. 3 is a block diagram of a signal generator according to the present invention.
FIG. 4 is a timing chart for explaining the operation of the signal generating device shown in the figure, and FIG. 4 is a diagram showing an example of an output waveform when the signal generating device according to the present invention is used. 11: Frequency setting register, 12: Phase setting register, 13: Adder, 14: Integration register, 15: Waveform memory, 16: Digital-analog converter, 17: Low-pass filter, 18: Cloth input terminal, 19: output terminal, 21: data switcher, 22: deviation data selection circuit, 23: deviation adder, 24: storage command generation circuit, 25: deviation mode selection signal input terminal, 26: deviation command signal Input terminal, patent applicant Takeda Riken Kogyo Co., Ltd.

Claims (1)

[Claims] ill A, a frequency setting register, a B9 phase setting register, a C0 integration register, D, an adder for adding the data of the frequency setting register and the data of the integration register, E, deviation. command means; F. deflection mode command means; G; a deflection mode selection circuit that transmits zero or data of the integration register in response to a signal from the deflection mode command means; H0 data of the phase setting register. and a deflection adder for adding data from the deflection mode selection circuit; (2) supplying data from the adder or the deflection adder to the integration register in response to a signal from the deflection command means; A data switch; J. A waveform memory that receives the signal of the integration register as an address signal and generates the data written in each address; K. Converts the output signal of the waveform memory into an analog value. A signal generating device comprising: a digital-to-analog conversion 2=;