JPS6021366B2 - Camera shooting information display circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for displaying photographic information of a camera, and in particular, from a so-called dot system in which a predetermined display in a display column of numbers, symbols, etc. is displayed by emitting light, to a segment light-emitting display of numbers, signals, etc. The present invention relates to a device that performs display by switching to a so-called segment method in which display is performed using elements.

In recent years, it has become common to display various information such as shooting speed and aperture in the viewfinder of a camera.

This display method includes a dot method and a segment method. In the dot method, for example, each shirt speed value of the camera is displayed along the side of the viewfinder, and a light emitting diode is placed next to each value display or beside the display mask to control exposure. The output of the circuit causes one of the light emitting diodes to emit light. this is,
Since the light emitting position corresponds to the displayed value, it has the advantage that you can roughly know the displayed value based on the position without having to read the numbers themselves, but on the other hand, it requires a large number of light emitting diodes, which takes up a considerable amount of space. This has the disadvantage that it also affects the viewfinder field of view. On the other hand, the segment method performs display using so-called 7-segment elements, and although it yields a step to the dot method in terms of ease of recognition, it is also capable of handling an amount of information per digit and is space-efficient. It has the advantage of being able to display numerical values themselves.

When it comes to choosing between the dot method and the segment method for cameras that require a large number of displays, the current trend is toward the segment method. Here, even if the segment method is adopted, it is convenient to configure the circuit based on the dot method, which has been the mainstream in the past, and then switch to the segment method as necessary. Here, the segment method is used to display numbers and symbols using the shape of segment elements. By blinking these in addition to the above-mentioned display, it is possible to perform many types of display at the same time using the same element. There is a need for a technique for displaying a blinking segment display element using a dot display signal that is the basis of segment display.

The present invention has been made in view of the above-mentioned points, and provides a photographic information display circuit for a camera that obtains a blinking signal for displaying dots and generates a signal that causes a segment display element to blink.

An embodiment of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 shows an embodiment of the present invention.

This circuit is designed to blink the segment display element by receiving two types of signals T, ~T8 and So~S3 formed for dot display.
It forms three signals of mountain 3. In this case, in order to display the dots dynamically, T, ~T6, and So~S3 are selected to have a frequency that appears to be continuous lighting to human vision, for example, 64Hz;
~T8 mutually and So~S〆 mutually are out of phase. The reason why there are 8 T signals and 4 S signals is that 32 dot display light emitting diodes are connected to the anode side,
This is because the light emission of 32 diodes is controlled by 12 signals divided into 4 groups and 8 groups on the cathode side. The T signal always appears at the same period, but the S signal changes in, for example, three ways. This corresponds to three conditions, for example, when the exposure is outside the appropriate exposure range, when the LED corresponding to the aperture value or shutter value is off (when the power supply voltage drops), and when it is outside the shooting limit, and each flashes at 8Hz. display, 4 days 2 blinking display, and lights out. In the illustrated embodiment, three force counters COUT, , COUT2, and
The S signal is supplied to COUT3 for counting, while the S signal is used to control the counting of these counters.

The outputs of these counters are the three flip-flop FFs,
, FF2, FF3 and AND circuits AND7, AND8
Output signals OUT1, OUT2 are output through an output circuit consisting of
, OUT3. These outputs are then applied to the segment display element via a decoder circuit (not shown) to display inappropriate exposure, low power supply voltage, and to turn off the light to indicate that the photographing limit is exceeded.

Figure 2 shows the input signals T, S and T in the circuit of Figure 1.
This figure shows the waveform of a clock signal formed based on the signal, and the configuration and operation of the circuit of FIG. 1 will be explained below based on the signal of FIG. 2.

Here, the signals T and S are "0" when a signal is present and "1" when there is no signal. The signals L to T become the clock signal CLK via the NAND circuits NAND, , NAND2 and the OR circuit OR.

If the t to T8 signals are, for example, Okae and have an appropriate phase difference from each other, a clock signal CLK of 8 HZ is obtained, which is applied to the counter COUT. Counter COUT,
is composed of seven stages of flip-flops, and the outputs of the third, fourth, and fifth stages are connected to the input of an AND circuit AND. Therefore, the AND circuit AND,
produces an output signal when counter COUT counts 28 clock signals CLK. The output of the sixth stage of the counter COUT is connected to one input of an AND circuit AND2, and the other input of the AND circuit AND2 is connected to the output of the AND circuit AND. Therefore, the AND circuit AND2 produces an output signal when the counter COUT receives a fixed count of 6 on the clock signal. Further counter COU
The output of the seventh stage of T is connected to one input of an AND circuit AND3, and the output of the AND circuit AND2 is connected to the other input of the AND circuit AND3. Therefore, in the AND circuit AND3, the counter clocks the clock signal CLK.
Counting 124 produces an output. On the other hand, counter CO
The output of an AND circuit AND6 is connected to the reset terminal R of each flip-flop in each stage of UT, and the input of this AND circuit AND6 is connected to the output of the NAND circuit NAND2 and S
NAND circuit N to which o~S3 signals are given as input signals
It is connected to the output of AND3.

Of these two NAND circuits NAND2 and NAND3, the input of the NAND circuit NAND2 is given the above-mentioned T and ~T4 signals, so it always produces a constant output signal, whereas the other NAND circuit NAND3 outputs the state signal So. ~
Since S3 is applied, its output signal also changes. Therefore, the output of the AND circuit AND6 is the state signal So
- It will change according to S3. Note that the counter COUT is reset by the state of the So to S3 signals between the T and T4 signals.

Shutter speed information corresponds to the T and ~L signals,
Assuming that the T5 to T8 signals correspond to the aperture and symbol display information, in Fig. 1, the former is used to detect the flashing cycle, and to detect the latter, the AND6 input should be NAND instead of NAND2. , the output should be . As shown in the figure, the status signals So to S3 are as follows: 4 pulses appear and 4 pulses disappear (in the case of 1 in the figure), 8 pulses appear and 8 pulses disappear (
In the case shown in Fig. 2), and it does not appear at all.

Therefore, the output signal of the fund circuit AND6 also appears correspondingly. And this state signal So~pot is the above T,~
Since it has the same period as the T8 signal, one period is equivalent to 8 clock signals CLK, and the disappearance of 4 pulses is equivalent to 32 times, 8
The number of pulse extinctions corresponds to 64 pulses. Therefore, when the state signal So ~ disappears for 4 pulses, the AND circuit AND8 does not generate a reset signal until the counter COUT counts 32 pulses, and when it disappears for 8 pulses, no reset signal is generated until the mouse pulse is counted, and furthermore, it does not generate a reset signal until the counter COUT counts 32 pulses. If it does not appear, no reset signal will be generated even if the maximum count value of the counter COUT, 12±, is counted. Therefore, when the count value of the counter COUT reaches 32, it corresponds to the disappearance of 4 pulses of the state signal So~S3, similarly, when it reaches I, it corresponds to the disappearance of 8 pulses, and when it reaches 128, no generation of So~S3 occurs. It corresponds to not having any.

In this embodiment, in consideration of errors in the reset signal CLK, the count values of the counters COUT and COUT are a little more than 4 r28.
”, “60”, and “124”, it is detected what state the state signals So to S3 represent.

That is, when the counter COUT reaches the count value "28", the AND circuit AND generates an output signal to set the flip-flop FF. When the count value reaches "60", the AND circuit AND2 generates an output signal to set the flip-flop FF2. Furthermore, when the count value "124" is reached, the AND circuit AND3 generates an output signal to set the flip-flop FF3. In other words, the counter COUT
, and AND circuits AND, .about.AND3, the flip-flops FF, .about.FF3 are set. On the other hand, regarding the reset of flip-flops FF, to FF3, FF3 is connected to the counter COUT. Similarly, AND circuit A
Reset by the output signal of ND6, the remaining FF,,F
F2 is reset by the output signals of AND circuits AND4 and AND5 combined with counters COUT2 and COUT3.

These counters COUT2 and COUT3 count one of the T signals, in this case the T8 signal, as an input signal, and are set when the output signal of the AND circuit AND or AND2 is applied. The counter COUT2 is composed of four stages of flip-flops, and the output of each stage and the first
The stage inputs are connected to the 5 inputs of the AND circuit AND4. Therefore, when the carinter COUT2 counts the T8 signal by one stitch, the AND circuit AND4 produces an output signal. On the other hand, the counter COUT2 is reset by the output signal of the AND circuit AND, which receives the clock signal CLK which appears at one-eighth period of the T8 signal.
Since the output signal is generated when the counter COUT, counts 2 hands, under normal conditions, the counter COUT2
All flip-flop stages of counter COUT2 are reset before the third stage flip-flop of COUT2 produces a Q output. In addition, the counter COUT2 is composed of five stages of flip-flops, and the output of each stage is connected to the five stages of the AND circuit AND5.
connected to the input.

Therefore, when the counter COUL counts 31 T8 signals, the AND circuit AND5 produces an output signal. On the other hand, the counter COUT3 is reset by the output signal of the AND circuit AND2, and like the AND circuit AND, this AND circuit AND2 also counts the clock signal CLK and produces an output signal when the count value reaches "60". Therefore, under normal conditions, all stages of the counter COUT3 are reset before the fourth stage flip-flop of the counter COU outputs the Q output. These counters COUT, ~COU
The outputs of the flip-flops FF, ~FF3, which respond to the outputs of the band circuits AND, ~AND5, which cooperate with T3, are connected to the AND circuits AND7, AND for determining the signal priority order.
8 and is output as a logic signal without going through it.

Next, the specific operation will be explained. It is now assumed that the status signals So to S3 have disappeared.

In this case, AND circuit AND6 does not apply a reset signal to counter COUT and flip-flop FF3. Therefore, all stages of the flip-flops of counter COUT produce outputs, and all AND circuits AND, -AND3 produce output signals. As a result, the flip-flop FF
3 is set, producing an output signal "0u0" representing "lights out". At this time, since the counters COUT2 and COUT3 are reset by the outputs of the AND circuits AND, AND2, the AND circuits AND4, AND5 do not generate output signals, and the flip-flops FF, FF2 are not reset. It is also assumed that eight pulses of the state signals So to S3 appear and disappear for eight pulses.

This is a 4Hz blinking display in the dot display and corresponds to the power supply voltage reaching the limit value. In this case, the flip-flops up to the sixth stage of the counter COUT produce Q outputs. During the time period corresponding to eight pulses of the status signals So to S3, the clock signal CLK counts a rat number of pulses if the status of the So to S3 signals does not change. Here, So~S
Since there is a possibility that the timing of the output signal is shifted by 4 pulses, the number of pulses for setting the FF is set to 60. As a result, the AND circuits AND, , AND2 generate an output signal and set the flip-flops FF, , FF2. Flip-flop FF3 is reset by being given the output of AND circuit AND6. As a result, flip-flops FF, FF2 produce a Q output, and FF3 produces a Q output. As a result, the AND circuit AND8 generates the "Out2 output". Since the AND circuit AND7 is not given the Q output of the flip-flop FF2, it does not generate the "O center tl" output. Furthermore, it is assumed that four pulses of the state signals So to S3 appear and disappear for four pulses. This is an 8Hz blinking display in dot display. When proper exposure cannot be obtained, it is assumed that the counter COUT produces a Q output for the same reason as mentioned above, up to the fifth stage flip-flop. In this case, the AND circuit AND provides an output signal to the flip-flop FF to set it, but the AND circuit AND
2, AND3 produces no output signal and the flip-flop F
F2 and FF3 are not set. Therefore, the AND circuit AND7 generates the "Outl" output when the input condition is met, and the other outputs "Out2" and "Out3" are not generated. In reality, "0 town t2" appears as the power supply voltage decreases after the output "OutIJ" is output.

On the other hand, when the power supply voltage is restored, the previous output, for example, "Out2" is changed to "Outl".

Or FF will also be reset and will no longer blink. This is the counter COUT2, COUT3 and the AND circuit AND
4. Based on the AND5 operation. For example, assume that the power supply voltage drops to a limit value and then recovers, and that four pulses of the status signals So to S3 appear and disappear. In this case, the AND circuit AND2 produces an output signal and resets the counter COUT2, but the AND circuit AND2 produces no output signal and the counter COUT3 is not reset. As a result, the AND circuit AND5 associated with the counter COUT3 resets the flip-flop FF2, eliminates the Q output of the flip-flop FF2 that had been generated up to that point, and generates a Q output. For this reason, the input conditions of the AND circuit AND7 are satisfied, and the "Outl" output is generated, replacing the "0M2 Issei force" that had been generated up to that point.Similarly, when the "OMI" output was generated, the settings of the aperture or shutter speed, etc. When the value is changed to obtain proper exposure, the flip-flop FF is reset by the operations of the counter COUT2 and the AND circuit AND4, and the input condition of the AND circuit AND7 is not satisfied, so that the "Outl" output disappears.

As described above, the present invention measures the disappearance time by being given a status signal which is a signal for displaying camera shooting information using a dot display method and which indicates a change in status by the extinction time of the signal. Since the output is generated according to the state, it is possible to display the state change in a segment format using a method different from the method used to display state changes in the dot display method.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a waveform diagram showing an input signal in the circuit shown in the figure and a clock signal formed using this input signal. COUT...Counter, NAND...
NAND circuit, OR...OR circuit, AND...
...AND circuit, FF...flip-flop. Figure 1 Figure 2

Claims (1)

[Claims] 1. A circuit that generates a clock signal by obtaining a first group of pulse signals to be applied to one pole of a light emitting diode for dot display, each having a constant repetition period and whose generation timing is regularly and sequentially shifted. , a group of signals to be applied to the other pole of the diode, in which both the pulse generation period and the pulse extinction period occur when a predetermined state change occurs, including improper exposure, a drop in power supply voltage, and outside the photographing limit. a circuit for forming a reset signal by obtaining a second pulse group that changes and has the same repetition period as the first pulse signal group; a first counter that generates an output when counting up to an intermediate value and when counting down to a lower position smaller than the intermediate value, and performs a reset operation in response to the reset signal; and the first pulse signal. a circuit for extracting one pulse signal in the group as a sub-reset signal; and a second counter that counts the sub-clock signal up to a first predetermined value and is reset by the median value count output from the first counter. , a third counter that counts the secondary clock signal up to a second predetermined value and is reset by the low value count output from the first counter; and a third counter that is reset by the maximum value count output from the first counter. a first flip-flop that is reset by the reset signal; a second flip-flop that is set by the median count output of the first counter and reset by the count output of the second counter; The third counter is set by the low value count output of the first counter.
a flip-flop that is reset by the count output of the counter, a circuit that takes out the Q output of the first flip-flop as it is, and an AND output of the Q output of the second flip-flop and the (2) output of the first flip-flop. a first AND circuit, and an output circuit having a second AND circuit for taking out an AND output between the Q output of the third flip-flop and both outputs of the first and second flip-flops; A photographing information display circuit for a camera that obtains at least three outputs according to a change in state of predetermined contents and displays these according to each output.