JPS58151576A - Timer device - Google Patents

Timer device

Info

Publication number
JPS58151576A
JPS58151576A JP3472382A JP3472382A JPS58151576A JP S58151576 A JPS58151576 A JP S58151576A JP 3472382 A JP3472382 A JP 3472382A JP 3472382 A JP3472382 A JP 3472382A JP S58151576 A JPS58151576 A JP S58151576A
Authority
JP
Japan
Prior art keywords
state
output signal
circuit
output
dichromatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3472382A
Other languages
Japanese (ja)
Inventor
Tomohide Oka
知英 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Toshiba TEC Corp
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tokyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tokyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP3472382A priority Critical patent/JPS58151576A/en
Publication of JPS58151576A publication Critical patent/JPS58151576A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G04HOROLOGY
    • G04FTIME-INTERVAL MEASURING
    • G04F3/00Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals with driving mechanisms, e.g. dosimeters with clockwork

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Predetermined Time Intervals (AREA)

Abstract

PURPOSE:To obtain a timer device which is capable of exactly showing whether an output state is on or off, namely, the time passing in its state, by providing a dichromatic display element whose color development is switched by existence of an output signal. CONSTITUTION:On a panel face 20 of the front of a body case 19, both an on- time setting control 21 and an off-time setting control 22 are provided, and on its upper part, a dichromatic light emitting LED24 which becomes a dichromatic display element consisting of 10 elements 23 is provided in one lateral row. This dichromatic light emitting LED24 consists of series of LED10-LED19 and LED20-LED29 for selectively displaying red or green, and each element 23 is combined, for instance, such as LED10 and LED20, and LED11 and LED21. By seeing color development of the dichromatic light emitting LED24, an operating state of an output contact is discriminated, and by seeing a position of the element 23 which is emitting light, the time passing in its state is discriminated. A state of an output signal becomes clear by a color, and also the time passing is grasped exactly since the element is made to emit light in order by counting a clock signal which becomes a reference of the output signal.

Description

【発明の詳細な説明】 本発明は、いわゆる電子デュアルタイi−と称される形
式のタイマー装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer device of the so-called electronic dual tie i- type.

従来のこの種のタイマー回路の概略を第1図に基いて説
明する。まず、操作電源入力端子(1)にトランス(2
)、整流回路(3)、定電圧回路(4)が接続され、こ
の定電圧回路(4)Kは二つのタイマー回路(5) (
6)が接続されている。これらのタイマー回路(5) 
(6)は発振回路、分周回路、針数回路、リセット回路
よりなるものであり、A−HIZ)8個の端子を有する
An outline of a conventional timer circuit of this type will be explained based on FIG. First, connect the operation power input terminal (1) to the transformer (2
), a rectifier circuit (3), and a constant voltage circuit (4) are connected, and this constant voltage circuit (4) K is connected to two timer circuits (5) (
6) is connected. These timer circuits (5)
(6) consists of an oscillation circuit, a frequency dividing circuit, a stitch count circuit, and a reset circuit, and has eight terminals (A-HIZ).

まず、A−Cなる端子は発振回路に接続され走時定数回
路(7)でパネル板(8)の操作つまみ(9) (1G
 Kそれぞれ連動している。D、ICなる端子は分周回
路に接続されているとともに分周率切換スイッチなlが
接続されてお9、これらの分周率切換スイッチα珍はパ
ネル板(8)のスイッチノブ01(L$に連動されてい
る。
First, the terminals A-C are connected to the oscillation circuit, and the operating knob (9) (1G
K are linked to each other. The terminals D and IC are connected to the frequency dividing circuit, and the frequency division rate changeover switch 9 is also connected.These frequency division rate changeover switches α are connected to switch knob 01 (L) on the panel board (8). It is linked to $.

ついで、前記整流回路(3)には、リレーコイル(ロ)
とトランジスタ(至)とが接続され、このリレーコイル
Q4とトランジスタ(至)とにはそれぞれ尭光ダイオー
ドαQα力が並列接続されている。そして、前記リレー
コイルα◆は外部制御用出力回路■に連動するように設
けられている。
Next, the rectifier circuit (3) includes a relay coil (b).
and a transistor (to) are connected, and a photodiode αQα is connected in parallel to the relay coil Q4 and the transistor (to), respectively. The relay coil α◆ is provided so as to be interlocked with the external control output circuit ■.

しかして、前記タイ1−回路(6)のF端子は前記トラ
ンジスタのベースに接続され、G端子は前記タイマー回
路(6)のリセット回路に連なるH端子に接続され、こ
のタイマー回路(6)OF端子は前記タイマー回路(5
)のリセット回路に連なるH端子KII続されている。
Thus, the F terminal of the tie 1 circuit (6) is connected to the base of the transistor, the G terminal is connected to the H terminal connected to the reset circuit of the timer circuit (6), and this timer circuit (6) OF The terminal is connected to the timer circuit (5
) is connected to the H terminal KII which is connected to the reset circuit.

このような構成において、操作電源が与えられると、た
とえば、タイマー回路(5)のF端子がLで、G端子が
Hとなる。そのため、タイマー回路(6)はリセット状
態KToる。また、トランジスタ(2)はOFFである
ため発光ダイオード(ロ)が発光し、OFF状態を表示
している。ついで、タイマー回路(5) Kより所定時
間が設定されてタイムアツプすると、壕ずG端子による
タイ!−回路(6)のリセットが解除され、F端子の出
力から逆にタイ!−回路(5)がリセットされ、そのタ
イ!−回路(5)の出力がHKなってトランジスタ(2
)をONさせ、リレーコイルα◆に通電して外部制御用
出力回路(至)を切換える。まえ、このと曹、発光ダイ
オード(至)が発光し、側状態を表示する。
In such a configuration, when the operating power is applied, the F terminal of the timer circuit (5) becomes L and the G terminal becomes H, for example. Therefore, the timer circuit (6) is in the reset state KTo. Further, since the transistor (2) is OFF, the light emitting diode (B) emits light to indicate the OFF state. Next, when the predetermined time is set by the timer circuit (5) K and the time is up, a tie is made by the trenchless G terminal! - The reset of circuit (6) is released and the tie is reversed from the F terminal output! -Circuit (5) is reset and the tie! -The output of the circuit (5) becomes HK and the transistor (2
), energizes the relay coil α◆ and switches the external control output circuit (to). In front of this, the light emitting diode will emit light to display the side status.

このように従来の回路による場合には、出力が開かOF
Fかのいずれかの状態であることは解るが、その状態が
どの位続いているかと云うことは全く不明である。
In this way, in the case of conventional circuits, the output is open or OF
Although it is known that the patient is in one of the states F, it is completely unclear how long that state lasts.

本発明は、このような点く鑑みなされたもので、出力状
態が側かOFFかの表示が行なわれるとともにその状態
での時間経過が明確に示されるタイマー回路置を得るこ
とを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide a timer circuit device that displays whether the output state is on or off, and clearly shows the elapsed time in that state.

本発明は、出力信号の基準になるクロック信号をカウン
トして複数個の素子よりなる二色表示素子の切換えを順
次行なわせ、これにより、一定状態での時間の経過を表
示し、ま九、出力信号が諏またはOFF したと龜に二
色表示素子の発色をいずれかの発色状態に切換えるよう
にし九ので、出力が係かOFFかの状態も一見して解る
ように構成し九ものである。
The present invention sequentially switches a two-color display element made up of a plurality of elements by counting a clock signal that serves as a reference for an output signal, thereby displaying the passage of time in a constant state, and When the output signal is turned on or off, the coloring of the two-color display element is switched to one of the coloring states immediately, so the configuration is such that it can be seen at a glance whether the output is engaged or off. .

本発明の一実施例を第2図ないし籐4図に基いて説明す
る。まず、本体ケース(2)の正面のパネル面一には、
08時間設定つまみQ論とOFF時間設定つまみ(2)
とが設けられているとと−に上部には10個の素子に)
Kよる二色表示素子となる二色発光LJiJ)(財)が
横一列に配設されている。この二色発光−(ハ)は、赤
または緑を選択的に表示するLKDs・〜臘・と■Ds
e−LE−との系列よりなり、各素子に)は九とえばL
iDt・とLM)m 、 L山tと」hと云うように組
合わ畜れている。
An embodiment of the present invention will be explained based on FIGS. 2 to 4. First, on the front panel of the main body case (2),
08 Time setting knob Q theory and OFF time setting knob (2)
(10 elements are provided at the top)
Two-color light emitting devices (LJiJ) (Incorporated), which are two-color display elements based on K, are arranged in a horizontal row. This two-color emission (c) is LKDs that selectively displays red or green.
consists of the series e-LE-, and for each element) is 9, for example L
They are bred together like iDt and LM)m, Lyamat and 'h.

しかして、第3図および第4図に基いてその^体的回路
をその作用とと−に説明する。まず、タイマー用IC(
2)は一般市場で入手可能なものであり、1−1−の端
子を有する。そして、入力電源端チーに電圧を印加する
と、抵抗&@で電流制限され、端子1,111Kiil
lsれた定電圧回路−で定電圧が作9出され、端子18
からVDDとして各部に供給される。
The physical circuit and its operation will now be explained based on FIGS. 3 and 4. First, the timer IC (
2) is available on the general market and has 1-1- terminals. Then, when a voltage is applied to the input power supply terminal Qi, the current is limited by the resistor &@, and the terminal 1,111Kiil
A constant voltage is generated by the constant voltage circuit 9, which is connected to terminal 18.
It is supplied to each part as VDD from the VDD.

ついで、タイマー用ICti4の内部には、発振回路−
e 3foo の固定分周回路員、H〜%。。の可変分
周回路0番、端子111,13,14 K Q e Q
 、 ”746  ノ第e第二、第三の出力を発生させ
る出方回路となる出力バッファ(イ)、デコーダ(至)
、オートリセット回路(ロ)が設けられている。そして
、前記発振回路−は端子S、7..1間で電源を与えら
れているとともに端子2を経て黴lll11可変抵抗V
R4(至)K!1続されている。tた、端子4には、V
Rsと8層とよ)なる抵颯(至)とVR,とVRsとよ
りなる抵抗(ロ)との二種が接続堪れ、これらは端子1
!、11 K接続されて切換動作制御がなされる切換回
路となる電子スイ′ツテ@に接続されている。
Next, inside the timer ICti4, an oscillation circuit is installed.
Fixed frequency divider member of e 3foo, H~%. . Variable frequency divider circuit No. 0, terminals 111, 13, 14 K Q e Q
, ``746 No.e Output buffer (A) and decoder (to), which are the output circuits that generate the second and third outputs.
, an auto-reset circuit (b) is provided. The oscillation circuit has terminals S, 7. .. Power is supplied between terminals 1 and 11 and variable resistor V passes through terminal 2.
R4 (To) K! It is continuous. t, terminal 4 has V
Two types of resistors (Rs and 8 layers), VR, and VRs (R) are connected, and these are connected to terminal 1.
! , 11 K are connected to an electronic switch which serves as a switching circuit for controlling switching operations.

ツキに、端子9,10.11 Kはデジタル&W(至)
が接続され、前記デコーダOIKmi続されている。こ
のデジタルEW(2)は分周比を決めるものであ〕、端
子−110,11の部分の符号tS・e at a &
とすれば、これらのレベルのH,Lで定められる分周比
は下表のとうりである。
Fortunately, terminals 9, 10.11 K are digital & W (to)
is connected to the decoder OIKmi. This digital EW (2) determines the frequency division ratio], and the sign tS・e at a &
Then, the frequency division ratio determined by these levels H and L is as shown in the table below.

また、端子12には抵抗&−を介してリレーコイル@傘
と直列のトランジスターが接続され、前記リレーコイル
@論は出力接点−に連動している。鵞九、端子12はコ
レクタが電源に接続され、工電ツIが前記二色発光Ia
HK接続され走対となっ九トランジスタ(44ム)(4
4B)の一方に抵抗R4−を介して接続されている。1
九、他方のトランジスI (44B)には抵抗−を介し
て端子13が接続されている。
Further, a transistor in series with a relay coil is connected to the terminal 12 via a resistor &-, and the relay coil is interlocked with an output contact. The collector of the terminal 12 is connected to the power supply, and the electric power supply I is connected to the two-color light emitting Ia.
9 transistors (44 μm) (4
4B) via a resistor R4-. 1
9. The terminal 13 is connected to the other transistor I (44B) via a resistor.

ついで、端子14には10進カウンタ(ロ)が接続され
ている。この10進カウンターのリセット端子には抵抗
−とコンデンサCmとよりなる初期リセット回路−が接
続され、電源投入時にはリセットされる。
Next, a decimal counter (b) is connected to the terminal 14. An initial reset circuit consisting of a resistor and a capacitor Cm is connected to the reset terminal of this decimal counter, and is reset when the power is turned on.

この10進カウンタ0A−Dなる出力は、デコーダーに
よEgo〜9010種の出力に変換され、この出力はT
z・〜〜と表記し九増幅トランジスタt4Kw!絖され
、これらの増幅トランジスタに)は前記二色発光Lli
lD−に接続されている。
The outputs of the decimal counters 0A-D are converted into outputs of Ego~9010 types by the decoder, and this output is T
Nine amplification transistors t4Kw, written as z・~~! and these amplification transistors) are connected to the two-color light emitting Lli.
Connected to ID-.

しかして、電源投入時にオートリセット回路(ロ)によ
り発振回路−、固定分周回路(至)、可変分周回路e1
がそれぞれリセットされ、同時[1G進カウンターも初
期リセット回路−によりリセットされる。
Therefore, when the power is turned on, the auto-reset circuit (b) activates the oscillation circuit -, the fixed frequency divider circuit (to), and the variable frequency divider circuit e1.
are reset, and at the same time, the 1G counter is also reset by the initial reset circuit.

この状11Iにおいては、端子12の出力Qはしてトラ
ンジスタH(4i人)をOFFさせておシ、端子13の
出力ζFiHでトランジスタ(44B)をONさせ、L
EDI・〜■1・に駆動電力を与えている。
In this state 11I, the output Q of the terminal 12 turns off the transistor H (4i people), and the output ζFiH of the terminal 13 turns on the transistor (44B), causing the L
Driving power is given to EDI・~■1・.

そして、発振回路−は抵抗(至)が選択されてそれによ
る発振周期で発振し、デジタル腑(2)で設定され九分
周比をもって出力バッファ(至)から出力が発生ずる。
Then, the oscillation circuit oscillates with the oscillation period determined by the selected resistor, and an output is generated from the output buffer with the frequency division ratio set by the digital controller (2).

九とえは発振回路出力100 X n (えだし、hは
可変分周数)で楢o 嬬1サイクルのH,Lを繰)返す
。まず、最初の%0がHで10進カウンターが出力を発
生し、デコーダの0端子に出力を出してLKDnを発光
させる。つぎの%0のHで、11が発光し、これがLE
Dt参までの10回繰り返堪れる。
For nine cycles, the oscillation circuit output is 100 x n (h is a variable frequency division number), and one cycle of H and L is repeated. First, the first %0 is H and the decimal counter generates an output, which is output to the 0 terminal of the decoder to cause LKDn to emit light. At the next H of %0, 11 emits light and this is LE
I can enjoy repeating it 10 times until Dt.

この状態においては、出力接点−がb−・な為接続状態
を示している。
In this state, the output contact - is b-, indicating a connected state.

このようにして%Q 010回の繰p返しが終了すると
、端子12のQはHになり、端子18の互はLKなる。
When the %Q010 repetitions are completed in this way, the Q at the terminal 12 becomes H, and the terminal 18 becomes LK.

これにより、トランジスターが謝してリレーコイル働に
通電し、出力接点を轟−・に切換え。
This causes the transistor to energize the relay coil and switch the output contact to low.

トランジスタ(44A)をONさせてLEDm〜LID
mを駆動状態にし、LEIlh・〜LEDI−は非点灯
状態となって色が変り、電子スイッチ(至)が切)換見
られてV&とVRIとによる抵抗(ロ)の条件のもとに
発振回路−が発振する。この場合の発振周期は前よりも
大自いものとすれば、第4図に示すように出力の変化間
隔が広がる。すなわち、’[@oH,Lの周期は前より
一大自くなJ)、LiDm〜LEDmが順次発光する。
Turn on the transistor (44A) and turn on LEDm~LID
m is driven, LEIlh~LEDI- becomes non-lit and changes color, the electronic switch (to) is switched, and it oscillates under the condition of the resistance (b) by V& and VRI. The circuit - oscillates. If the oscillation period in this case is made longer than before, the interval between changes in the output becomes wider as shown in FIG. That is, '[@oH, the period of L is much larger than before], and LiDm to LEDm sequentially emit light.

これが−巡すると、−回の時間制御の周期がin、入力
電源がある限り同じ動作を繰り返す。
When this cycle continues, the cycle of time control is in, and the same operation is repeated as long as there is input power.

このような動作は、−個のタイマー用1c(2)を用い
るにけで集村され、しか4動作中においては、二色発光
Llij)(財)の発色を見れは出力接点−の動作状態
が判別され、また、発光している素子(2)の位置をみ
れば、その状態での時間経過が判別される。
Such an operation can be performed by using the timer 1c (2), and during operation, the color development of the two-color light emitting device (Llij) (Incorporated) is determined by the operating state of the output contact. is determined, and by looking at the position of the emitting element (2), the passage of time in that state can be determined.

本発明は、上述のように出力信号が切換ることKよp発
光色が興なる二色表示素子を設けたので、出力信号の状
態は色によって明確になり、また、出力信号の基準にな
るクロック信号をカウントして素子を拳次発光させるの
で、その状態における時間経過もきわめて喪く知ること
ができる等の効果を有するものである。
As described above, the present invention is provided with a two-color display element in which the output signal is switched and the color of light emitted is different from K to P. Therefore, the state of the output signal is made clear by the color, and also serves as a reference for the output signal. Since the elements are made to emit light one after another by counting clock signals, it is possible to clearly see the passage of time in that state.

【図面の簡単な説明】[Brief explanation of the drawing]

県1図は従来の一例を示す回路図、第2図は本発明の一
実施例を示す斜視図、菖3図はその回路図、第4図はタ
イミングチャートである。
Figure 1 is a circuit diagram showing a conventional example, Figure 2 is a perspective view showing an embodiment of the present invention, Figure 3 is a circuit diagram thereof, and Figure 4 is a timing chart.

Claims (1)

【特許請求の範囲】[Claims] 信号入力時から所定の設定時間後に出力信号を生じ、別
に定められた設定時間後に出力信号を停止し、前記信号
入力のある場合には前記出力信号の発生と停止とを繰9
返すようにしたタイマーにおいて、前記出力信号の基準
になる周期の小さいタロツク信号により所定時間毎に素
子の切換えが行なわれ前記出力信号の有無により発色が
切換えられる複数素子による二色表示素子を設けたこと
を特徴とするタイマー装置。
An output signal is generated after a predetermined set time from the time of signal input, and the output signal is stopped after a separately determined set time, and when the signal is input, the output signal is generated and stopped repeatedly.
The timer is provided with a two-color display element consisting of a plurality of elements whose elements are switched at predetermined time intervals by a tarokk signal with a short period that serves as a reference for the output signal, and whose color development is switched depending on the presence or absence of the output signal. A timer device characterized by:
JP3472382A 1982-03-05 1982-03-05 Timer device Pending JPS58151576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3472382A JPS58151576A (en) 1982-03-05 1982-03-05 Timer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3472382A JPS58151576A (en) 1982-03-05 1982-03-05 Timer device

Publications (1)

Publication Number Publication Date
JPS58151576A true JPS58151576A (en) 1983-09-08

Family

ID=12422241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3472382A Pending JPS58151576A (en) 1982-03-05 1982-03-05 Timer device

Country Status (1)

Country Link
JP (1) JPS58151576A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61179995U (en) * 1985-04-30 1986-11-10
JPH034193A (en) * 1989-05-31 1991-01-10 Sumitomo Rubber Ind Ltd Method and device for effective time display

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61179995U (en) * 1985-04-30 1986-11-10
JPH034193A (en) * 1989-05-31 1991-01-10 Sumitomo Rubber Ind Ltd Method and device for effective time display

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