JPS60211825A - Thin film semiconductor element - Google Patents
Thin film semiconductor elementInfo
- Publication number
- JPS60211825A JPS60211825A JP6875784A JP6875784A JPS60211825A JP S60211825 A JPS60211825 A JP S60211825A JP 6875784 A JP6875784 A JP 6875784A JP 6875784 A JP6875784 A JP 6875784A JP S60211825 A JPS60211825 A JP S60211825A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film semiconductor
- semiconductor layer
- metal
- metal substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02425—Conductive materials, e.g. metallic silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 この発明は薄膜半導体素子に関するものである。[Detailed description of the invention] Industrial applications This invention relates to thin film semiconductor devices.
従来例の構成とその問題点 従来、薄膜半導体素子の基板としては、ガラス。Conventional configuration and its problems Conventionally, glass has been used as the substrate for thin film semiconductor devices.
石英、サファイア等の絶縁性基板、もしくは研摩したス
テンレス鋼板（以下ＳＵＳという）等の導電性基板が使
われている（この導電性基板を以下金属基板という）。An insulating substrate such as quartz or sapphire, or a conductive substrate such as a polished stainless steel plate (hereinafter referred to as SUS) is used (this conductive substrate will hereinafter be referred to as a metal substrate).
金属基板上に薄膜半導体層、例エバアモルファスシリコ
ン（以下ａ−８ｉ という）層を形成した場合、素子の
信頼性には、薄膜半導体層と、金属基板との密着性が大
きな要素となってくる。金属基板は研摩して使われてい
るが、研摩しである金属基板は、それ自体基板の表面積
が小さく、薄膜半導体層との密着面積が少ない。When a thin film semiconductor layer, such as an Eva amorphous silicon (hereinafter referred to as a-8i) layer, is formed on a metal substrate, the adhesion between the thin film semiconductor layer and the metal substrate is a major factor in the reliability of the device. . Metal substrates are used after being polished, but the polished metal substrate itself has a small surface area and has a small adhesion area with the thin film semiconductor layer.
一方、研摩していない金属基板においては、金属基板の
表面積が大きくなり、薄膜半導体層との密着面積が大き
い。このように表面の凸凹の大小により、金属基板と薄
膜半導体との密着力や特性の点で差があった。また金属
基板上に形成した半導体層は、金属基板と共にプレス加
工やレーザー等による後工程により、内部応力や熱ひず
み等を発生する。そのため、薄膜半導体層と、金属基板
との界面において、密着力が弱いと剥離が生じる。On the other hand, in an unpolished metal substrate, the surface area of the metal substrate is large, and the area of close contact with the thin film semiconductor layer is large. As described above, there are differences in adhesion and properties between the metal substrate and the thin film semiconductor depending on the size of the surface irregularities. Further, the semiconductor layer formed on the metal substrate generates internal stress, thermal strain, etc. due to post-processing using press processing, laser, etc. together with the metal substrate. Therefore, if the adhesion is weak at the interface between the thin film semiconductor layer and the metal substrate, peeling will occur.
現状の研摩した金属基板と、薄膜半導体層との密着強度
は、前記の点において、十分とはいいがたかった。The adhesion strength between the current polished metal substrate and the thin film semiconductor layer cannot be said to be sufficient in the above-mentioned respect.
発明の目的
本発明は、゛金属基板とａ −３ｔ 等の薄膜半導体層
との密着性を向上して、信頼性及び素子性能の向上を計
った薄膜半導体素子を提供することを目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a thin film semiconductor device with improved reliability and device performance by improving the adhesion between a metal substrate and a thin film semiconductor layer such as a-3t.
発明の構成
本発明は上記目的を達成するために、金属基板上にＣｒ
又はＣｒ を含む合金層を形成したことを特徴とする
ものである。Structure of the Invention In order to achieve the above object, the present invention provides Cr on a metal substrate.
Alternatively, it is characterized by forming an alloy layer containing Cr.
金属基板と、薄膜半導体層との密着性にかかわる主たる
要素は次の通りである。The main factors involved in the adhesion between the metal substrate and the thin film semiconductor layer are as follows.
（１）金属基板の清浄度
（噂 金属基板の表面状態
（鴎 金属基板と、薄膜半導体層とのなじみ（１）の金
属基板の清浄度に関していれば、半導体技術の発展に伴
って、十分な清浄度を持つ金属基板は得られてはいるが
、所要工程が多くなり、装置的には高価なものが多い。(1) Cleanliness of metal substrates (Rumors) Surface condition of metal substrates (Rumours) Compatibility of metal substrates with thin film semiconductor layers (1) Regarding cleanliness of metal substrates, with the development of semiconductor technology, sufficient Although a clean metal substrate can be obtained, many steps are required and the equipment is often expensive.
（巧の金属基板の表面状態に関していえば、金属表面の
凸凹が、薄膜半導体層を均一に金属基板上に形成させな
いだめ、素子の特性上問題になることが多く、現状では
研摩した金属基板を使用し、凸凹をなくして使用してい
る。しかし研摩した金属基板は、基板表面積が減少し、
薄膜半導体層との密着面積が減るため、密着強度的には
不利である。(As for the surface condition of Takumi's metal substrate, the unevenness of the metal surface often causes problems with the characteristics of the device unless the thin film semiconductor layer is uniformly formed on the metal substrate. Currently, polished metal substrates are However, polished metal substrates reduce the surface area of the substrate.
Since the adhesion area with the thin film semiconductor layer is reduced, this is disadvantageous in terms of adhesion strength.
（鴫の金属基板と、薄膜半導体層とのなじみに関してい
えば、金属の種類によって、また薄膜半導体の種類によ
って変化することが確認された。商業的に使われる金属
基板は限られており、また薄膜半導体素子自体の特性的
な要請により、使える金属基板は限られるため、その種
類は多くない。(As for the compatibility between the metal substrate and the thin film semiconductor layer, it was confirmed that it changes depending on the type of metal and the type of thin film semiconductor.) There are only a limited number of metal substrates that are used commercially, and There are not many types of metal substrates because the types of metal substrates that can be used are limited due to the characteristics of the thin film semiconductor element itself.
現在使われている金属基板は、研摩したＳＵＳ基板、も
しくは、Ａｌ にＮｉメッキとＣｒメッキを施した基板
であるが、必ずしも密着強度が十分であるとはいいがた
い。ここにおいて、金属基板上に各種金属層を蒸着して
、基板表面の改質化を計り、金属基板と蒸着金属層との
界面、蒸着金属層と薄膜半導体層との界面で双方との密
着強度の大きい蒸着金属を選定すれば、信頼性の高い薄
膜半導体素子を形成することが可能となる。The metal substrates currently in use are polished SUS substrates or Al substrates with Ni plating and Cr plating, but it cannot be said that the adhesion strength is necessarily sufficient. Here, various metal layers are deposited on a metal substrate to modify the substrate surface, and to improve the adhesion strength at the interface between the metal substrate and the deposited metal layer, and the interface between the deposited metal layer and the thin film semiconductor layer. By selecting a deposited metal with a large value, it becomes possible to form a highly reliable thin film semiconductor element.
金属基板上に各種金属を蒸着することにより、前記（１
）の金属基板の清浄度に関して言えば、蒸着面は清浄面
であるため、高価な半導体グレードの洗浄装置はいらな
くなり、金属基板の脱脂程度で前洗浄は済１せられるこ
とになる。なお、金属同士の蒸着に関して、その密着性
は一般的に大きいため、今回この方法では、信頼性確保
において問題ではなかった。By depositing various metals on a metal substrate, the above (1)
) Regarding the cleanliness of the metal substrate, since the evaporation surface is a clean surface, there is no need for expensive semiconductor grade cleaning equipment, and pre-cleaning can be completed by simply degreasing the metal substrate. In addition, since the adhesion between metals is generally high, there was no problem in ensuring reliability with this method.
前記（功の金属基板の表面状態に関していえば、蒸着金
属が、金属基板表面上をおおうため、表面の凸凹はあっ
ても、その表面は蒸着により微視的状態において滑らか
となるため、研摩が不要に々る。研摩が不要になれば、
基板コストも低下し、蒸着のだめに上がるコストは、補
ってあまりあるものとなる。さらに研摩不要であると、
基板表面の凸凹による表面積は、研摩面に比して大きく
なるため、密着性はさらに向上する。Regarding the surface condition of the metal substrate mentioned above, since the vapor-deposited metal covers the surface of the metal substrate, even if the surface is uneven, the surface becomes microscopically smooth due to vapor deposition, so polishing is difficult. Unnecessary.If polishing is no longer necessary,
Substrate costs are also reduced, more than outweighing the increased costs of vapor deposition. Furthermore, there is no need for polishing.
Since the surface area due to the unevenness of the substrate surface is larger than that of the polished surface, the adhesion is further improved.
前記（曇の金属基板と、薄膜半導体層とのなじみに関し
ていえば、蒸着金属の種類によって、蒸着金属とａ −
３ｉ 薄膜半導体層との密着強度には第８図、第９図に
示すように大きな差があることがわかった。その中でＣ
ｒ およびＣｒ ｆ、（含んだ合金が密着性に関して良
い特性を示した。Regarding the compatibility between the cloudy metal substrate and the thin film semiconductor layer mentioned above, depending on the type of the deposited metal, the difference between the deposited metal and the a-
It was found that there was a large difference in adhesion strength with the 3i thin film semiconductor layer, as shown in FIGS. 8 and 9. Among them, C
r and Cr f, (the containing alloy showed good properties with respect to adhesion.
このように、金属基板表面」二に、蒸着でＣｒ ｉたは
Ｃｒを含んだ合金属を形成することにより、表面清浄で
研摩不要な、密着性の大きい信頼性のある薄膜半導体素
子が得られる。In this way, by forming Cr or an alloy containing Cr on the surface of a metal substrate by vapor deposition, a reliable thin film semiconductor element with a clean surface, no need for polishing, and high adhesion can be obtained. .
なお、蒸着金属は、純度の高いものが使えるため、基板
による不純物の拡散、および汚染が防止でき、第１０図
に示す実線の５ＵＳ３０４に比べ破線のＣｒは素子特性
上良いものが得られる。Incidentally, since a highly pure vapor-deposited metal can be used, diffusion of impurities and contamination by the substrate can be prevented, and Cr shown by the broken line can provide better device characteristics than 5US304 shown by the solid line shown in FIG.
捷だ金属基板もその材質、グレードが自由に選べるため
、基板コストを低下できる。Since the material and grade of the solid metal substrate can be freely selected, the cost of the substrate can be reduced.
実施例の説明 以下本発明の詳細な説明する。Description of examples The present invention will be explained in detail below.
第１図において、１は金属基板であり、その材質は問わ
なく、広い範囲から選択できる。第２図は金属基板１を
脱脂後、各種蒸着金属層２（！−影形成たものである。In FIG. 1, 1 is a metal substrate, and its material can be selected from a wide range regardless of the material. FIG. 2 shows various vapor-deposited metal layers 2 (shades formed) after the metal substrate 1 has been degreased.
ここでの各種蒸着金属は、Ｃｒ−ｉたけＣｒを含んだ合
金が適している。An alloy containing as much Cr as Cr-i is suitable for the various vapor-deposited metals here.
第３図は第２図で形成した各種蒸着金属層２の」二に、
薄膜半導体層３を形成したものであり、ここでの半導体
層はａ −３ｉ である。FIG. 3 shows various vapor-deposited metal layers 2 formed in FIG.
A thin film semiconductor layer 3 is formed, and the semiconductor layer here is a -3i.
第４図は第３図で形成した薄膜半導体層の上に透明導電
膜４、例えば工ｎ２０３−ｓｎ０２，５ｎ０２などを形
成したものであり、これで薄膜半導体素子が形成される
。なお、素子の構成は一例であり、この場合だけには限
らない０
次に基板と薄膜半導体層との密着性の試験方法について
述べる０
第６図において、前述のようにして作った半導体素子６
を矢印６の方向に、薄膜半導体層表面を向けて半径Ｒで
曲げる。これは金属基板への応力を想定している。第６
図は第６図を上から見た図である。薄膜半導体素子６の
上の半径Ｒで曲げた曲りの中心部付近７においては、第
７図の拡大図のように微細なりランクが入る。これは金
属基板の変形に追従しきれなくなった半導体層及び透明
電極層が、割れておぺるものである。第７図において、
８は透明電極層と薄膜半導体層の割れたクラックであり
、密着性が不良で、薄膜半導体層が各種蒸着金属層から
脱落、剥離した部分９がある。FIG. 4 shows that a transparent conductive film 4, such as n203-sn02, 5n02, etc., is formed on the thin film semiconductor layer formed in FIG. 3, thereby forming a thin film semiconductor element. Note that the configuration of the device is an example, and is not limited to this case.Next, a method for testing the adhesion between the substrate and the thin film semiconductor layer will be described.
is bent with a radius R in the direction of arrow 6, with the surface of the thin film semiconductor layer facing. This assumes stress on the metal substrate. 6th
The figure is a top view of FIG. In the vicinity 7 of the center of the bend at the radius R on the thin film semiconductor element 6, there is a fine rank as shown in the enlarged view of FIG. This is because the semiconductor layer and transparent electrode layer are unable to follow the deformation of the metal substrate and break. In Figure 7,
Numeral 8 indicates a crack between the transparent electrode layer and the thin film semiconductor layer, and there is a portion 9 where the thin film semiconductor layer has fallen off or peeled off from the various vapor-deposited metal layers due to poor adhesion.
密着強度を見る時には、この部分が単位面積当りとのぐ
らいあれば良いか見れば良い。When looking at adhesion strength, it is sufficient to see if this portion should be about the same as per unit area.
さらにこの状態で、半導体素子の信頼性テストで使われ
る１２０’Ｃ不飽和型８ｈｒのプレッシャークツカー試
験を行なうと、第７図の剥離した部分が、一層広い面積
を占めることになる。第８図は、第１図から第７図まで
の工程で形成した金属基板１（この場合は５ＵＳ３０４
）の上に、Ｘ軸方向に書かれである金属を１６０°Ｃで
おなじ嘆厚になるように蒸着し、各種蒸着金属層２を形
成した。Ｙ軸は前記工程を行なって、前記条件のプレッ
シャークンカー試験を通して、単位面積当りの剥離部分
９の割合である。これをａ −８ｉ 脱離度と呼ぶ。脱
離度が低いほど密着強度は大きい。第８図でわかるよう
に、Ｃｒ またはＣｒ ｆｌ含んだ合金の蒸着金属層上
と薄膜半導体層との密着強度は他のものに比して著しく
太きい。Furthermore, when a 120'C unsaturated 8-hour pressure tester used in reliability testing of semiconductor devices is conducted in this state, the peeled portion shown in FIG. 7 occupies an even wider area. FIG. 8 shows the metal substrate 1 (5US304 in this case) formed in the steps from FIG. 1 to FIG.
), the metals shown in the X-axis direction were vapor-deposited at 160°C to the same thickness to form various vapor-deposited metal layers 2. The Y-axis is the ratio of the peeled portion 9 per unit area after performing the above steps and passing the pressure Kunker test under the above conditions. This is called the a −8i degree of elimination. The lower the degree of desorption, the greater the adhesion strength. As can be seen from FIG. 8, the adhesion strength between the vapor-deposited metal layer of the alloy containing Cr or Cr fl and the thin film semiconductor layer is significantly greater than that of other types.
第９図は、ニクロム合金をつけだ場合の密着強度を調べ
たものである。Ｃｒ とＮｉ の割合を各種変化させて
蒸着金属＠２を形成した。評価方法は第８図の場合と同
一である。Ｘ軸はＣｒ／Ｎ ｉの比を表わしている。捷
だＹ軸は前と同じａ−３ｉ脱離度である。Ｃｒ を入れ
ると密着強度は大きくなる。FIG. 9 shows an investigation of the adhesion strength when a nichrome alloy was applied. Vapor deposited metal@2 was formed by varying the ratio of Cr and Ni. The evaluation method is the same as in the case of FIG. The X-axis represents the Cr/N i ratio. The Y-axis is the same a-3i desorption degree as before. Adding Cr increases the adhesion strength.
Ｃｒ を各種蒸着金属層２に混入することが有効である
ことがわかる〇
第１０図は、一般的に太陽電池でいうところのＩ−Ｖ特
性である。各種合金層２を他の条件を同一にして５ＵＳ
３０４と純Ｏｒ でつけ、光電特性を比較した。工ｓｃ
で知られる短絡電流値ては変化がないところから、金属
の表面反射率にはきわたった差はない。次に■ｏｃで知
られる開放電圧にも差がないため、双方ともｐ−ｉ −
ｎ接合はとれている。It can be seen that it is effective to mix Cr into the various vapor deposited metal layers 2. Figure 10 shows the IV characteristics generally referred to in solar cells. 5US of various alloy layers 2 with other conditions being the same.
304 and pure Or, and the photoelectric properties were compared. engineering sc
Since there is no change in the short-circuit current value known as , there is no significant difference in the surface reflectance of metals. Next, since there is no difference in the open circuit voltage known as ■oc, both p-i −
The n-junction has been removed.
しかし、ＦＦで知られるところの曲線因子においては、
明らかに純Ｃｒ ｆつけた金属基板のものが、５ＵＳ３
０４よりも１０〜２０％程度良いものが得られる。これ
は、密着強度向上によって生じたものと考えられる。こ
のように特性面においても、Ｃｒの含有量の多いものが
、良い結果を示している。However, in the fill factor known as FF,
The metal substrate with pure Cr f is obviously 5US3.
A product that is about 10 to 20% better than 04 can be obtained. This is considered to be due to the improvement in adhesion strength. As described above, in terms of properties as well, those with a high Cr content show good results.
発明の効果
以上述べたように、金属基板上にＣｒ またはＣｒ合金
を蒸着して金属基板と薄膜半導体層との密着強度を大き
くすることは、密度向上による信頼性向上と洗浄が簡単
になり、研摩が不要になること、および安価な金属基板
が選べることにより、蒸着工程がふえるにもかかわらず
、相対的にコストダウンを図ることができる。Effects of the Invention As described above, increasing the adhesion strength between the metal substrate and the thin film semiconductor layer by vapor depositing Cr or Cr alloy on the metal substrate improves reliability due to increased density and facilitates cleaning. Since polishing is not required and an inexpensive metal substrate can be selected, costs can be relatively reduced even though the number of vapor deposition steps is increased.
第１図は本発明における金属基板の断面図、第２図は同
基板上に各種の蒸着金属層を形成した断面図、第３図は
蒸着金属層上に薄膜半導体層を形成した断面図、第４図
は薄膜半導体層上に透明導電膜を形成した断面図、第５
図は薄膜半導体素子を曲げた側面図、第６図はその上面
図、第７図はその部分拡大図、第８図は各種蒸着金属層
Ｊａ−８１の脱離度との関係を示す図、第９図はＣｒ合
金であるニクロムの組成とａ −３ｉ の脱離度との関
係を示す図、第１０図は薄膜半導体素子のＩ−■特性を
示す図である。
１・・・・・・金属基板、２・川・・蒸着金属、３・川
・薄膜半導体層、４・・・・・透明導電膜。
代理人の氏名 弁理士 中 尾 敏 男 はが１名第１
図
第２図
第３図
第４図
第５図
■
第６図FIG. 1 is a cross-sectional view of a metal substrate according to the present invention, FIG. 2 is a cross-sectional view of various vapor-deposited metal layers formed on the same substrate, and FIG. 3 is a cross-sectional view of a thin-film semiconductor layer formed on the vapor-deposited metal layer. Figure 4 is a cross-sectional view of a transparent conductive film formed on a thin film semiconductor layer;
The figure is a side view of a bent thin film semiconductor element, FIG. 6 is a top view thereof, FIG. 7 is a partially enlarged view thereof, and FIG. 8 is a diagram showing the relationship between the degree of desorption of various vapor-deposited metal layers Ja-81, FIG. 9 is a diagram showing the relationship between the composition of nichrome, which is a Cr alloy, and the degree of desorption of a -3i , and FIG. 10 is a diagram showing the I-■ characteristics of a thin film semiconductor element. DESCRIPTION OF SYMBOLS 1... Metal substrate, 2... Vapor deposited metal, 3... Thin film semiconductor layer, 4... Transparent conductive film. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 Figure 3 Figure 4 Figure 5■ Figure 6
Claims (1)
着層を形成したことを特徴とする薄膜半導体素子。1. A thin film semiconductor device comprising a vapor deposited layer of Cr or an alloy containing Cr on the surface of a metal substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6875784A JPS60211825A (en) | 1984-04-05 | 1984-04-05 | Thin film semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6875784A JPS60211825A (en) | 1984-04-05 | 1984-04-05 | Thin film semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60211825A true JPS60211825A (en) | 1985-10-24 |
Family
ID=13382941
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6875784A Pending JPS60211825A (en) | 1984-04-05 | 1984-04-05 | Thin film semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60211825A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01123366U (en) * | 1988-02-15 | 1989-08-22 |
-
1984
- 1984-04-05 JP JP6875784A patent/JPS60211825A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01123366U (en) * | 1988-02-15 | 1989-08-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900003830B1 (en) | Method for effecting adhesion of silicon or silicon dioxide plates | |
| JP2003077860A (en) | ELECTRODE FOR p-TYPE SiC | |
| EP2989656B1 (en) | Method for producing a schottky diode on a diamond substrate | |
| JPS59104184A (en) | Solar battery | |
| US6884718B2 (en) | Semiconductor manufacturing process and apparatus for modifying in-film stress of thin films, and product formed thereby | |
| US5851852A (en) | Die attached process for SiC | |
| JPS5933532B2 (en) | Method of forming amorphous silicon | |
| CN101246933A (en) | Soldering pad manufacturing process used for LED Epi wafer | |
| JPS60211825A (en) | Thin film semiconductor element | |
| JPS59208789A (en) | Solar cell | |
| JPS59117115A (en) | Method of producing semiconductor device | |
| US5821174A (en) | Passivation layer of semiconductor device and method for forming the same | |
| US9728705B2 (en) | Metallization having high power compatibility and high electrical conductivity | |
| JPH0832094A (en) | Thin film semiconductor solar cell and manufacture thereof | |
| JPS6249753B2 (en) | ||
| JPH084095B2 (en) | Method for manufacturing semiconductor device | |
| JPS62113483A (en) | Thin-film solar cell | |
| JPH06192828A (en) | Semiconductor target | |
| JPH0224030B2 (en) | ||
| JPS63185052A (en) | Tantalum metal thin film circuit | |
| US20220341035A1 (en) | Electrode and method for production | |
| JPS61264350A (en) | Electrophotographic sensitive body | |
| JPS59167071A (en) | Amorphous silicon solar battery | |
| JPH065771B2 (en) | Manufacturing method of photovoltaic device | |
| JPS6310590B2 (en) |