JPS60211694A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate two-way serial continuous reading by controlling a serial output of reading information of plural memory arrays by means of time series selection signals outputted from a timing generator circuit in responding to an up/down counter. CONSTITUTION:In accordance with the counted value of an up/down counter CONT, a time series selection signal is outputted from a decoder DCR of a timing generator circuit in directions corresponding to an up counted value and a down counted value. Drive stage circuits DV0-3 of memory arrays MARY0-3 read out simultaneously by a common address are driven, and serial outputs of the arrays MARY0-3 are controlled. Therefore, two-way serial continuous reading in desired directions can be executed at a high speed without use of a shift register, etc.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is effective for use in a semiconductor memory device that has a function of serially outputting data consisting of a plurality of bits/1 read in parallel.

[Background technology]

For example, in the case of random access memory (RAM), an access method called nibble mode has been proposed in addition to a method of accessing in 1-bit units (for example, 11).Hitachi, Ltd. P of the Hitachi IC Memory Data Book J published in March.
307-P, 32'0). In this nibble mode, for example, 4-bit data is serially output by a selection signal formed by the counting output of a shift register or binary counter that operates in synchronization with the column address I-LL signal CAS. It is possible that

Through research conducted by the inventor of the present application, it has been discovered that such a serial output method has the following drawbacks. In other words, the readout order is determined by the operation of the shift register or counter circuit, so for example, the data of the second focus is read out first, and then the data of the first focus is read out. If desired, the above-mentioned first bit data is output after performing a 3-bit shift operation in the shift register described in (h) and performing a 3-bit 11-number operation in the counter circuit. Therefore, a long time is spent on reading in the opposite direction to the operation of the shift 1-[/ register or counter circuit. This becomes an even bigger drawback in the byte mode in which 8-bit serial output is performed.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of speeding up serial continuous reading in both directions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this field is as follows.

That is, by serially outputting complement bit data read out in parallel using a selection signal formed according to the counting output of the up/down counter, high-speed bidirectional serial continuous reading is realized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment in which the present invention is applied to a dynamic RAM. In the figure, one memory array M out of a plurality of memory arrays is
ARYO and its peripheral circuits are shown as representatives. Note that other memory arrays M-ARYI to MARY3
The selection operation is also performed by the common peripheral circuit or internal address signal.

In the example circuit shown in the figure, O3FE between n channels
I CF E T (I n5ulat
edGate Field Effect, Tran
This will be explained using the example ``sister''.

The 1-bit memory cell MC has information record 1! as shown as a representative. Consists of capacitor Cs and address selection MOS FET Qm, logic "1"
, "0" information is stored in the form of whether there is charge in the capacitor Cs or not.

To read information, turn on the MOS FET Qm, connect the capacitor C3 to the common data line DL, and check how the potential of the data line DL changes depending on the charge accumulated in the capacitor C8. This is done by sensing what happens.

Although not particularly limited, a dummy cell DC is provided as a reference for detecting such a minute signal.

This dummy cell DC is manufactured under the same manufacturing conditions and with the same design constants as the ribbed cell MC in that the capacitance value of its capacitor Cd is approximately half that of the capacitor C8 of the memory cell MC. Capacitor Cd is charged to ground potential by MO3FET Qd' prior to addressing.

As described above, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor Cs, it forms a reference voltage that is approximately equal to half the read signal from the memory cell MC.

In the same figure, SA is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by a timing signal (sense amplifier control signal) Its input and output nodes are coupled to lines DL and DL. This sense amplifier S A Lf, 44 (7) AC M
u st It has MO3FETs Q1°Q2, and their positive feedback action differentially amplifies minute signals appearing on complementary data lines DL and DL.

The number of memory cells coupled to complementary data lines DL, DL is made equal to increase detection accuracy, and 1llil dummy cells are coupled to each of DL, DL. Furthermore, each memory cell MC is coupled between one word line WL and one of the complementary pair data lines. Each word line W
Since L crosses both data line pairs, the word line W
Even if a noise component generated in L is transferred to the data line due to capacitive coupling, the noise component appears equally on both data line pairs DL, DL, and is canceled out by the differential sense amplifier SA.

In the above addressing, "ζ", complementary data line pair DL,
When a memory cell MC coupled to one of DL is selected, one of a pair of dummy word lines DWL, DWL is selected so that a dummy cell DC is always coupled to the other data line.

During the above atranging, the stored information number of the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high level or low level potential obtained by this sensing operation.

However, as mentioned above, the high level is the power supply voltage Vc
When c drops by more than a certain degree, several readings occur,
While rewriting is repeated, a malfunction occurs where the logic is read as "0".An active restore circuit is provided to prevent this malfunction.
It is R. In this active restore circuit, there is a movement to selectively boost (voltage) only the J level signal to the potential of the electric voltage Vcc without any influence on the low level signal.

The data line pair DL shown as a representative on the same day,
DL is MO3FETQ that constitutes column switch CW
3. Common complementary data line pair CI)L, CD via Q4
Connected to L. Similar MO3FETQ5. It is connected to the common complementary data line pair CDL, CDL via Q6. The common complementary data line pair CDL, CDL has a long terminal of the data output cover sofa DOB and an output terminal of the data input cover sofa DIB including the main amplifier MA, the driving circuit 1iDV and the output circuit OB, respectively, as described later. Connected.

The row decoder and column decoder RC-DCR receives an internal complementary address signal formed by the address buffer ADB, forms one word line, a dummy word line, and a column switch selection signal to address memory cells and dummy cells. conduct. That is, the external address signals AXO-AXn are taken into the address buffer ADB in synchronization with the timing signal par generated by the row address strobe signal #W, and the external address signals AXO-AXn are input to the address buffer ADB.
In addition to transmitting the signal to the DCR, predetermined word line and dummy word line selection operations are performed using the word line selection timing signal φX. And column address strobe signal CAS
YO-AYn is sent to the external address signal in synchronization with the timing signal φac generated by the address buffer ADB.
At the same time, data lines are selected by data line selection timing signal φy.

FIG. 2 shows a circuit diagram of an embodiment of the data output cover sofa circuit DOB and the timing generation circuit TG that controls its operation when realizing the nibble mode function of serially transmitting 4-pin data. There is.

Although not particularly limited, in this embodiment, four sets of memory arrays MARYO to MARY3 are configured, and four main amplifiers MAO-MA3 amplify respective read signals.
(not shown) are respectively supplied to the next driving circuit vIrDVO-DV3. In the same figure,
Drive stage circuits DVO and DV3 are shown as representatives.

That is, the drive stage circuit DVO receives the timing signal φop.
Between the terminal to which Q is supplied and the ground potential point of the circuit, there is a synchronized data signal douto from the main amplifier MAO.
, a bush-pull MO that receives d outo crosswise.
3FET QI O, Ql 2 and Qll.

Supplied by Ql3 Gate Inc. That is, the inverted output signal doutO is supplied to the gates of MO3FETQIO and Ql3, and the non-inverted output signal doutO is supplied to the gates of MO3FETQIO and Ql3.
Supplied to the gates of Q11 and Ql2.

Above MO3FETQI O and Ql2 and MO3FETQ
The signal obtained from the connection point of 11 and Ql3 is supplied to the gate of the next bush-pull type output MO5FET QI4°Ql5. Zuwanaji, MO3FETQIO and Ql2
The signal at the connection point is the output MO3FETQ1 on the ground potential side.
5 gates. The signal at the connection point of MO3FETQI1 and Ql3 above is the output MO3 on the power supply voltage Vce side.
Supplied to the gate of 3FETQ14.

The remaining drive stage circuits DVI to DV3 and output circuits OB1 to O
B3 is also constructed from a circuit similar to the above.

The output terminals of the output circuits 0BO to OB3 are shared, in other words, connected to one output terminal Dout in a wired-OR configuration.

The timing signals φopQ to φop3 supplied to each of the drive stage circuits D'VO to DV3 are generated by the following timing generation circuit TG.

Although not particularly limited, the timing generation circuit TG includes an up/down counter circuit C0NT and a decoder circuit DCR that receives the count output signal of the up/down counter and forms the timing signals φopQ to φop3. Above up/down counter C0N
2-bit address signals AXi and AYi are taken into T as their initial values. That is, by supplying binary information specifying the memory array to be output first to the up/down counter C0NT, time-series reading is performed sequentially from any memory array according to the counting operation of the up/down counter CON. It is something. In other words, the up/down counter C0NT
Although not particularly limited, the initial value is taken in by the first low level of the column address strobe signal qCAS. And column address strobe signal CA
Since the amplifier or down counting operation is performed every time S is returned to the high level and then set to the low level, the read signal of the memory array incremented by +1 or -1 can be obtained from the first specified arbitrary memory array. It is possible to do this. Although not particularly limited, the up/down control signal U/D may be supplied by providing a specific external terminal, or if the row at/slope signal RAS after taking in the row address signal is at a low level. It is formed by making it an amplifier signal and changing it to a high level to make it a down signal (not shown).
.

A timing signal φopo~ is generated by a decoder DCR receiving the count output of the up/down counter circuit C0NT.
φop3 is formed chronologically. As a result, the four drive stage circuits DVO to DV3 selectively operate one after another, so it is possible to realize a pull mode in which read signals from the four memory arrays are serially output.

Note that the drive stage circuits DVO to DV3 are rendered inactive by the low level of the timing signals φopo to φop3.
makes its output low level, so the output circuit OBO
~OB3 becomes a high impedance state, and the output signals of the output circuits OBO~OB3 that receive signals supplied through the drive stage circuits DVO~DV3 activated by the high level of the timing signals φopo~φop3 are output from the data output terminal Dout. It is something that is sent out.

〔effect〕

(1) By using an up/down counter circuit to specify the output order of read signals from multiple memory arrays, it is possible to always obtain output signals at the highest speed in both directions. can get. For example, specify memory array MARYI, then memory array M
When outputting a read signal from ARY2 or memory array MARYO, by performing an amplifier or down operation of the counter circuit, the above-mentioned wasted operation cycles are not generated, and the output is performed at the highest speed. It is something that can be done.

(2) According to (1) above, it is possible to obtain a semiconductor memory device having an easy-to-use serial output function.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the drive stage circuit and the output circuit can be anything, as long as the output circuit is in a high impedance state during the non-operating period according to a timing signal, and the signal from the main amplifier is supplied to the output circuit during the operating period. It's okay. Further, the timing generation circuit supplied to the drive stage circuit may be of any type as long as it forms a time-series timing signal according to the operation of the up/down counter circuit. Furthermore, when using a column address strobe signal as an input signal for performing the counting operation of the up/down counter circuit,
Various embodiments can be adopted, such as one using one shot pulse formed at the timing of the change, or one in which the input signal is supplied from an external terminal.

Furthermore, the number of bits to be output and the number of divisions of the memory array can be modified in various ways, such as a byte mode in which the memory array M A RY is divided into eight and 8-bit data is serially output.

[Application field]

The above explanation will mainly focus on the dynamic type R
Although we have explained the case where it is applied to AM, it is not limited to this, and it can be applied to Sukti Sok type RAM, ROM (
By applying the present invention, even a device such as a read-only memory (read-only memory) can be widely used as a semiconductor memory device having a function of serially reading data of multiple bits in both directions.

[Brief explanation of drawings]

Claims (1)

[Claims] 1. A memory array that is divided into a plurality of parts and selected by a common address signal, and a plurality of read signals from each divided memory array according to a selection signal formed in time series. An output circuit that outputs serially, an up/down counter circuit that performs counting according to a predetermined timing signal, and a timing generation circuit that receives the counting output signal of the up/down counter circuit and forms the above-mentioned time-series selection signal. A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the timing signal supplied to the up/down counter circuit is a signal formed according to a column address strobe signal supplied from an external terminal. 3. The semiconductor memory device according to claim 1 or 2, wherein the up/down counter circuit is supplied with a decoded output of a specific external address signal as an initial value. 4. A plurality of main amplifiers, drive stage circuits, and output amplifier circuits are provided according to the number of the memory arrays divided into the plurality of memory arrays, and the drive stage circuit is time-selected by the time-series selection signal. Claim 1, characterized in that the device enters the operating state in series,
The semiconductor memory device according to item 2 or 3.