JPS60208841A - Manufacture of dielectric separating substrate - Google Patents

Abstract

PURPOSE:To prevent the breakdown at the outer surface part of the raw material of a dielectric separating substrate during polishing processes, by performing chamfering in the first process of the polishing processes, predicting a part, which is to become the dielectric separating substrate at the end of the polishing processes, and performing machining, by which the outer surface part of the divided substrate becomes a round shape. CONSTITUTION:Chamfering of the raw material of a dielectric separating substrate 11 is performed in polishing processes. Thereafter, a supporting layer 15 on one surface of the raw material of the separating substrate 11 and a semiconductor single-crystal layer 12 on the other surface thereof are polished to the specified thicknesses, respectively. A part, which is to become the separating substrate at the end of the polishing processes (a part enclosed by broken lines 16 and 17 in the Figure), is predicted beforehand, and the chamfering is performed so that the outer surface of the separating substrate becomes a round shape. The polished and removed parts on both sides of the predicted part are formed in slant surfaces, which are continued to the round shape.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a dielectric isolation substrate, and more particularly to a method for chamfering a dielectric isolation substrate material. O (Prior Art) A conventional method for manufacturing a dielectric isolation substrate, particularly a polishing process of a dielectric isolation substrate material, will be explained with reference to FIGS. 1(a) to 1(e).

In FIG. 1(a), 1 is a dielectric isolation substrate material, and this isolation substrate material 1 is made by forming a V-groove 3 on the surface (lower surface in the figure) of a silicon single-crystal substrate 20. It is constructed by depositing an insulating film 4 on the surface of the substrate 2 including the inner wall, and further forming a polycrystalline silicon layer 5 as a support layer on this insulating film 4 (below the insulating film 4 in the figure). Ru. - The surface side (lower surface side in the figure) of the silicon polycrystalline layer 5 of this dielectric isolation substrate material 1 is polished so that the surface will serve as a flat reference surface in the subsequent process (FIG. 1(b)). The amount of polishing here is within a range that still ensures a sufficient thickness of the silicon polycrystalline layer 5 as a support layer.

Next, using the flat surface of the silicon polycrystalline layer 5 as a reference plane, the silicon single crystal substrate 20 birth surface side (top surface side in the figure) is
Polish and remove the polishing material to a thickness that leaves a polishing residue on the bottom of @3 (Fig. 1 (C)).

After that, the outer periphery of the dielectric isolation substrate material 1 is shown in FIG.
), process the chamfer into a round shape. This chamfering process can be performed by grinding with a profiling whetstone, as described in, for example, Semiconductor World March 1983 issue, pages 53 to 58.

Thereafter, the drawing side of the silicon single crystal substrate 2 is polished and removed until the bottom of the groove 3 is exposed, as shown in FIG. 1(e).

With this, the dielectric isolation substrate is completed.

By the way, when forming the silicon polycrystalline layer 5 in order to manufacture the dielectric isolation substrate material 1 shown in FIG. Since the dielectric isolation substrate material 1 is elongated, the edge shape of the outer peripheral portion of the dielectric isolation substrate material 1 is uneven, or a sharp portion is formed at the edge portion. Therefore, in the above-mentioned method in which chamfering is not performed until the final polishing, the outer periphery of the dielectric isolation substrate material 1 is often chipped and defective during the polishing process up to the multiple chamfering steps. .

To solve this drawback, it is best to perform chamfering as the first step of the polishing process. However, in that case, the shape during chamfering may change significantly upon completion of polishing, and the chamfering may become meaningless. For example, in Figure 2 (a
) As shown in Figure (b), the silicon single crystal substrate 2 side, which had a round shape during the chamfering process, but which requires a particularly large amount of polishing removal after polishing is completed, as shown in Figure (b). A sharp shape was formed at the edge portion 6, which caused chipping during the device process.

(Objective of the Invention) The present invention has been made in view of the above points, and its purpose is to prevent the outer periphery of the dielectric isolation substrate material from being chipped during the polishing process, and to prevent sharp edges from forming on the outer periphery of the substrate upon completion of polishing. An object of the present invention is to provide a method for manufacturing a dielectric isolation substrate that can accurately obtain a round shape without any rough parts.

(Summary of the Invention) The main point of this invention is to perform chamfering in the first step of the polishing process, and at that time, predict in advance the portion that will become the dielectric isolation substrate upon completion of the polishing process, and 1, so that the part has a round shape, and whether the outer peripheral part of the polishing removed part inside the predicted part is continuous with the round shape.
The purpose is to perform a chamfering process to create a flat surface.

(Example) An embodiment of the present invention will be described below with reference to FIG.

In FIG. 3(a), reference numeral 11 is a dielectric isolation substrate material.
3 with a pulse length of about 10 to 50 μm, then the V groove 1
An insulating film 14 made of a thermal silicon oxide film is coated to a thickness of about 1 μm on the surface of the substrate 12 forming the inner wall of the substrate 3, and a silicon support layer is further formed on this insulating film 14 (below the insulating film 14 in the figure). The polycrystalline layer 15 is formed to have a thickness of approximately 350 μm to 420 μm. If we predict the portion of this separation substrate material 11 that will remain as a dielectric separation substrate upon completion of the polishing process, it will be a region having a thickness component t (350 to 400 μm) surrounded by the broken line 16.17 in the figure. Here, the broken line 16 is determined at the position of the accurately controlled bottom of the V-groove 13, and the broken line 817 indicates the position of the silicon polycrystalline layer 15 after standard leveling; The thickness can be arbitrarily determined as long as the layer 15 has a thickness equivalent to that of the support layer.

Next, surface J4I2 is processed on the separated board cable material 11. At that time, the chamfering process is performed so that the outer periphery of the part that will become the separated substrate surrounded by broken lines 16 and 17 has a round shape, as shown in FIG. This is done so that the outer periphery of the removed portion becomes a slope that continues into the round shape. That is, on the back surface (upper surface in the figure) 18 of the silicon monocrystalline substrate 12 and the surface (lower surface in the figure) 19 of the silicon polycrystalline layer 15,
The chamfer width (50 to 500 μm) shown by and B actually exists, and also on the surface shown by broken lines 16 and 17 A'
The chamfer shape is defined as the condition that the chamfer widths (10 to 30 μm) of i and B' exist. In this example, the thickness component is defined as a circle with a radius of % centered near the center line 20 of the region and the surfaces of surfaces 18 and 19.
It was made into a round shape with a slope connecting to the contact point of the circle at the corner.

Next, the surface 1tll (lower surface side in the figure) of the silicon polycrystalline layer 15 is polished down to the position of the temporary line 17 as shown in FIG. 3(C), and the reference surface 19' is leveled.

Thereafter, with the surface 19' of the silicon polycrystalline layer 15 as a reference, the shell side (upper surface side in the figure) of the silicon single crystal substrate 12 as a semiconductor single crystal layer is placed on the bottom of V~13 to achieve the longest finish. The polishing removal device is removed by polishing until the thickness remains (FIG. 3(d)).

Thereafter, the back side of the silicon single crystal substrate 12 is polished as a final polishing leg, as shown in FIG. 3(e).
Polish and remove until the bottom of V#13 is exposed. As a result, a dielectric isolation substrate is optically formed.

Incidentally, in the above method, the surface I@ processing can be performed using a profiling grindstone as described in the document B listed in the section of the prior art. Further, the silicon polycrystalline layer 15 and the silicon single crystal substrate 12 can be polished by grinding with a grindstone or by lapping.

(Effects of the Invention) As is clear from the above embodiment, according to the method of the present invention, chamfering is performed at the beginning of the polishing process. Therefore, chipping of the outer periphery of the dielectric isolation substrate material during the polishing process can be prevented.In the conventional method, the probability of chipping occurring was about 90 inches, but with this invention, this can be reduced to zero. Ta.

Furthermore, according to the method of the present invention, the part that will become the separated substrate upon completion of the polishing process is predicted in advance, and the chamfering process is performed so that the outer periphery of the separated substrate has a round shape. Even at times, it is possible to accurately obtain a round shape with no sharp parts on the outer periphery of the substrate. Therefore, chipping will not occur in the device process.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing a conventional method for manufacturing a dielectric isolation substrate, Fig. 2 is a cross-sectional view illustrating problems caused by a method for solving the drawbacks of the method shown in Fig. 1, and Fig. 3 is a cross-sectional view showing the method according to the present invention. FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a dielectric isolation substrate. DESCRIPTION OF SYMBOLS 11... Electric isolation plate material, 12... Silicon single crystal substrate, 13... V#, 14... Insulating film, 15...
...Silicon polycrystalline layer. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] After chamfering the dielectric separation substrate material in a polishing process, the support layer on one side of the separation substrate material and the semiconductor single crystal layer on the other side are each polished to a predetermined thickness. In addition, the chamfering process is performed by predicting in advance the part that will become the separated substrate upon completion of the polishing process, so that the outer periphery of the separated substrate will have a round shape, and the outer periphery of the polishing removed portion on both sides of the predicted part. A method for manufacturing a dielectric isolation substrate, characterized in that the step is performed so that the slope forms a continuous slope with the round shape.