JPS602085A - Speed controller for motor - Google Patents

Speed controller for motor

Info

Publication number
JPS602085A
JPS602085A JP58108692A JP10869283A JPS602085A JP S602085 A JPS602085 A JP S602085A JP 58108692 A JP58108692 A JP 58108692A JP 10869283 A JP10869283 A JP 10869283A JP S602085 A JPS602085 A JP S602085A
Authority
JP
Japan
Prior art keywords
signal
motor
multiplied
circuit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58108692A
Other languages
Japanese (ja)
Inventor
Kazuo Horikawa
堀川 一夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP58108692A priority Critical patent/JPS602085A/en
Publication of JPS602085A publication Critical patent/JPS602085A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/16Controlling the angular speed of one shaft

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE:To accurately control a motor with an inexpensive electric circuit by raising the resolution by multiplying the output signal of an encoder. CONSTITUTION:The title controller has a rotary encoder 10, a multiplier 20 for multiplying the output signal, a multiplication signal number discriminator 40 for discriminating what the multiplication signal is in number, a memory 50 for storing the periodic error data between the multiplication signals measured in advance in response to the signal number of the multiplication signal, an error signal generator 60 for generating the error signal by reading out the periodic error signal corresponding to the multiplication signal number from the memory, a control circuit 80 for generating a motor control signal SC corrected for the periodic error of the multiplication signal by inputting the signal, and a drive circuit 100 for driving the motor 1 by the motor control signal SC.

Description

【発明の詳細な説明】 本発明は、モータの回転速度17−Cは回転位置ケロー
タリーエンコーダにより検出し、その検出信号音基準信
号と比較し得らnる差信号によジモータの速度?制御す
るモータの速度制御装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION In the present invention, the rotational speed 17-C of the motor is detected by a rotational position rotary encoder, and the detected signal is compared with a sound reference signal to determine the motor speed? The present invention relates to a speed control device for a motor to be controlled.

従来、モータの速度制御装置として1例えは。One example is a conventional motor speed control device.

パルス発生器tモータのロータ軸に直結してそnから出
力さnるパルス信号音検出し、これと基準ノξルス信号
と全比較して速度偏差信号?得、この偏差信号に比例し
罠信号にエリ速度全制御するようにし7ζものが広く用
1hC)n−でいる。
A pulse generator directly connected to the rotor shaft of the motor detects the pulse signal sound outputted from it, and compares this with the reference norm signal to obtain a speed deviation signal. In addition, the trap signal is proportional to this deviation signal, and 7ζ is widely used in order to fully control the speed of the trap signal.

上述のパルス発生器としては、磁気?用いる方式や光学
式のものがあるが、最近広く用いら九でいるのが光学式
のものであり、ロータリーエンコーダと言えばほとんど
が光学式のもの全指すようになっている。
Is the pulse generator mentioned above magnetic? There are different types of encoders and optical types, but recently the optical type is the most widely used type, and rotary encoders are now referring to all types of optical type encoders.

現在市販さnている光学式ロータリーエンコーダには、
その用途に応じて種々の分解能(7回当りの分割数)?
持つものがあり1分解能が晶くなるにつnてその価格も
急赦に高くなっている。例えばi、ooθパルス/回転
程度の分解能のものであILば、2〜3万円以下、S、
OOθパルス/回転程度の分解能のものでt6io万円
程度、10゜000 /eルス/回転以上の高分解能の
ものになnば30万円以上と高価格になる。
Optical rotary encoders currently on the market include:
Various resolutions (number of divisions per 7 times) depending on the purpose?
As more and more devices have crystallized resolution, their prices are rapidly increasing. For example, if the IL has a resolution of i, ooθ pulse/rotation, it will cost less than 20,000 to 30,000 yen, S,
A device with a resolution of about OOθ pulses/rotation costs about 60,000 yen, and a device with a high resolution of 10°,000 pulses/rotation or higher costs more than 300,000 yen.

し罠がってモータを高精度に低速度で速度制御する罠め
に高分解能のロータリーエンコーダを用する場合にはコ
ストアップが避けらnなめ。
However, if a high-resolution rotary encoder is used to control the motor at a low speed with high precision, an increase in cost is unavoidable.

本発明はこのような事情に鑑みなされ罠もので。The present invention was created in view of these circumstances.

安価な低分解能のロータリーエンコーダ?用いてモータ
の速度制御?高精度にしかも安価VC笑現しうる速度制
御装置を提供することを目的とするものである。
An inexpensive low-resolution rotary encoder? Use motor speed control? It is an object of the present invention to provide a speed control device that is highly accurate and can be implemented as an inexpensive VC.

本発明の速度制御装置は、安価な低分解能のロータリー
エンコーダを用い、その出力を逓倍して分解能を上げる
ようにし罠ものであり、逓倍することにより生じる逓倍
信号の周期誤差を予め測定しておき1周期誤差?補正し
罠モータの制御信号を得て制御の精#會上げるようにし
χもので、モータの回転子の回転速度せ7?:は回転位
置?検出するロータリーエンコーダと、このロータリー
エンコーダの出力信号を逓倍して逓倍信号を発生させる
逓倍回路と、この逓倍回路[接続さn前記逓倍信号が何
番目の信号であるかを判定する逓倍信号番号判定回路と
、予め測定さnyc iiJ記逓倍信号間の周期誤差デ
ータを前記逓倍信、号の信号番号と対応づけて記憶した
メモリを有し、前記逓倍信号番号判定回路の判定結果に
もとづいて、その逓倍信号番号に対応する前記周期誤差
データ?前記メモリより読み出して誤差信号を発生させ
る誤差信号発生回路と、前記誤差信号を入力して前記逓
倍信号の周期誤差が補正されπモータ制御信号音発生さ
せる+aIJ御回路と、前記モータ制御信号により前記
モータを駆動する駆動回路と金有することを特徴とする
ものである。
The speed control device of the present invention uses an inexpensive low-resolution rotary encoder and multiplies its output to increase the resolution.The periodic error of the multiplied signal caused by multiplication is measured in advance. 1 cycle error? The control signal of the trap motor is corrected and the control signal is obtained to improve the control. : Is it the rotation position? A rotary encoder to be detected, a multiplier circuit that multiplies the output signal of the rotary encoder to generate a multiplier signal, and a multiplier signal number determination device that determines the number of the multiplied signal. and a memory that stores periodic error data measured in advance between the multiplied signals in association with the signal number of the multiplied signal, based on the judgment result of the multiplied signal number judgment circuit. The periodic error data corresponding to the multiplication signal number? an error signal generation circuit that reads out the error signal from the memory and generates the error signal; an +aIJ control circuit that inputs the error signal to correct the periodic error of the multiplied signal and generates a π motor control signal sound; It is characterized by having a drive circuit for driving a motor and a metal.

以下1図面ケ用いて本発明の笑施態様について詳aIに
説明する。
Hereinafter, embodiments of the present invention will be explained in detail with reference to one drawing.

u!/図は本発明の一実施態様を示すモータの速度制御
装置全体の構成を示すブロック図である。
u! 1 is a block diagram showing the overall configuration of a motor speed control device according to an embodiment of the present invention.

第1図において、ロータリーエンコーダ10はモータl
のロータ軸にカップリングにより連結さ1]、ており、
りOoの位相差を持り7てλつの正弦波信号?出力する
ものである。
In FIG. 1, a rotary encoder 10 is connected to a motor l.
It is connected to the rotor shaft by a coupling 1],
7λ sine wave signals with a phase difference of Oo? This is what is output.

逓倍回路、20は、ロータリーエンコーダ/θからのり
O゛位相差を持つ罠2つの正弦波信号を合成して元の正
弦波の1周期の間に互いに等しい位相差を有する複数の
中間的位相?持つ正弦波信号全作り、こうして得られる
複数の互いに等しい位相差を有する正弦波信号を波形整
形して得られる矩形波全組合わせて1元の正弦波の/周
期の間に複数の短形波を発生させる回路である。
The multiplier circuit 20 synthesizes two sine wave signals having a phase difference of O゛ from the rotary encoder/θ and generates a plurality of intermediate phase signals having mutually equal phase differences during one period of the original sine wave. Create a complete sine wave signal with the same phase difference, and shape the resulting multiple sine wave signals with equal phase differences to form a rectangular wave. Combine all of the rectangular waves obtained during the period of one original sine wave. This is a circuit that generates

一般に元の信号の一周期の間<’n個の@号音発生させ
る場合n逓倍するというが、逓倍信号番号判定回路po
はn個の逓倍信号のうち何査目の信号であるか全判定す
る回路である。
Generally, when <'n @ sound signals are generated during one period of the original signal, it is said to be multiplied by n.
is a circuit that completely determines which scan-th signal it is among the n multiplied signals.

メモリtoは、予め測定さ7’lπ迎倍信号の周期誤差
データをその逓倍信号の信号番号と対応づけて記憶し罠
ものである。
The memory to stores period error data of the 7'lπ multiplied signal measured in advance in association with the signal number of the multiplied signal.

誤差信号発生回路ΔOは、逓倍信号番号判定回路弘0の
逓倍信号番号判定回路にもとづいてその逓倍信号番号に
対応する周期誤渋データ?メモリ!Oから読み出して誤
差1g号ケ発生させる回路である。
The error signal generation circuit ΔO generates cycle error data corresponding to the multiplication signal number based on the multiplication signal number judgment circuit of the multiplication signal number judgment circuit HIRO0. memory! This is a circuit that reads data from O and generates an error of 1g.

制御回路ざOは、誤差信号発生回路toからの誤差信号
を入力して此倍信号の周期誤差の補正紮行ない、周期誤
差の補正さf′したモータの制御信号全発生させる回路
である。
The control circuit O is a circuit that receives the error signal from the error signal generation circuit to, corrects the periodic error of the multiplied signal, and generates all the motor control signals whose periodic errors have been corrected f'.

駆動回路100は、制御回路♂Oがらのモータの制御信
号によりモータl′に駆動する罠めの回路である。
The drive circuit 100 is a trap circuit that drives the motor l' using a motor control signal from the control circuit ♂O.

以上が速度制御装置全体の構成であるが1次に上述の各
回路について詳細に説明する。
The above is the overall configuration of the speed control device. First, each of the above-mentioned circuits will be explained in detail.

第2図は逓倍回路20の詳細ヲ示すブロック図である。FIG. 2 is a block diagram showing details of the multiplier circuit 20.

ロータリーエンコーダIOからの互いに20°の位相差
ケ持つ71ニー2つの正弦波すなわち5ine、cos
ine の信号は各合成回路コl〜コjに入力さ九、第
3図(A ) fc示すような合成されて位相がずれπ
正弦波信号S2〜S5.丁なゎち振幅が同じで位相が3
t0ずっすtl−π正弦波が作らnる。罠だし合成回路
21については。
71 knee two sine waves with 20° phase difference from each other from rotary encoder IO i.e. 5ine, cos
The signals of ine are input to each of the synthesis circuits l to j, and are synthesized as shown in Fig. 3 (A) fc with a phase shift of π.
Sine wave signals S2 to S5. The amplitude is the same and the phase is 3.
A sine wave t0 is created by tl-π. Regarding Tradashi Synthesis Circuit 21.

5ine−cosin? のイg号は合成されないで正
弦波信号S1がそのまま出力さ几る。波形成形回路、2
6〜30は、正弦波信号s、−8s全−8s會B)に示
すような短形波信号SRI〜sR5に波形成形する。次
に短形波信号SRI〜SR5は演算回路3/vc入力さ
九論理的に組合わされて、第3図(C)に示すように信
号レベルlの信号が偶数個加えらt″L、π場合に信号
レベルlの信号を発生させ。
5ine-cosin? The signal Ig is not synthesized and the sine wave signal S1 is output as is. Waveform shaping circuit, 2
6 to 30 are waveform-shaped into rectangular wave signals SRI to sR5 as shown in sine wave signals s, -8s total -8s B). Next, the rectangular wave signals SRI to SR5 are input to the arithmetic circuit 3/vc and are logically combined, and as shown in FIG. In this case, a signal of signal level l is generated.

元の正弦波信号S1の一周期がj逓倍さfL7(逓倍信
号Sm(Sm1〜Sm5)が演算回路3/49出力され
る。
One period of the original sine wave signal S1 is multiplied by j and a multiplied signal Sm (Sm1 to Sm5) is output from the arithmetic circuit 3/49.

このようにして作らn7(逓倍信号にはその周期(信号
と信号との間隔NC電気回路に起因する誤差が含まnる
。丁なわち正弦波(g号82〜S5は電気回路にエリ合
成して発生させているものであり、各正弦波信号81〜
S5の間の位相差にばらつきが生じる。従って逓倍信号
Sm1〜Sm5の周期にばらつきが生じ、このばらつき
を補正しな−と精度の高い逓倍信号は得らnな論。なお
ロータリーエンコーダioからの出力すなわち正弦波信
号S1そのものの周期、および合成さn7(正弦波信号
82〜S5そのものの周期の精度は逓倍信号の周期の精
度に比較し極めて高い。
The multiplied signal created in this way includes an error due to its period (interval between signals, NC electric circuit). Each sine wave signal 81 to
Variations occur in the phase difference between S5. Therefore, variations occur in the cycles of the multiplied signals Sm1 to Sm5, and it is impossible to obtain highly accurate multiplied signals unless this variation is corrected. Note that the accuracy of the period of the output from the rotary encoder io, that is, the sine wave signal S1 itself, and the period of the synthesized signal n7 (sine wave signals 82 to S5 itself) is extremely high compared to the accuracy of the period of the multiplied signal.

次に逓倍信号Sm1〜Sm5の周期誤差?求め補正する
方法について説明する。
Next is the periodic error of the multiplied signals Sm1 to Sm5? The method of finding and correcting it will be explained.

回転子のイナーシャが大きく回転速度変動の少ない基準
となるモータに、用いよウトスるロータリーエンコーダ
10および逓倍回路2oを接続して、得らfLる逓倍信
号の周期を測定する。
The rotary encoder 10 and the multiplier circuit 2o to be used are connected to a reference motor whose rotor has a large inertia and a small variation in rotational speed, and the period of the obtained multiplied signal fL is measured.

第≠図は逓倍信号の周期誤差全補正する方法を説明する
πめの図であり、逓倍信号の先端位置(信号レベルがO
からlに変化する位置)のみ全表示しである。
Figure ≠ is a π-th diagram explaining the method of completely correcting the periodic error of the multiplied signal.
Only the position that changes from 1 to 1) is fully displayed.

第≠図(A)は、制御しようとする目標速度の時の理想
的な逓倍信号の周期?示す図である。
Figure (A) shows the ideal period of the multiplication signal at the target speed to be controlled. FIG.

第グ図(B)は、実際の周期誤差を含む逓倍信号Sm1
〜Sm5k示す図である。図において各信号Sm2、S
m3.Sm4.Sm5はそn−f:′n理想信号に対し
て△t2進み、△t3遅n、△t4遅几、△t5遅nの
周期誤差を有している。なお。
Figure (B) shows the multiplied signal Sm1 containing the actual periodic error.
It is a diagram showing ~Sm5k. In the figure, each signal Sm2, S
m3. Sm4. Sm5 has period errors of Δt2 leading, Δt3 delay n, Δt4 delay n, and Δt5 delay n with respect to the n-f:'n ideal signal. In addition.

この理想周期に対する周期誤差△t2〜△t5は例えハ
オシロスコープ等で実測可能である。この場合、理想信
号に対して最大の遅n、を持っ信号はSm15であるが
、この信号Sm5が理想信号に合致するように第≠図(
B)の信号列を図において△t5の距離だけ左側に移動
させ罠ものが第≠図(C)である。
The periodic errors Δt2 to Δt5 with respect to the ideal period can be actually measured using an oscilloscope or the like. In this case, the signal with the maximum delay n with respect to the ideal signal is Sm15, but the signal Sm5 matches the ideal signal as shown in Fig.
Figure (C) is a trap in which the signal train in B) is moved to the left by a distance of Δt5 in the figure.

第弘図(C)より明らかなように、逓倍信号の周期誤差
全補正するには、各信号S、1、Sm2、Sm3、Sm
4にそn−enΔt5、△t5+△t2゜△t5−△t
a、△t5−Δt4時間だけ遅延させるように丁nはよ
い。
As is clear from Fig. 1 (C), in order to completely correct the periodic error of the multiplied signal, each signal S, 1, Sm2, Sm3, Sm
4, n-enΔt5, △t5+△t2゜△t5-△t
It is better to delay the time by a, Δt5 - Δt4 time.

そこでまず逓倍(A号沓号判定回路≠Oについては、例
えば公知のカウンターとデコーダケ用いることができる
ので回路の詳#IFi省略するが、逓倍回路コθから順
次出力源ILる逓倍信号Sm1〜Sm5の信号番号全判
定して信号番号が/〜jのいづn−であるかを表わす信
号音出力する。
Therefore, first of all, regarding the multiplier (No. A signal determination circuit ≠ O, for example, a well-known counter and decoder can be used, so the details of the circuit #IFi are omitted, but the multiplier circuit θ sequentially outputs the multiplier signals Sm1 to Sm5 from the output source IL). All signal numbers are determined and a signal tone is output indicating whether the signal number is izn- of /~j.

次に誤差信号発生回路toは、上記逓倍信号番号判定回
路≠0の逓倍信号番号判定回路にもとづいてその逓倍信
号5rr11〜Sm5の信号番号/−jに対応する周期
誤差データ(逓倍信号r理想周期に合致さゼるπめに必
要な連延時1i41 ) ’にメモリs。
Next, the error signal generation circuit to generates periodic error data (multiple signal r ideal period 1i41)' memory s is required for the πth continuation that matches .

から読み出してその信号Sef制御回路ざOへ入力する
The signal Sef is read out and inputted to the control circuit ZO.

なおメモリ10は例えばPROMk用いることができ、
各信号番号に対応する予め測定さ′t12だ遅延時間が
記憶さnている。すなわち信号番号/[対応して△t5
.信号番号2T/C対応して△t5+△t2.信号番号
3に対応して△t5−△t3、(8号番号弘に対応して
△t5−△t4の遅延時間が記憶さ几ている。
Note that the memory 10 can be, for example, a PROMk,
A pre-measured delay time corresponding to each signal number is stored. That is, signal number/[correspondingly △t5
.. Corresponding to signal number 2T/C, △t5+△t2. Delay times Δt5-Δt3 are stored corresponding to signal number 3, and delay times Δt5-Δt4 are stored corresponding to signal number 8.

次V?:、第j図に制御回路にOの詳細を示すブロック
図ケ示す。
Next V? A block diagram showing the details of the control circuit is shown in Figure J.

ANDゲー1−J’/は逓倍信号Smと周期測定用クロ
ックが入力さnその出力がカウンターJlに入力さnる
。カウンターざ2は逓倍信号5rTlの立ち上りのタイ
ミングでリセットパルスRが入力さf′1.基準クロッ
ク全カウント開始する。カウント信号は順次コンパレー
タざ3に入力さnる。コンパレータr3ぼメモリーjO
から読み出さtl−罠周期呟差データ信号Seとカウン
ター1.2からの基準クロックのカウント数とを比較し
て、その差がθとなnば信号St比出力る。すなわちコ
ンパレータざ3からは、逓倍信号Smを周期誤差データ
信号Seの時間だけ遅延させπ周期誤差が補正さnた逓
倍信号Sが出力さnる。
The AND game 1-J'/ receives the multiplied signal Sm and the period measuring clock, and its output is inputted to the counter Jl. A reset pulse R is input to the counter 2 at the timing of the rise of the multiplied signal 5rTl. Start counting all reference clocks. The count signal is sequentially input to the comparator 3. Comparator r3 memory jO
The tl-trap cycle difference data signal Se read from the counter 1.2 is compared with the count number of the reference clock from the counter 1.2, and if the difference is θ, a signal St ratio is output. That is, the comparator 3 outputs a multiplied signal S which is obtained by delaying the multiplied signal Sm by the period of the periodic error data signal Se and correcting the π periodic error.

周期が補正さf′Lπ逓倍信逓倍信号比較回路r≠で速
度設定用の基準信号S。と比較さn、この差信号によっ
てモータ/が制御さ1−る。この比較回路J4は、モー
タ/の制御方式によって種々の公知の方式ケ用いること
ができ、例えば基準信号S。
The period is corrected and the reference signal S for speed setting is obtained by f′Lπ multiplication signal multiplication signal comparison circuit r≠. The motor is controlled by this difference signal. This comparison circuit J4 can use various known methods depending on the control method of the motor, for example, the reference signal S.

と周期が補正され疋逓倍信+58との位相の差を検出し
て、その差に応じ罠モータ制御信号S。音発生させる方
式のものであっても良いし、基準信号Soの周期(基準
速度に対応)と周期が補正さnπ逓倍侶信号の周期(モ
ータケ制御中の失透に検出さnる速度に対応)との差?
検出してその差に応じ罠モータ制御仏号S。音発生させ
る方式のものであっても良い。まπ両方式を併用しπも
のであってもよい。
The period is corrected and the phase difference between the multiplication signal +58 is detected and the trap motor control signal S is generated according to the difference. It may be of a type that generates a sound, or the period of the reference signal So (corresponding to the standard speed) and the period of the nπ multiplier signal (corresponding to the speed detected by devitrification during motor control) whose period is corrected. )?
Detect and control the trap motor according to the difference. It may also be of a type that generates sound. Alternatively, both the π and π expressions may be used in combination.

扇動回路100はモータ制御イぎ号S0によって周期が
補正され罠逓倍信号S’に基$信号S。に一致させるべ
く、すなわち位置ず1、ま7?:は速度すn會Oとする
ように、モータ/の回転子全回転駆動させる回路である
The agitation circuit 100 generates a $ signal S based on the trap multiplication signal S' whose period is corrected by the motor control signal S0. , i.e. position 1, 7? : is a circuit that drives the rotor of the motor to full rotation so that the speed is set to O.

前述の制御回路♂Oは、周期誤差が補正さn、7(逓倍
信号Sと基準信号S。と全比較して周期誤差が袖止さ7
’l 7cモ一タ制御1g号S。音発生させるようVC
+14 lJy、さnているが、第を図Vこ示すような
方式によって周期誤差が補正さn罠モータ制御信号S。
In the control circuit ♂O mentioned above, the periodic error is corrected n, 7 (the multiplied signal S and the reference signal S.
'l 7c motor control 1g S. VC to generate sound
+14 lJy, but the periodic error is corrected by the method shown in Figure V. The trap motor control signal S.

?発生させるようにしてもよい。? It may be made to occur.

比較回路♂夕は前述の比較回路lr弘と同じ働き紮する
回路であって、基準信号S。と周期誤差が含in−た逓
倍信号Smと?比較してモータ制御信号S。′(逓倍(
R−1:Smの周期誤差が含丑几てぃ/S)y発生させ
る回路で々)る。加算器と6はモータ制御信号S。′と
誤差信号発生回路60力・らの周期誤差データ信号Se
と’に710算して周期誤差が補正さfl、πモータ制
御信号S。r発生させるものである。
The comparison circuit ♂Y is a circuit that operates in the same manner as the above-mentioned comparison circuit ♂Hiroshi, and is a circuit that performs the same function as the reference signal S. and the multiplied signal Sm containing periodic error in? Compare the motor control signal S. ′(multiply(
R-1: This is the circuit that generates the cycle error of Sm. Adder and 6 are motor control signals S. ' and the periodic error data signal Se of the error signal generation circuit 60 and
The periodic error is corrected by calculating 710 and 'fl, π motor control signal S. r is generated.

以上詳細に説明しπように本発明によn、ば、安1II
hな低分解能のエンコーダ分用い、エンコーダの出力伯
号伊逓倍することVCよって分解能?上けるととも、に
、逓倍することにより生じる逓倍信号の周期誤差ケ予め
測定して寂さ、周期誤差?補正し罠モータの制御信号分
得るように構成しπものであり、高分解能の高価々エン
コーダ分用いることなく、安価な電気回路音用いて高$
t7 u’lにモータケ制御することができる。
As described above in detail, according to the present invention,
By using a low-resolution encoder and multiplying the encoder's output by VC, is the resolution determined by VC? Measure in advance the periodic error of the multiplied signal that occurs due to multiplication. It is configured to correct and obtain the control signal of the trap motor, and it uses an inexpensive electric circuit sound without using a high-resolution, expensive encoder.
The motor can be controlled at t7 u'l.

特ff(X発明はロータリーエンコーダの出力信号の周
期が長い低速回転モータの速度を・高梢疲に制御1−る
ことがてきる。
Features ff (X) The invention can control the speed of a low-speed rotary motor with a long output signal period from a rotary encoder to achieve high tree fatigue.

【図面の簡単な説明】[Brief explanation of the drawing]

&τ/図に本発明の一夾施態様を示すモータの速度制御
装置全体の構JiXk示すブロック図、第2図は第1図
における逓倍回路の詳細ケ示すブロック図、 第3図は逓倍信号?発生させゐ方法を説明する罠めの図
。 第グ図は逓倍信号の周期誤差を・補正1−る方法?説明
する罠めの図。 第5図は第1図における制御回路の一冥側例の詳示:u
′fr:示すブロック図。 第6図ζ1第1図における制御回路の他の実施例の詳細
′?6:尽すブロック図である。 /・・・・・・モータ 10・・・・・・0− 夕IJ−エンコータ、!0・・
・・・・逓倍回路 グO・・・・・・逓倍信号番号利足回路5θ・・・・・
・メモリ (,0・・・・・・誤差・1g号発生向路go・・・・
・制御回路 100・・・・・・駆動回路
&τ/ Fig. 2 is a block diagram showing the entire structure of a motor speed control device showing one embodiment of the present invention, Fig. 2 is a block diagram showing details of the multiplier circuit in Fig. 1, and Fig. 3 is a block diagram showing the details of the multiplier circuit in Fig. 1. A trap diagram explaining how to generate it. The figure below shows how to correct the periodic error of the multiplied signal. A diagram of a trap to explain. Figure 5 shows a detailed example of the control circuit in Figure 1: u
'fr: Block diagram shown. FIG. 6ζ1 Details of another embodiment of the control circuit in FIG. 1'? 6: This is a complete block diagram. /...Motor 10...0-Yu IJ-Encoder,! 0...
...Multiplier circuit OG...Multiplier signal number Profit circuit 5θ...
・Memory (, 0...Error ・1g generation direction path go...
・Control circuit 100...Drive circuit

Claims (1)

【特許請求の範囲】 1、■ モータの回転子の回転速度ま7cは回転位置を
検出するロータリーエンコーダと、@ 該ロータリーエ
ンコーダの出力信号を逓倍して逓倍信号全発生させる逓
倍回路と。 θ 該逓倍回路に接続さn前記逓倍信号が何番目の信号
であるかを判定する逓倍信号判定回路と。 0 予め測定さf′Lだ前記逓倍4W号間の周期誤差デ
ータを前記逓倍信号の信号着力と対応づけて記憶し罠メ
モ’Jk有し、前記逓倍信号番号判定回路の判定結果に
もとづいて、その逓倍信号番号に対応する前記周期誤差
データを前記メモリより読み出して誤差信号を出力する
誤差信号発生回路と。 ■ 前記誤差信号全入力して前記逓倍信号の周期誤差が
補正でn罠モータ制御信号を発生させる制御回路と4 Q 前記モータ制御信号により前記モータを駆動する駆
動回路とを有することを特徴とするモータの速度制御装
置。 2、前記モータ制御信号が、前記逓倍信号を前記誤差信
号に対応して遅延させて得らnる補正信号と予め定めら
nπ基準信号との差信号であることを特徴とする特許請
求の範囲第1項記載のモータの速度制御装置。 3、前記モータ制御信号が、前記逓倍信号と予め定めら
tL7(基準信号との差信号を前記誤差信号に対応して
補正した信号であること全特徴とする特許請求の範囲第
1項記載のモータの速度制御装置。
[Claims] 1. (1) A rotary encoder for detecting the rotational speed or rotational position of the rotor of the motor, and a multiplier circuit for multiplying the output signal of the rotary encoder to generate all multiplied signals. θ a multiplied signal determination circuit connected to the multiplier circuit and which determines the number of the multiplied signal; 0 has a trap memo 'Jk in which periodic error data between the multiplied 4W signals measured in advance is stored in association with the signal arrival strength of the multiplied signal, and based on the judgment result of the multiplied signal number judgment circuit, an error signal generation circuit that reads the periodic error data corresponding to the multiplied signal number from the memory and outputs an error signal; (2) A control circuit that inputs all of the error signals and generates an n-trap motor control signal by correcting the periodic error of the multiplied signal, and a drive circuit that drives the motor using the 4Q motor control signals. Motor speed control device. 2. The motor control signal is a difference signal between a correction signal obtained by delaying the multiplied signal in accordance with the error signal and a predetermined nπ reference signal. 2. The motor speed control device according to item 1. 3. The motor control signal is a signal obtained by correcting a difference signal between the multiplied signal and a predetermined reference signal tL7 (reference signal) in accordance with the error signal. Motor speed control device.
JP58108692A 1983-06-17 1983-06-17 Speed controller for motor Pending JPS602085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58108692A JPS602085A (en) 1983-06-17 1983-06-17 Speed controller for motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58108692A JPS602085A (en) 1983-06-17 1983-06-17 Speed controller for motor

Publications (1)

Publication Number Publication Date
JPS602085A true JPS602085A (en) 1985-01-08

Family

ID=14491220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58108692A Pending JPS602085A (en) 1983-06-17 1983-06-17 Speed controller for motor

Country Status (1)

Country Link
JP (1) JPS602085A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61195314U (en) * 1985-05-24 1986-12-05
JPS62217891A (en) * 1986-03-19 1987-09-25 Fuji Electric Co Ltd Control system of commutatorless motor
JPH0380696U (en) * 1989-11-30 1991-08-19
JP2003056753A (en) * 2001-08-10 2003-02-26 Sekisui Chem Co Ltd Pipe supporting structure for overhead piping

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61195314U (en) * 1985-05-24 1986-12-05
JPH023780Y2 (en) * 1985-05-24 1990-01-29
JPS62217891A (en) * 1986-03-19 1987-09-25 Fuji Electric Co Ltd Control system of commutatorless motor
JPH0380696U (en) * 1989-11-30 1991-08-19
JP2003056753A (en) * 2001-08-10 2003-02-26 Sekisui Chem Co Ltd Pipe supporting structure for overhead piping

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