JPS60204057A - Small-sized electronic apparatus with data storage function - Google Patents

Abstract

PURPOSE:To grasp clearly one cycle of data by displaying delimiter data for one cycle of data when data is displayed cyclically successively at every switch operation. CONSTITUTION:The output of an oscillator 7 is divided by a frequency dividing circuit 8 and is given to a timing signal generating circuit 9, and various fundamental timing signals are given to a ROM10, a RAM11, an instruction decoder 12, and an address control part 13. An operating part 14 operates time counting data in accordance with a microprogram from the ROM11 and stores the result in the RAM11, and data from the RAM11 is converted to display data by a decoder 15 and is displayed on a display part 2. When data is displayed cyclically successively at every switch operation in an input part 16, delimiter data is displayed in the display mode different from the data display mode if data is circulated once.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a small electronic device with a data storage function in which data such as a telephone number is preset, and the data is read out and displayed as necessary. Regarding.

[Prior art]

2. Description of the Related Art Conventionally, small electronic devices with a data storage function have been developed which store a plurality of data in a memory and read out and display the data as needed.

Therefore, in the conventional device described above, when reading data from memory, all data areas are accessed and the address is displayed in a loop as, for example, 0.1, . . . , n10.1, . , or only the area where data has been entered, for example 0.
1.2, . . . , 10.0.1, . . . are displayed in a loop.

[Problems with conventional technology]

In the former case of data display using the conventional device described above, the larger the memory capacity, the longer it takes to display the data.
Furthermore, when there are many areas in which no data is written, there is a problem in that wasted time increases significantly.

On the other hand, in the latter case, since only the area where data has been written is looked at, there is a problem in that it is impossible to know when the data has completed its cycle.

[Purpose of the invention]

To provide a small electronic device with a data storage function that allows only valid data to be efficiently displayed and one cycle of data to be clearly understood.

[Key points of the invention]

When data is displayed cyclically in sequence for each switch operation, delimited data is displayed after the data has gone through one cycle.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to an electronic wristwatch will be described with reference to the drawings. FIG. 1 shows the external appearance of an electronic wristwatch. A display section 2 is provided in the center of the upper surface of the case 1, and pushbutton switches SA (+ direction search) and 5B (one-way search) are provided at the bottom for searching data such as the Denhiyoshi number preset in the memory. ) is provided.

In addition, on the right side of case 1, there is a switch for setting data such as telephone numbers, etc. There is a switch for displaying the number of used data storage units of the SL1 memory (one line corresponds to one page as described later) and the maximum number of pages. A switch S1 is provided, and a switch S2 for specifying a data read mode and a data write mode, and a switch S for specifying a clock mode and a memory mode are provided on the left side. Inside the case 1, L81 parts, batteries, etc. are arranged.

FIG. 2 shows the configuration of the display section 2. This display section 2 is composed of a liquid crystal display device, and in the figure, 3 is 6 digits, and each digit is 5×
There is a character display section consisting of a 5-dot display, a numeric display section 4 consisting of a sun-shaped segment, 5 a colon display section, and 6 a PM display section. The numeric display section 4 displays the time, date, telephone number, etc., and the colon display section 4 blinks at one-second intervals in the clock mode, and the PM display section 6 blinks in the afternoon time zone in the clock mode. It will be lit.

FIG. 3 shows the entire circuit. The reference frequency signal outputted from the oscillator 7 is frequency-divided by a frequency dividing circuit 8 and given to a timing signal generating circuit 9. The various basic timing signals created there are stored in ROM (ReF'Only Me%).
! j)10. RAM (random access memory) 11,
The signal is given to the instruction decoder 12 and address control section 13, and drives each of them.

The ROM 10 stores microprograms that control all operations of this electronic wristwatch, and each microprogram is read out from the area designated by the address control section 13 and executed. The operation code of the microprogram to be read out is input to the instruction decoder 12 from the terminal OP, and the data is input to the data bus from the terminal DO to the RAMI.
input to the address input terminal A d cl r of I, the address control section 13, and the input terminal DI2 of the calculation section 14, respectively;
Furthermore, the next address data is input to the address control section 13.

The instruction decoder 12 decodes the operation code and provides a read/write control signal to the RAM II, and also provides a calculation command to the calculation section 14.

In addition, the terminals DI, , DI of the calculation unit 14 have the RAM 11
The data read from the terminal DO is input, and the calculation is executed according to the calculation command at that time.

The calculation result data is then sent to the terminal DI of RAMII and written therein. Further, the arithmetic unit 14 outputs a signal of 32 Hz every 1/32 seconds and supplies it to the address control unit 13.

At this time, the timekeeping clock from the frequency dividing circuit 8 is also input to the address control unit 13, and the address control unit 13 responds to this by addressing the address for reading out the program for the timekeeping process fp-, which is executed once every 1732 seconds. Give data to ROM10,
Therefore, the calculation unit 14 executes calculation to obtain new time measurement data in response to this, and the resulting data is stored in the RAM II.
Store it in

The data read from the AMII is also input to the decoder 15, converted to display data, and displayed on the display section 2. Further, the input section 16 is connected to the switch S 1% S AN
SBN refers to Ss, S2, and ss, and input data from these switches is sent to the data bus and RAMII
written to.

FIG. 4 is a diagram of the structure of RAM II. As shown, TN DSMs LSns Ns P% 8%Fs
It has at least n registers and data storage registers for 50 pages 1 to 50. Each register of the TID stores time data or date data in the clock mode. N register is 1 in clock mode
"," is a flag register that is set to 10 in memory mode. The n register is a flag register that is set to IIO'' in read mode and 1'' in write mode.

The n register is a register that stores the number of pages containing data (number of registers), the N register is a register where the maximum number of pages is set, the P register is a register where the number of display pages is set, and the S register is a register where the number of display pages is set. FI9, the register where the top page of the page is set.
The IC register is an editing flag register. and 1
~50 data alphabets (letters) and 12 digits of numbers can be set.

Next, the operation of the above embodiment will be explained with reference to FIGS. 5 to 9. First, the overall operation will be explained with reference to the general 70- in FIG. 5 and the state transition diagram in FIG. When the arithmetic unit 14 outputs a signal of 32 Hz and supplies it to the address control unit 13, the address control unit 13 reads the timekeeping processing program from the ROM10 and causes the arithmetic unit 14 to execute the timekeeping operation 3t (step Gt). In that case, Tl of RAMII
Read the previous time data and date data from each register of D, add a predetermined value to it, and read the new data again to T.
, D.

When the time counting process is completed, it is determined whether the switch s3 for changing the poetic language mode or the memory mode has been operated (step G3); if it has not been operated, the process proceeds to step G
6 and determines whether the data in the N register is "0" or not. If the value is 0'', the display process in step G is executed while the clock mode is being set, and the eighth
As shown by A in the figure, the data in the T and D registers are sent to the display section 2 to display the time and date. Next, it is determined whether or not there is a predetermined interrupt process (step Gs), and if there is, it is executed; if not, it waits until the next execution of this general 70 process.

On the other hand, when it is determined in step G that the switch S has been operated, the process proceeds to step G, where it is determined whether the data in the N register is 1''.

If it is 1'', the process proceeds to step G4 even though the memory mode is currently set, and sets the flag ``0'' in the N register to set the clock mode.On the other hand, if it is not 1'', the process proceeds to step G even though the watch mode is currently active.

The program proceeds to step G6 and sets the memory mode by setting 1'' in the N register.Then, if the display processing proceeds to step G7 via step G6, as shown in FIG. By pressing switch S3, the mode is reversed and B's memory mode is displayed, and the phone number is displayed.If B's phone number had been displayed until then, A's clock is changed by pressing switch S3. The display switches to the mode display.

If the data in the N register is not IIO" in step G6, that is, if the memory mode has been set, the process proceeds to step G9, where it is determined whether the switch s2 for switching between the write mode and the read mode has been operated. And if it is not operated, step GI4
Jumps to , it is determined whether the n register is '0' or not,
If it is '0', the read mode is being set, and step G
1. Proceed to edit flag register Fs]! , is 0'' or not, and if it is 0'', read processing (step G
After executing 1a), proceed to step G8. On the other hand, l 01
If it is not 1, after executing the write process (step G1.),
Proceed to step G8.

On the other hand, if the data in the n register is not 0" in step Gt4, it means that the write mode is being set, so the process immediately proceeds to step G17 and executes it. Next, as shown in FIGS. 6 and 9, steps G and 7 The operation of write processing will be explained.When writing data, first operate switch sA or switch sB to write data into RAM.
The data "51" obtained by adding 1 to the data "50" in the data storage registers 1 to 5o of I1 in the positive or negative direction is set.

Next, RAM II is addressed by the data in the P register containing the current display page number (step Wz). Then, it is determined whether or not the key is powered by hand (step W), and if the switch SA or SB is operated, step W is executed.

It is determined whether it is the switch SL or not, and now "
Since the answer is "NO", the process advances to step W2I, where it is determined whether it is the switch SA or not. If the switch SA is now being operated, the process proceeds to step W, 2, where the P register is incremented by 1.
The register is advanced one page. And step W2
．． The data "50" in the N register and the data in the P register are compared, and if N≧P, the process returns to step Wz; on the other hand, if N(P), the current displayed page has exceeded the 50th page. The process then proceeds to step W8, where "1" is set in the P register, the display page is returned to the first page, and then the process returns to step W2.

On the other hand, when the switch SB is operated, the process proceeds from step W21 to step W25, where it is determined whether the switch SB has been operated, and then, at step W26, the P register is incremented by -1 and returned by one page.

Then, it is determined whether the data in the P register has become "0", that is, whether the 0th page has been reached (step W
u), if the page is not the 0th page, the process returns to step W2; on the other hand, if the page is the 0th page, the data "50" of the N register is set in the P register, and the 50th page is set. Then, return to step W.

Then, by operating switch SA or SB as described above, +
The data written in the page corresponding to the data in the P register which is set to 1 or -1 is read out from the register and displayed on the display unit 2. When the display section 2 shows that no data (telephone number) is written in the current page of the P register as shown in FIG. 9A by repeatedly operating the switch SA or SB, the switch Stop SA or SB operation. As a result, 3 in Figure 9
As shown in FIG. 3, first, a cursor is displayed at the first digit of the character display section 3. So switch S.

When you operate , the alphabet r4J is automatically displayed in the first digit. In this case, step Ws
, W4, and W2g, the operation of the switch S1 is determined, and then step W2. Through the process, the character rAJ is displayed, and the process returns to step W.

To input a telephone number using a hand drum, set the last name and abbreviation within six characters in the character display section 3, and set the actual telephone number in the number display section 4. But now, my last name is rsUZUKIJ
, Vjvi sets r0123-45-7890J, switch S1 is operated successively until the first letter "S" is displayed according to the alphabet. Then, as shown in FIG. 9C, when the character r8J is displayed, the switch SL is operated to input that character.

At this time, the operation of the switch SL is determined in step W4, and then in step W, the data in the S register and the P register are compared. When 8>P, the data of the current display page of the P register is set to the S register (step W6), the data "S" is transferred to the register of the current page of the AMII (step W7), and the As shown in D in the figure, the display cursor is moved to the next second digit (step W8), and the data "S"
is stored in the register of the current page (step W
e) o Then return to step W3.

The input of other characters r v Z U K I J is done in exactly the same way, and is performed by operating the switches St and SL. Then, as shown at E in FIG. 9, the last character rIJ appears, and when it is memorized by switch S, F in FIG.
As shown in , the cursor moves to the first digit on the upper side of the number display section 4, and thereafter, each time the switch SX is operated, the numbers are displayed in the order of 0.1, ..., 9, so the desired number is displayed. When a number is displayed, operate switch SL to store it in the register of the current page. Therefore, G, H,
I indicates the process. When data input for one page is completed, the next page is designated by switch SA or SB, and the next data is stored in the same manner by switches S3 and SL.

After inputting the required number of data into the data storage registers 1 to 50 of RAMI 1 as described above,
There is no need to operate any keys, so go to step W.

From step W,. The process proceeds to step WI2, and it is determined whether the 7-lag FSIIi for editing is '1''. Since the write process is currently being executed, it has been set to 1'' first, and the process proceeds to step WI2, where the S register is set. A comparison is made between the data and the data "50" in the N register. In this case, if a data input operation has been performed, the relationship S≦N is established and the editing work begins in step wet. However, if no data input operation has been performed, the processing in step W1 starts with S
)N, and this write process ends.

In the editing work in step W12, an alphabetical arrangement is performed for six character data in the data in each of the 1 to 50 data storage registers. After that work is completed, step W1. The editing flag PSE force is set to 10'', and then step W
By repeating processing from 14 to W2 degrees, the actual number of data in RAMI l, that is, the number of used registers n from 1 to 50.
is calculated.

That is, first, data "0" is set in the n register and data [J is set in the P register by steps W1 and Wo.

Then, the P-th page of RAMII, that is, the first page, is specified (step W16) 1 It is determined whether there is data there (step W+y) o If there is data, the n register is incremented by 1, and on the other hand, If not, the process proceeds to steps W and D without being incremented by +1. Then, it is determined whether the data in the P register is equal to the data "50" in the N register, that is, whether the search for the presence or absence of data has been performed up to the 50th page. Step W,
. Then, the P register is incremented by 1, and the next hesi is specified. 'In this way, steps WI6 to W. 50
The process is repeated several times until the number n of registers used is reached, and when N=P, the process ends.

Next, with reference to FIGS. 7 and 10, the step 01
The read processing of step 6 will be explained. In this case, when the data in the registers 1 to 50 are to be sequentially read and displayed, the switch SA or SB is operated, and when the number of used registers is to be displayed, the switch SI is kept pressed.

For example, if you operate switch SA now, step R1
The operation is determined and the process proceeds to step R3, where it is determined whether the data of the n register (the number of registers in which data is written) is not "0", and if n=r
If the result is ``o'', no data is stored in any of the data storage registers 1 to 50, and the process proceeds to step R, where the data of the current page is displayed. In this case, since no data has been written to this page, delimited data indicating no data is displayed as shown in D in FIG. 10.

On the other hand, if n is 0, the process proceeds to step R8, where the P register and the n register are compared. If p<n, proceed to step R8, advance the currently displayed page to the next page,
The data of that page is displayed (step R1). If P=n, proceed to step R4 and check whether the data in the n register is equal to the data "50" in the N register, that is, whether data has been written to all registers 1 to 50. Then, when there is an empty page (r'
NOJ), proceed to step R6, return the current display to the first page, and display the data (step R,)
. Also, when data has been written to all pages (r
YE8J), the process advances to step R3, specifies the next page, and displays the data (step R1). Furthermore, P>n
When , the process advances to step R6, returns to the first page, and displays the data (step 几,).

In this way, each time switch SA is operated, the necessary steps L to R7 are executed based on the relationship between the currently displayed page and the number of n registers used, and the next page is sequentially designated. The data will then be displayed. Figure 10 A-)B-+04D4A→
... shows this situation. For example, suppose that data has been written to registers 1 to 20 of registers 1 to 50, and when this read process is started, page 3 of the P register is If it is a page, first, 3
The data on page 1 is displayed, and then each time the switch SA is operated once, each data on page 4, 5, 6, ..., 19, and 20 is displayed, and then 21 where no data is written. When the page reaches the page, the delimited data with no data shown in D in Figure 10 is displayed, and then the page is returned to the first page and each data of pages 1, 2, 3, 4, ..., 20 is displayed, and then The process of returning to the first page from the display of delimited data with no data on the 21st page is repeated.

Since the switch SB is a switch that addresses the RAM 11 in the negative direction, contrary to the switch SA, each process in steps 8 to 4 is self-explanatory, so a description thereof will be omitted.

Next, when you want to know the number of registers used, press the switch S, and for the duration of the press, for example, 27150 is displayed as shown in 1 in FIG. 10. In this case, "27" indicates the number of registers used, and "50" indicates the maximum number of pages.

That is, when the switch S1 is pressed, the process proceeds to step R1s via steps 1 and R, and the pressing operation is determined. Then, the number display process (step 6) as shown in E of FIG. 10 is performed.

Although the number of used pages is displayed in the above embodiment, the number of remaining pages may be displayed.

Furthermore, when data is sequentially read out each time a switch is operated, in the above embodiment, when the last data of the data written in alphabetical order in the data storage registers 1 to 50 is read out and displayed, the next register is read out. The delimited data is displayed to show that no data has been written, but in addition to this, for example, data is currently stored in registers 1 to 10, and when switching to memory mode, the data in register 5 is displayed first. Assuming that, every time the switch is operated, 5→
The delimited data may be displayed as follows: 6 → 7 → 8 → 9 → 10 → 1 → 2 → 3 → 4 → delimited data → 5 → 6 → . Furthermore, it goes without saying that the arrangement order performed when editing data is not limited to alphabetical order.

Further, the present invention is applicable not only to electronic wristwatches but also to any small electronic device having a memory.

〔Effect of the invention〕

As explained above, this invention is a small electronic device with a data storage function that displays delimited data when data is displayed cyclically in sequence for each switch operation, so it is effective. It has the advantage that only the data is displayed without wastage, it is possible to clearly see that the data has gone through a cycle, and it is also possible to know whether there is an empty area.

[Brief explanation of drawings]

Fig. 1 is an external view of an electronic wristwatch according to an embodiment of the present invention, Fig. 2 is a block diagram of the display section 2, Fig. 3 is a circuit block diagram, Fig. 4 is a block diagram of RAMII, and Fig. 5 is a general diagram. FIG. 6 is a diagram showing the write processing flow, FIG. 7 is a diagram showing the read processing flow, FIG. 8 is a diagram showing the transition between clock mode and memory mode, and FIG. 9 is a diagram showing the write mode. FIG. 10 is a diagram showing the state transition of the read mode. 2...Display section, 3...Character display section, 4
...Numeric display section, 7...Oscillator, 8.
...Frequency divider circuit, 9...Timing signal generation circuit, 10...ROM, 11...R
AM, 12...Instruction decoder, 13...
・Address control section, 14... Arithmetic section, 15...
...Decoder, 16...Input section, Sl, S
2.S8.5A1SB1SL...Switch. Patent Applicant: Casio Computer Co., Ltd. Figure 1, Figure 2, Figure 2, Figure 8, Figure 9, Figure 10, Procedural Amendment (Voluntary) September 20, 1980, Manabu Shiga, Commissioner of the Patent Office, 1, Indication of the Case Patent Application No. 58339 of 1983 2, Name of the invention, Small electronic device with data storage function 3, Relationship to the amended case Patent IB applicant address: 2-6-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Name: (
144) Casio Computer Co., Ltd. Representative: Toshio Kashio 4, Agent address: 8 Iwatsuki Building, 6-7-16 Ginza, Chuo-ku, Tokyo
1iF'"'...1,) Name Patent Attorney (6548) Hajime Yamada 7-5, Subject of amendment 6, Contents of amendment (1) On page 5, line 10 of the specification attached to the application, "...・・・
...Also, data" should be corrected to read, "Also numerical data and address data." (2) Similarly, on page 6 of the specification, lines 3 to 6, “・
. . . Also, the calculation section 14 inputs 1/32 . The address of the ROM 10 can be changed based on the calculation result of the calculation unit 14. Also, frequency dividing circuit 8
The 32Hz clock clock output from the address controller 13 is also input to the address control unit 13, and so on. (3) Similarly, on page 18 of the specification, lines 7 to 11, there is a line that says ``...and an empty page......(rYIi
8J), steps R and J are written as "And when data has been written to all pages ("YESj"), proceed to step R6, return the current display to the first page, and display that data. (Step R?). Also, if there is an empty page, correct it as (rNOJ L step island). (4) Correct figures 3 and 7 of the drawings as shown in the attached sheet.

Claims (1)

[Claims] It has multiple data storage units each storing data consisting of multiple characters, and by operating a single operation switch, the data display mode that displays the data in each different data storage unit can be cyclically switched and displayed. A small electronic device with a data storage function comprising a display control means for displaying a display mode different from the data display mode while the plurality of data display modes are cycled through by operation of the single operation switch. A small electronic device with a data storage function.