JPS6020399A - Testing method of semiconductor storage element - Google Patents

Testing method of semiconductor storage element

Info

Publication number
JPS6020399A
JPS6020399A JP58129002A JP12900283A JPS6020399A JP S6020399 A JPS6020399 A JP S6020399A JP 58129002 A JP58129002 A JP 58129002A JP 12900283 A JP12900283 A JP 12900283A JP S6020399 A JPS6020399 A JP S6020399A
Authority
JP
Japan
Prior art keywords
time
check
storage element
bits
checking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58129002A
Other languages
Japanese (ja)
Inventor
Shinichi Kunieda
国枝　伸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58129002A priority Critical patent/JPS6020399A/en
Publication of JPS6020399A publication Critical patent/JPS6020399A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE:To shorten a check time by checking a characteristic by the group of a divided storage element. CONSTITUTION:The storage elements for M bits are divided into N groups for M/N bits, and the storage elements are accessed in every group with a test pattern signal to make a check on the characteristics, so that the time T required for the check satisfies an equation. Therefore, the time T is shortened to 1/N comparing to the case when a test pattern for the storage elements for M bits is used to attain the shortening of the check time. In the equation, (k) is a constant.

Description

【発明の詳細な説明】 本発明は半導体記憶素子のテスト方法に関する。[Detailed description of the invention] The present invention relates to a method for testing semiconductor memory devices.

最近半導体ＲＡＭ　（ｌ（、ａｎｄｏｗ　Ａｃｃｅｓｓ
　Ｍｅｍｏｒｙ）の記憶容量の増加は極めていちぢるし
く、現在主流である６４ｋｂｉｔから２５５ｋｂｉｔあ
るいはＩＭｂｉｔへと急増するの１時間の問題である。Recently, semiconductor RAM (l(, andow Access
The increase in the storage capacity of memory (memory) is extremely difficult, and it is only a matter of an hour before it rapidly increases from the currently mainstream 64kbit to 255kbit or IMbit.

その際、半導体ＲＡＭＰ製造する上での一つの大きな問
題点として、製品の電気的特性のチェックに要する時間
の問題がクローズアップさねでくる。一般に、この電気
的特性のチェックに要する時間は、記憶容量のベキ乗に
比例するので、従来と同じやり方でチェックしていたの
では、その設備の面でもあるいは時間の面でも、非現実
的な、ものになってしまう。At this time, one of the major problems in manufacturing semiconductor RAMPs is the time required to check the electrical characteristics of the product. Generally, the time required to check the electrical characteristics is proportional to the power of the storage capacity, so checking in the same way as before would be unrealistic in terms of equipment and time. , it becomes a thing.

本発明の目的はこのよう逢問題点を解決する方法の提供
にある。An object of the present invention is to provide a method for solving these problems.

従来、半導体ＲＡＭの電気的特性をチェックするにあた
り、テストパターンと呼ばれる一定のシーフェンスに従
った信号を、半導体ＲＡＭデバイスのアドレス入力ビン
に印加し、半導体几ＡＭＰ構成している全記憶要素をア
クセスする。ｌ：うにしていた。この為、いわゆるギャ
ロップと呼ｄ：れるようをテストパターンの場合、チェ
ックに要する時間Ｔは記憶容ｔＭのベキ乗に比例し Ｔ＝ｋＭ” となる。この為、１６ｈｂロ半導体ＲＡＭでは、Ｔは数
秒以下であったのが、６４ｋ　ｂｉｔでは数１０秒かか
り、２５６ｋ　ｂｉｔ　ＲＡＭやＩ　Ｍ　ｔ〕ｉ　ｔ　
１（、ＡＭでは数分から１０数分かかると予想され、量
産上重大な問題となってくる。Conventionally, when checking the electrical characteristics of a semiconductor RAM, a signal according to a certain sea fence called a test pattern is applied to the address input bin of the semiconductor RAM device, and all memory elements making up the semiconductor RAM device are accessed. do. L: I was waiting. For this reason, in the case of a so-called gallop test pattern, the time T required for checking is proportional to the power of the storage capacity tM, and becomes T=kM.For this reason, in the 16HB semiconductor RAM, T is It took several seconds or less for 64k bits, but it took several tens of seconds for 256k bits RAM and I M t]it
1 (with AM, it is expected to take from several minutes to over 10 minutes, which poses a serious problem in mass production.

そこで、本発明では、Ｔの増加を次のような方法でおさ
える事ができる４ｆ：説明する。すなわち、従来は、Ｍ
Ｌｒｉｔの全記憶要素に対してテストノくター／信号に
よりアクセスしていたが、本発明では、記憶要嬬ｔ″４
々がＭ／Ｎｂ１ｔよりなるＮ個のグループに分け、各グ
ループごとにテストパターン信号によりアクセスすると
いう方法を採用する。こうすれば、チェックに要する時
間Ｔは Ａ１ｉ＋ Ｔ＝ｋＮ（−） Ｎ ２ −に− １〜 となり、従来のチェック時間の１／Ｎ　ｉＣｈる。ここ
で問題になるのは、Ｎの値の最大値がいくつかという事
である。この最大値は、本発明の方法でやったチェック
の結果が、従来の方法の結果と一致しなくなるＮの値で
決まる。第１図に示す６４ｋ　ｂｉｔ　Ｒ，ＡＭの場合
のデータによると、Ｎ＝８までは、１００％一致しへ＝
１６になると一致しないものがでてくるので、Ｎ＝８’
ｅ用いれば、第２図に示すようにして従来の　７８のチ
ェック時間で、従来のやり方と同等のチェック結果が得
られることがわかる。Therefore, in the present invention, the increase in T can be suppressed by the following method 4f: This will be explained. That is, conventionally, M
All the memory elements of Lrit were accessed by the test node/signal, but in the present invention, the memory requirement t″4
A method is adopted in which each group is divided into N groups of M/Nb1t, and each group is accessed by a test pattern signal. In this way, the time T required for the check becomes A1i+T=kN(-)N2-1~, which is 1/NiCh of the conventional check time. The problem here is that there are several maximum values for N. This maximum value is determined by the value of N at which the result of the check performed by the method of the present invention does not match the result of the conventional method. According to the data for 64k bit R, AM shown in Figure 1, there is 100% agreement up to N=8.
When it reaches 16, there will be some discrepancies, so N=8'
As shown in FIG. 2, it can be seen that by using e, the same check results as the conventional method can be obtained in the conventional check time of 78.

このように、記憶要素をいくつかのグループにわけ、そ
のグループごとにチェックを行うという方法は、チェッ
ク時間の短縮に極めて有効な発明である事は明かでるる
。It is clear that the method of dividing storage elements into several groups and checking each group is an extremely effective invention for reducing the checking time.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例による分割数と一致率と関係を示
す図で横軸は記憶要素を等分割する分割数、縦軸は分割
してチェックした結果が分割せずにチェックした場合の
結果と一致している割合、第２図はチェックされる記憶
素子数とチェック時間との関係金示す図で横軸は記憶要
素の数、縦軸は１０２４ビツトのチェック時間を１とし
た時の相対チェック時間、又グラフのパラメーターは記
憶要素を等分割した時の分割数、である。FIG. 1 is a diagram showing the relationship between the number of divisions and the matching rate according to an embodiment of the present invention. The horizontal axis is the number of equal divisions into which a storage element is divided, and the vertical axis is the result of checking after dividing and checking without dividing. Figure 2 shows the relationship between the number of memory elements to be checked and the check time. The horizontal axis is the number of memory elements, and the vertical axis is the check time for 1024 bits when it is set to 1. The relative check time and graph parameter are the number of equal divisions of the storage element.

Claims (1)

【特許請求の範囲】[Claims] 半導体記憶素子の電気的特性で評価するにあたり、前記
半導体素子の記憶要素を複数個のグループに分割し、前
記分割された記憶素子のグループごとに、電気的特性を
評価することを特徴とする半導体記憶素子の電気的特性
評価方法。A semiconductor characterized in that when evaluating the electrical characteristics of a semiconductor memory element, the memory elements of the semiconductor element are divided into a plurality of groups, and the electrical characteristics are evaluated for each group of the divided memory elements. Method for evaluating electrical characteristics of memory elements.
JP58129002A 1983-07-15 1983-07-15 Testing method of semiconductor storage element Pending JPS6020399A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58129002A JPS6020399A (en) 1983-07-15 1983-07-15 Testing method of semiconductor storage element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58129002A JPS6020399A (en) 1983-07-15 1983-07-15 Testing method of semiconductor storage element

Publications (1)

Publication Number Publication Date
JPS6020399A true JPS6020399A (en) 1985-02-01

Family

ID=14998713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58129002A Pending JPS6020399A (en) 1983-07-15 1983-07-15 Testing method of semiconductor storage element

Country Status (1)

Country Link
JP (1) JPS6020399A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032680A (en) * 1989-05-31 1991-01-09 Fujitsu Ltd Semiconductor integrated circuit apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53120234A (en) * 1977-03-30 1978-10-20 Toshiba Corp Semiconductor memory
JPS5641599A (en) * 1979-09-12 1981-04-18 Ando Electric Co Ltd Address generation system of pattern generator
JPS57189397A (en) * 1981-05-14 1982-11-20 Toshiba Corp Semiconductor storage device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53120234A (en) * 1977-03-30 1978-10-20 Toshiba Corp Semiconductor memory
JPS5641599A (en) * 1979-09-12 1981-04-18 Ando Electric Co Ltd Address generation system of pattern generator
JPS57189397A (en) * 1981-05-14 1982-11-20 Toshiba Corp Semiconductor storage device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH032680A (en) * 1989-05-31 1991-01-09 Fujitsu Ltd Semiconductor integrated circuit apparatus

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