JPH032680A - Semiconductor integrated circuit apparatus - Google Patents

Abstract

PURPOSE:To reduce the number of external terminals required in inputting and outputting test signals and test data by providing a testing circuit within a chip to test a macrocell based on the test signals from outside. CONSTITUTION:A semiconductor integrated circuit apparatus 1 is built containing a random logic circuit 2, a single port RAM 3, external input terminals 4-9 and an external input/output terminal 10. Input data I00-I (b-1) on the side of the random logic circuit 2 divided in plurality are inputted into a selector as input from the normal mode side while external test input data TI00-TI (b-1) for the semiconductor integrated circuit apparatus 1 are inputted thereinto and these input data are selected by an MTM signal. In this manner, one macrocell (single port RAM) is divided by a number as specified and a testing of one macrocell is performed as if a plurality of macrocells exist thereby enabling limiting of the number of terminals required.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Working Examples Explanation of the Principle of the Present Invention (Figures 1 to 7) The Present Invention First embodiment of the present invention (Fig. 8) Second embodiment of the present invention
(Figure 9.10) Third embodiment of the present invention (Figure 11.12) Fourth embodiment of the present invention (Figure 13) Effects of the invention [Summary] A random logic circuit and a macro cell are included in the same chip. The purpose of the present invention is to provide a semiconductor integrated circuit device that can significantly reduce the number of test terminals without increasing the number of gates used in a mixed semiconductor integrated circuit device. In a semiconductor integrated circuit device in which a macro cell is embedded, a test circuit for testing the macro cell based on an external test signal is provided in the chip, and the test circuit tests one macro cell with a predetermined bit width.

The macrocell is divided into a plurality of macrocells, and the test is performed on the divided macrocell.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a composite semiconductor integrated circuit device in which a random logic circuit and macro cells such as RAM, ROM, and multipliers are mixed in the same chip, and in particular, it relates to a compound semiconductor integrated circuit device in which a random logic circuit and a macro cell such as a RAM, ROM, and a multiplier are mounted together on the same chip. This invention relates to improvements in macrocell test circuits that can be used to test macrocells.

With recent advances in semiconductor manufacturing technology, semiconductor integrated circuits 1
The scale of gates that can be mounted on a single chip has increased dramatically, and semiconductor integrated circuits that can mount tens of thousands to hundreds of thousands of gates are now being seen.

However, the random logic section in one chip is limited to tens of thousands of gates at most, and logic design and logic verification become extremely difficult when the scale becomes larger than this. Therefore, it has become essential to install macro cells such as RAM, ROM, multipliers, and ALUs, and macro cells with large bit widths are installed.

The testing method used in these cases has become an issue.

[Conventional technology]

Conventionally, in semiconductor integrated circuits equipped with random logic and macro cells, logic designers (users) were often asked to create test circuits and test patterns. In other words, changing the bit or word width means changing the size of the macrocell, and the test circuit for that test also differs in size, so it is common for logic designers to create the test circuit. It was a target. However, as the types and number of macrocells installed increase, the burden on logic designers becomes extremely heavy, so there is an increasing need for semiconductor vendors to conduct testing.

In order to conduct tests on the semiconductor vendor side, a circuit dedicated to testing is required, and there are two main types of methods for doing so. One method is to serially read data using scan flip-flops, and the other method is to directly control all terminals of the macrocell under test from external terminals. The former method is to incorporate a scan flip-flop serially, give a system clock externally in normal mode and input it to the scan flip-flop, then set it to scan mode, use the scan-in terminal as input, and set the scan-out terminal to the scan flip-flop. The terminal is used as an output, and a scan clock is applied as many times as there are scan flip-flops to shift the data and read it out serially.

[Problem to be solved by the invention]

However, in such conventional semiconductor integrated circuit devices, although the former method uses fewer external terminals, the number of gates used increases to utilize scan flip-flops, and the number of test patterns increases due to serial readout. There was a problem with that. For example, when the focus and word width are 46, 46 scan flip-flops are required, which greatly increases the number of logic circuits used for these flip-flops, making it unsuitable for testing RAM.

Furthermore, in the latter method, the number of gates used is small and the number of test patterns is small, but a large number of external terminals are required because the test patterns are input directly from the external terminals of the LSI to the macrocell. Therefore, RAM and ROM with a large number of bits
, multiplier, ALU, etc., the number of terminals required for testing may exceed the number of usable terminals, which is the number of terminals on the package, excluding the power supply terminals. In addition, most of the test terminals can be shared with user terminals, but if they are shared, the shared terminals will be loaded, delay time will increase, and the characteristics will be poor (and the characteristics required by the logic designer). The common terminals that can actually be used are
It decreases considerably. In the past, the bit width was relatively short, so the above-mentioned problem did not pose much of a problem.However, recently, as macro cells with extremely large focus widths have been mixed together, the number of test terminals has increased seriously. This is becoming a problem.

Therefore, the present invention provides the following advantages: without increasing the number of gates used;
It is an object of the present invention to provide a semiconductor integrated circuit device that can significantly reduce the number of test terminals.

The macrocell is divided into a plurality of macrocells having a width υ1, and a macrocell test is performed on the macrocell after the division.

Therefore, there is no need to prepare a large number of test external terminals for macrocells having a large bit width, and the number of external terminals required for inputting and outputting test signals and test data is significantly reduced.

Means for Solving Problem C] In order to achieve the above-mentioned object, the semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which a random logic circuit and a macro cell are mixedly mounted in one chip, and in which a test signal from an external source is inserted into the chip. A test circuit is provided that tests the macrocell based on the above, and the test circuit is configured to divide one macrocell into a plurality of macrocells having a predetermined bit width and to perform the test on the divided macrocell. do.

[Effect]

In the present invention, one macro cell is brought into a predetermined focus [Example] The present invention will be described below with reference to the drawings.

The present invention provides a dedicated test circuit that can divide one macrocell into arbitrary bits and test them as a plurality of macrocells, thereby making it possible to directly control the macrocell from the outside.

The macro test mode signal MTM is used as a dedicated terminal, and this signal selects between normal mode and macro cell test mode, and other signals necessary for macro cell testing are shared with external terminals used in normal mode. do. The macrocell referred to here refers to a cell with multiple bit widths and multiple functional blocks, such as RAM, ROM,
Multipliers, ALUs, etc. are shown.

1 to 7 are diagrams for explaining the basic principle of the present invention, and are examples in which a single port RAM is used as a macro cell. In FIG. 1, 1 is a random logic circuit 2
, a composite semiconductor integrated circuit (semiconductor integrated circuit device) in which a single-port RAM 3 is mounted on the same chip, and the semiconductor integrated circuit device 1 has a random logic circuit 2, a single-port RAM 3, external input terminals 4 to 9, and external input/output. Terminal 10, input buffers 11 to 13, bidirectional human output buffer 14, selector circuits 15 to 18 that select the input signal from the random logic circuit 2 and the human input signal for macro cell testing using the macro test mode signal MTM, and the bit select signal. A bus driver 19, 20 that selects which bit of the test output signal is to be output to the output data bus 23, which will be described later; a test circuit dedicated address bus 21;
It is configured to include an input data bus 22 dedicated to the test circuit and an output data bus 23 dedicated to the test circuit.

External input terminals 4 to 9 each have a RAM test mode selection signal (Macro Te5t Mode) M T
M, write enable signal in test mode (Tes
tWrite Enable) T W E , control signal (Bit
5elect) B SQ, BSI, address signal for test circuit (TestAddress) T A, input data signal for test circuit (Test Data Inp
ut) T I is input, and the test circuit output data signal (TestData 0ut) is input from the external input/output terminal IO.
put) TO is output. In addition, 31 is the input data for the random logic circuit when the test address terminal and the random logic circuit terminal are shared, and 32 is the input data for the random logic circuit when the test human data terminal and the random logic circuit terminal are shared. Input data, 3
3 is the input data for the random logic circuit when the test output data terminal and the random logic circuit terminal are shared, 34 is the write enable signal on the random logic circuit side, 35 is the address signal on the random logic circuit side, 36.37 is an input data signal on the random logic circuit side, and 38.39 is an output data signal on the random logic circuit side.

The focus width of the address bus 21 is single port R/A.
Single port RAM with the same number of addresses as M3
3. Manpower. The bit width of the human-powered data bus 22 is determined by dividing the bit width of the single port RAM 3 into one having the largest bit width. For example, if it is desired to divide a RAM with a bit width of 15 bits into two, the bit width of the input data path will be 8 bits because it can be divided into 8 bits and 7 bits. Similarly to the human-powered data bus 22, the bit width of the output data bus 23 is determined by dividing the bit width of the RAM into the largest bit width. In the case of RAM, the input data and output data have the same bit width. Note that the large power buffers 11 to 13 are a combination of inputs and inputs,
By controlling with MTM signals, any combination such as input and bidirectional is possible.

Similarly, the bidirectional human output buffer 14 can be combined with output and output, output and bidirectional, etc.

In addition, since the drawing in FIG. 1 is complicated, the buffer 12
Although only three buffers 12 to 14 are shown, in reality, the same number of buffers 12 to 14 as the number of address test input data test output data is required.

FIG. 2 is a block diagram of the single port RAM 3, and FIG. 3 is a block diagram of the single port RAM 3 with a built-in test circuit. In Figure 2.3, single port R
AM3 includes a buffer 41, an address buffer 42, an address transition detection circuit (ATD) 43, and a precharge circuit 4.
4, a row decoder 45, a column decoder 46, a sense amplifier 47, a write amplifier 48, a column select 49, and a memory cell array 50 in which memory cells are arranged in a matrix in the row and column directions with a predetermined capacity.

The buffer 41 is a write enable (t) that controls data writing and reading.
, to the write amplifier 48, and the address buffer 42 buffers the external address (A00 to A+a-+) manually entered by multiplexing the row address and column address, and the external address is output to the address transition detection circuit. 43, and is output to the row decoder 45 and column decoder 46. The address transition detection circuit 43 receives external data sent from the address buffer 42.

The transition state is detected based on the address and transmitted to the precharge circuit 44 and sense amplifier 47. Precharge circuit 44 precharges the data line of memory cell array 50 according to this detection result. Row decoder 45 decodes the transmitted external address or internal address, and selects and activates one of the many word lines of memory cell array 50 according to the decode result. Column decoder 46 decodes the transmitted external address and outputs it to column select 49. The write amplifier 48 receives external data (I OO = I <-
1, ), and outputs this data to column select 49, and selects one of the many bit lines of memory cell array 50 according to the decoding result from column decoder 46. The sense amplifier 47 amplifies the potential of the bit line selected via the column select 49 and reads out the data (DOO to D!Il+-11) of the memory cell connected to this bit line.

Inside of the single port RAM 3 shown in FIG.

The configuration itself is the same as the conventional one, but in addition to the signals from the random logic circuit 2, the single port RAM 3 is different from the conventional one in that signals are input and output from the external terminal via the test-dedicated circuit. It is different from That is,
As shown in FIG. 3, the write enable signal WE on the random logic circuit 2 side and the write enable signal TWE in the test mode are input to the selector 51, selected by the test mode selection signal MTM, and output to the buffer 41. The selector 52 receives an external address 800~ from the random logic circuit 2 as an input from the normal mode side.
A (a-11) is input manually, and these addresses are selected by the MTM signal.The selector 53 also receives random logic 1. Input data 100 on the circuit 2 side
I (b-1 is input, and the semiconductor integrated circuit device 1 external test manual data T!, ...T I <b-1
, and these input data are selected by the MTM signal. On the other hand, the data of the memory cell array 50 is outputted to the outside of the single boat RAM 3 via the column select 49 and the sense amplifier 47 as outputs DOO to DII to the user side, and
The bus driver 54 outputs data of a predetermined bit to the outside as test output data TDOO to TD (11-11) in accordance with the bit select signal BS.

In this case, a selector may be used instead of the bus driver 54. The selector 51, selector 52, selector 53, and bus driver 54 are the selector circuit 18, selector circuit 17, and selector circuit 15.1 shown in FIG.
6 and bus drivers 19 and 20, respectively, and these constitute a test circuit as a whole.

4-7 are timing charts of the principle explanatory diagram shown in FIG. 1, and FIGS. 5-7 are detailed timing charts of FIG. 4. In FIG. 4, when the macro test mode selection signal MTM is set to "L", the test mode is entered, and when the write enable signal TWE during testing is set to "L"', writing becomes possible. As shown in FIG. 4(d), when a certain address (TAO0~TAt-n) is selected, the test data (TTo.~TIfn-1) is selected.
1 is written to the single boat RAM 3 (see Figure 4 (C
), the write enable signal TWB is activated in the next cycle.
When set to "H" to enter the successive state, the data written here (TDOO to TDLm-11) or (T D m -TDfi-+) is output. Specifically, in the cycle ■, the data of "'I 1" is written to the address of "'AI", and in the cycle of ■, the data of the address of "A1" is written as TD OT D.
(Read data from the m-11 terminal. In the cycle (■), write the data of "I2" to the address of "A2", and in the cycle of (■) write the data of the address of "A2" from TDO to T D (n-+ , reads data from the terminal. In cycles from ■ to ■, TDO to T D (m-1)
A terminal is selected, and data is read from m test output data terminals. At this time, T D m−T D <
The output of n −+ + is invalid (that is, it is in the Z (high impedance) state).

In the cycles from ■ to ■, the address and input data are the same, but the output terminal is T D m - T D tn -1
> is selected, and data is read from (n−m) test output data terminals. At this time, TD, ~
The output of TD, , is invalid.

5-7 are detailed timing diagrams of FIG. 4. The read mode of the macro test mode represents the timing of ■■■■ in Figure 5, and its write mode represents the timing of ■■■■ in Figure 6.
represents the timing of Set the macro test mode terminal to “’H”
When set to °', the mode becomes normal mode (user mode) as shown in FIG.

As described above, the present invention divides one macrocell (single port RAM 3 in FIG. 1) into a predetermined number of bits, and divides one macrocell into a predetermined number of bits, so that one macrocell functions as if there were a plurality of macrocells. I'm trying to test it. Therefore, the number of terminals required for testing can be limited, and especially when the focus width is multi-divided, the number of external terminals required for testing can be significantly reduced.

Examples will be described below based on the above basic principle. 8th
The figure shows a first embodiment of a semiconductor integrated circuit device according to the present invention, and this embodiment is an example applied to a semiconductor integrated circuit device equipped with two single-board RAMs as macro cells. In explaining this embodiment, the same components as those in the principle explanatory diagrams shown in FIGS. 1 to 3 are given the same numbers and symbols.

In FIG. 8, 61 is a 4 word x 4 bit single port RAM, 62 is a 4 word x 8 bit single port RAM, and the single port RAMs 61 and 62 are connected to a random logic circuit (not shown). In order to make the connection state of the test circuit easier to understand, the connections connected to the random logic circuit (not shown) are omitted, but the connections are made in the same manner as in the principle explanatory diagram shown in FIG. 4.5 and 63-69 are external input terminals, 70.7
1 is an external output terminal, the external input terminal 4 receives the test mode selection signal MTM, the external input terminal 5 receives the write enable signal TWE in the test mode, and the external input terminal 6 receives the test mode selection signal MTM.
3.64 is the test circuit address signal TA.

0 to TAI are manually input, and each signal MT
MSTWE, TAO1TAI is single boat RAM
61 and 62 in parallel. On the other hand, external input terminal 6
5.66 is the test circuit input data signal T10. T.I.
I is input, and TIO and Tll are connected in parallel to each bit to be divided and to each RAM 61 and 62. Further, the selection signal MS of the macrocell under test for selecting the RAM 61.62 is input to the external input terminal 67, and the external input terminal 68
．． A control signal B501BSI for performing a bit division test in the test mode is input to 69, respectively. MS and BSO select the test output signal TDO-TD3 of a predetermined bit of the RAM 61 (single baud) via the decoder 72 with an enable terminal.
4, and the bus drivers 73 and 74 receive the test input data signal T10-T divided into bits and input.
Test output signal TDO output in a format corresponding to I3
-Select TD3. The truth table of the decoder with enable terminal 72 is shown in Table 1.

Similarly to Table 1, the selection signal MS and control signal B501BSI of the macrocell under test inputted via the inverter 75 are sent to the test output signal TDO of a predetermined bit of the single boat RAM 62 via the decoder 76 with an enable terminal.
The test output signal T is outputted to the bus drivers 77 to 80 that select TD7, and the test output signal T is output in a form corresponding to the input test input data signals TTO to TI7, which are divided into bits and input. -Select Do to TD3.

The truth table of the decoder with enable terminal 76 is shown in Table 2.

The test was conducted assuming that there were six RAMs of Table 2 words x 2 bits.

In the configuration shown in Table 3 and above, the composite semiconductor integrated circuit 1 of this embodiment is equipped with two single-board RAMs 61 and 62, and the single-board RAM 61 is divided into 2 pieces of 4 words x 4 bits (single board). 4 words of RAM62
8 bits are divided into 4 parts. Therefore, in the single port RAM 61, the RAM is divided into two, inputs are input into each two (2 bits), and outputs are paired into two (2 bits) each and controlled by bit selects BSO and BSI.

In addition, in the single baud) RAM 62, the RAM is divided into four parts, inputs are input in parallel two by two, and outputs are paired two by two and controlled by the B501BSI.

In this way, in this embodiment, the signal of MS, B501BS1 is used as shown in the truth table of Table 3. Therefore, in the conventional test circuit, a plurality of macro cells are installed, and the bit width is When a very large macrocell exists, the number of external terminals for testing on the entire chip is determined by the number of terminals required for this macrocell, but according to this embodiment, when testing a macrocell, it is possible to Since it can be divided into an arbitrary number of bit widths, it is possible to reduce the number of external test terminals for the entire chip by dividing only large macrocells by bit width. Even if there are multiple macrocells of various types, the number of external terminals for testing the entire chip is limited.

It does not increase much. In this embodiment, by dividing the 8-bit single port RAM 62 into four parts, the number of external terminals required for inputting and outputting test data can be reduced to two, compared to eight in the conventional example. In reality, a macro cell may be equipped with a RAM other than 8 bits, for example, 32 bits, and in such cases, conventionally, even if a macro select function was added and external terminals were shared, the final result was an external 32-bit RAM. However, in this embodiment, the larger the bit width of the RAM, the more remarkable the effect becomes.

In this embodiment, the bus driver 54 is used, but a selector may also be used, and the decoder 72.7
6 may be omitted, and focus select signals corresponding to the number of divisions may be provided externally to directly control them. Further, although there are two bit select signals, in order to divide the signal into four or more, the number of bit select signals may be increased to three or four. Furthermore, if the number of divisions is large, the number of BS signals may be increased and the bus driver may be decoded by a decoder.

Figure 9.10 shows the second part of the semiconductor integrated circuit device according to the present invention.
FIG. 2 is a diagram showing an embodiment, and this embodiment is an example in which two single-board RAMs and ROMs are mounted as macro cells. Components that are the same as those in the principle explanatory diagrams shown in FIGS. 1 to 3 and the first embodiment shown in FIG. 8 are given the same reference numerals.

In Fig. 9, 61 is a 4 word x 4 bit single baud RAM, 81 is a 4 word x 8 bit ROM, the single baud RAM 61 is 4 words x 4 bits divided into two, and the ROMS1 is 4 words x 8 bits. The bit is divided into four parts. Figure 1O shows ROMS1 with a built-in test circuit.
In this figure, an address buffer 82, an address transition detection circuit (ATD) 83, a row decoder 84, a column decoder 85, and a memory cell array in which memory cells are arranged in a matrix in the row and column directions with a predetermined capacity are shown. 86, column select 87 and sense amplifier 88
The internal structure of the ROM 81 itself is the same as that of the conventional one, so a description thereof will be omitted.

Macro cell test mode signal MTM, test.

In the mode, the write enable signal TWE and the test circuit input address signal TAO1TAI are connected in parallel to the single port RAM61 and ROMS1, and the test circuit input data Tl01TII is connected in parallel to each via of the single port RAM61 to be divided. . In addition, the control signal B501BSI and the selection signal MS of the macrocell under test are used when performing a bit division test in the test mode.
selects the outputs of the macro cells of the single port RAM 61 and ROM 81 via decoders 72 and 76 with enable terminals. The truth table for the circuit of FIG. 9 is shown in Table 4.

(Next summer, blank space below) Table 4 Therefore, in this example, it is assumed that there are two 4-word x 2-bit RAMs and four 4-word x 2-bit ROMs depending on the MS, BSO, and BSl signals. The test can be carried out using the same method, and the same effects as in the first embodiment can be obtained.

FIGS. 11 and 12 are diagrams showing a third embodiment of the semiconductor integrated circuit device according to the present invention, and this embodiment is an example in which two macro cells, a single port RAM and a multiplier, are mounted. Components that are the same as those in the principle explanatory diagrams shown in FIGS. 1 to 3 and the first embodiment shown in FIG. 8 are given the same reference numerals.

In FIG. 11, 61 is a 4-word x 4-pin single port RAM, 91 is a 4-word x 4-bit multiplier, the single-port RAM MS1 divides 4 words x 4 bits into two, and the multiplier 91 is a 4-word x 4-bit multiplier. FIG. 10 is a block diagram of the multiplier 91, in which the word x 4 bits is divided into four.
In this figure, the multiplier 91 has multiplier data AOO to Af
t-11 and test circuit multiplier data TAOO~TA
a selector 92 which receives input data and selects these input data according to MTM, a multiple buffer 93 which buffers the input data selected by the selector 92, and multiplicand data B OO=B (fi-11
and test circuit multiplicand data TBOO-TB-I
, is input and selects these input data according to MTM, a Booth decoder 95, a multiple array 96, and an adder circuit 97. The multiplication result from the multiplier 91 is outputted to the user side DOO~D. (
It is output to the outside as L, and is also output to the bus driver 54.
The bus driver 54 outputs the test output data T D 0 to the test output data T D 0 according to the MS and BS.
0 = T D (outputted to the outside as L-11).

Returning to FIG. 11, 101 to 104 are clocks TCK1
~External input terminal where TCK4 is input, 105-108
is the test input data Tl01TII as the clock TCK
Launch in synchronization with 1~TCK4, multiplier TAO~TA3
, is a latch circuit that outputs multiplicands TBO to TB3 to the multiplier 91. Multiplier 91 differs from memory cells in that a circuit such as a launch or flip-flop is added before the input data is input to test clock signals TCK1 to TCK4.
need to be controlled.

Macro cell test mode signal MTM and test circuit input data signals Tl0-TII are input to single port RAM6.
1 and multiplier 91 in parallel, Tl01T■1
are connected in parallel for each pin of the single port RAM MS1 that is further divided. Furthermore, the write enable signal TWE and test circuit manual data signals TAO and TAI in the test mode are connected only to the single port RAM 61.

MS and BSO are outputted via a decoder 72 with an enable terminal to a bus driver 73 that selects test output signals TDO to TD3 of predetermined bits of the single port RAM MS1, and then via an impark 75.

The selection signal MS and control signal B501BSI of the macrocell under test are input to the decoder 1 with an enable terminal.
Bus drivers 77 to 8 select test output signals TDO to TD7 of predetermined bits of the multiplier 91 via bus drivers 77 to 8
Output to 0. The truth table for the circuit of FIG. 11 is shown in Table 5.

Table 5 Accordingly, in this embodiment, the test can be performed assuming that there are two 4-word x 2-bit RAMs and four 2-bit output multipliers based on the signals of the MS and B501BS1. In the case of an ALU, the number of terminals can be reduced and tests can be performed by connecting the ALU in the same way as the multiplier.

In each of the above embodiments, the number of macro cells is two, but of course the number is not limited to this, and for example, the number of macro cells shown in FIG.
As shown in the embodiment, the number of macro cells may be two or more by increasing the number of macro select signals. Figure 13 shows a single port RAM III with a built-in test circuit, a ROM 112 with a built-in test circuit, and a multiplier 1 with a built-in test circuit.
13, test input data Tl0-Tl3 and test input addresses TAO-TA2 are connected to test output data TD.
This is to obtain O1TDI. However, the address terminal of the macro cell is connected in parallel to the terminal of each macro cell, and when there is no definition of the address terminal in the macro (multiplier, ALU, etc.)
is not connected.

Further, in each of the above embodiments, the focus width is 2 bits, but it goes without saying that the bit width may be of any size, and even if the bit width is different when divided into one macro cell. I do not care. For example, when dividing a 256 word x 36 bit RAM into 8 bit units, 256 words x 36 bits.

4 8-bit RAM, 256 words x 4 bits R
There may be one AM. Also single boat RAM3
, ROM 81, multiplier 91, and a test circuit externally attached thereto.

〔Effect of the invention〕

According to the present invention, when testing a macrocell, it is divided into an arbitrary number of parts with an arbitrary bit width, so by dividing only large macrocells into bit widths, the number of external terminals for testing on the entire chip can be greatly reduced. can be reduced to

[Brief explanation of drawings]

Figures 1 to 7 are diagrams for explaining the present invention in detail, Figure 1 is its overall configuration diagram, Figure 2 is a block diagram of its single board RAM, and Figure 3 is its single board RAM with built-in test circuit. Block diagram of the port RAM. Figure 4 is its timing chart. Figure 5 is the timing chart of the read mode during macro test. Figure 6 is the timing chart of write mode during macro test. Figure 7 is the timing chart of user mode. 8 is an overall configuration diagram showing the first embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 9.10 is a second embodiment of the semiconductor integrated circuit device according to the present invention.
9 is a diagram showing the overall configuration thereof, FIG. 10 is a block diagram of the test circuit built-in ROM, and FIGS. 11 and 12 are diagrams showing a third embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 11 is an overall configuration diagram thereof, FIG. 12 is a block diagram of a multiplier with a built-in test circuit, and FIG. 13 is a macro cell showing a fourth embodiment of a semiconductor integrated circuit device according to the present invention. Explain the case where there are two or more. FIG. 1... Composite semiconductor integrated circuit (semiconductor integrated circuit device), 2... Random logic circuit, 3...
Single boat RAM (macrocell), 4 to 9.63
~69.101~104...External input terminal, lO...External input/output terminal, 11-13...Input buffer, 14...
・Bidirectional human output buffer, 15-18...Selector circuit, 19.20.54.73.74.77-80
...Path driver, 21...Address bus, 22...Input data path, 23...Output data path, 31.32... Manual data for random logic circuit, 33...Input data for random logic circuit,
34...-Write enable signal, 35...
...Address signal, 36.37...Manual data signal, 38.39.
...Output data signal, 41...Buffer, 42.82...Address buffer, 43.83
...Address transition detection circuit, 44...
Precharge circuit, 45.84...Row decoder, 46.85...
...Column decoder, 47.88...Sense amplifier, 48...Write amplifier, 49.87...Column select, 50...
...Memory cell array, 51-53...Selector, 61.62...Single boat RAM (macro cell), 70.71...External output terminal, 72.76...
...Decoder with enable terminal, 81...
ROM (macro cell), 91... Multiplier (macro cell), 92.94... Selector, 93... Multiple buffer, 95...
・Booth decoder, 96...Multiple array, 97...Adder circuit, 105-108...Latch circuit, IO2...
...Decoder with enable terminal, 111...
Single port RAM with built-in test circuit (macrocell)
, 112... ROM with built-in test circuit (macro cell), 113... Multiplier with built-in test circuit (
macrocell), MTM...Test mode selection signal, TWE...Write enable signal in test mode, TAO, TAI...Address signal for test circuit, MS... ... Macrocell under test selection signal, B501BSI... Bit select signal, TIO-TI3... Input data signal for test circuit, TDO-TD3... Output signal for test. Macro test mode Macro test mode, write mode/read mode Timing chart of read mode during macro test to explain principle Timing chart of write mode during macro test to explain principle Fig. 2 Fig. User mode Timing chart of user mode to explain principle 〇- Lolo H)-+

Claims (1)

[Claims] In a semiconductor integrated circuit device in which a random logic circuit and a macro cell are mixed in one chip, a test circuit for testing the macro cell based on an external test signal is provided in the chip, and the test circuit tests one macro cell. 1. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is divided into a plurality of macro cells having a predetermined bit width, and the test is performed on the divided macro cells.