JPS60201472A - Matrix product computing device - Google Patents

Abstract

PURPOSE:To obtain a matrix product computing device in which matrix product is computed in short computing operator obtaining the product of two operands and integrating them in a matrix and connecting each operand registers of each operator as a shift register. CONSTITUTION:Product adders are arranged in a matrix, operand registers RA of each row are connected as shift registers and operand registers RB of each column are connected as shift registers. When an operand comes from a data bus DB, a clock signal (CA or CB) is given to a corresponding row or column and the content of the data bus is stored in the 1st row or column of operand register, the operand stored so far is stored in the operand register of the next stage and the operand is moved similarly. A flip-flop FFA or FFB in the product adder is set at the same time. When a clock Cop is outputted after the operand is fed to he required row or column, the arithmetic is conducted only for the product adder whose flip-flops FFA, FFB are both set.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the field to which the invention pertains The present invention relates to a device that assists a central processing unit to calculate an IJ product at high speed.

(2) Description of conventional technology To calculate the product of an (m, n) type matrix and a <n, t) type matrix using a conventional device, 1. The calculation of Σ alj-1)jk was performed m·''-1 times. To increase your computing power using this method,
aij @ 1) jl() and calculates the cumulative sum. However, if the number of product-accumulators increases considerably, the operand supply of the data bus will not be able to keep up, and the In the end, the limits of calculation speed became apparent due to the capabilities of the data bus.

In this case, since the supply time of all operands becomes the calculation time, the following relationship holds true.

T□=2nsmst/M (11) where sTO is calculation time (seconds) and 2M is the amount of operands that the data bus can supply per unit time.

For example, when calculating the product of (100,100) type matrices, if M is 100M words/sec, To will be 20 msec, and no matter how many product-sum calculators there are, calculations cannot be made any faster. Multiplexing the buses increases operand supply capability, but the degree of multiplicity cannot be increased much because main memory contention occurs and control between buses becomes complicated.

(3) Object of the Invention An object of the present invention is to provide a matrix product calculation device that can calculate matrix products in a short calculation time, is easy to control, and requires a small number of product-sum calculation units.

(4) Structure of the Invention According to the present invention, arithmetic units that multiply the products of two operands and take the cumulative sum are arranged in a grid, and each operand register of each arithmetic unit is connected as a shift register to form a matrix product. Get a computing device.

(5) Examples of the invention Next, the main feature will be explained in more detail with reference to the drawings.

FIG. 1 shows an example of the internal configuration of a product-sum calculator that is a component of the multi-IJ multiplication calculation device of the present invention, and shows an internal data bus that supplies information from the previous stage or data source using a clock CA. An internal data bus DBI that supplies information from previous stages or other data sources by clock CB as well as an operand register RA that stores the contents of DAI.
Operand register RB that stores the contents of and each clock zero.

It consists of an arithmetic unit OP that is activated by CB and COP and performs multiplication and accumulation. In the arithmetic unit OP, the clock CA drives the flip-flop 70-tube FFA, the clock CB drives the flip-flop FFB, and the flip-flop 70-tubes FFA and F
The output from the FB and the clock COP are ANDed to create a control signal in the control section. On the other hand, a control signal from the control unit causes the operand register R to be transferred from the internal data bus DAO.
A75) Obtain the information from the operand register RB from the internal data bus DBO, multiply them by a multiplier, and use the output as the output from the result register that stores the result of the previous multiplication. are added by an adder and newly stored in the result register.

FIG. 2 shows an embodiment of the present invention, in which the product-accumulators shown in FIG. 1 are arranged in a grid, the operand registers RA for each row are connected as shift registers, and the operand registers RB for each column are also shifted. It is wired as a resistor.

Therefore, clock CA.

CB is supplied to each row and each column. Also clock C
op is commonly supplied to all product-sum calculation units.

In this operation, when an operand is sent from the data bus DB, a clock signal (CA or CB) is output to the corresponding row or column, and the contents of the data bus are stored in the operand register in the first column or row. , the operands stored up to that point are stored in the next-stage operand register, and the operands are moved in the same manner thereafter. At the same time, 7 lip-flops FFA or FFB in the product-sum calculator are set. After sending the operands to the required rows and 2 columns, the clock Cop is sent to the flip-flop FFA.

Calculation is performed only in the product-sum calculation unit in which both FFB is set. After the calculation is completed, flip-flops FFA and FFB
will be reset. This series of operations is called one cycle,
A matrix product can be obtained by executing the required number of cycles.

The order in which the operands are sent is as follows. Operand register RAtxJ sequentially sends n elements of the first row of matrix A and t-1 zeros following them. The n elements of the second row of A and the following m-1 zeros are sequentially sent to the operand register RA21 from the second cycle. Thereafter, in the same way, n 5- elements and t-1 zeros are sent with a delay of one cycle. Similarly, n elements and m-1 zeros in each column of B are 1
Send by shifting each cycle. After sending everything in this way, it will be piled up. Therefore, the number of cycles required to calculate the product is n+(m-1)+(t-1).

FIG. 3 is a diagram showing a specific example of operation.

This is an example of calculation of a (4,2) type matrix A and a (2,3) type matrix B. Each of the inner 4×3 squares corresponds to a product-sum calculator, and the cell confession shows the operation of the calculator corresponding to the elapsed cycle. The outer cells indicate the order in which operands are sent.

Next, a comparison will be made between the device of the embodiment and the conventional device in the case where m- product-sum calculators are used. The number of operands required per cycle is 2met in the conventional device, but only m+ in the device of this embodiment. On the other hand, the number of cycles required to calculate the matrix product is 6- times smaller than the conventional n cycles. For example, in the case of (10,10) type matrices, it is multiplied by 028, and in the case of (100,100) type matrices, it is approximately 003
It costs twice as much. Conversely, if the bus capacity remains the same, the number of computing units can be increased.

As described above, since it is less susceptible to bus limitations, the number of arithmetic units can be greatly increased, and calculation speed can be improved.

Furthermore, if the number of arithmetic units is kept the same, the efficiency of using the bus will be reduced, and the bus can be used for other data transfers, thereby improving the processing capacity of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a product-sum calculator used in an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a (4,2) type matrix. FIG. 3 is a diagram showing the operation when calculating the IJ product of a (2,3) type matrix. D person I, DBI...Internal data bus from the previous stage, DAO. DBO・・・・・・Internal data bus to next stage %C person, C
B: Clock pulse, Cop: Operation timing clock pulse, D: Connection to data bus.

Claims (1)

[Claims] Arithmetic units that multiply the products of two operands and take the cumulative sum are arranged in a grid, and the two operand registers of each arithmetic unit are elements that constitute shift registers for each row and column of the lattice. A matrix product calculation device featuring: