SU594502A1 - Conveyer-type multiplier - Google Patents

Description

(54) CONVEYOR MULTIBURST DEVICE

The invention relates to computing and can be used to create high-performance digital computers.

Multiplication devices are known comprising a multiplication matrix, a multiplier and a multiplier registers 1J. Such devices make it possible to shorten the multiplication time, but by large hardware costs with low equipment utilization efficiency.

The closest technical solution to the proposed is a device containing an adder matrix, the rows of which are divided into groups of two adders in each group united by transfer tires, multiplicative and multiplier registers, a buffer register, partial amount registers and partial transfer registers 121.

A disadvantage of this device is that it does not use the possibilities of increasing the productivity and efficiency of using equipment.

The aim of the invention is to improve the speed of the device.

This goal is achieved by the fact that in the device the transfer output of each previous group of the adder is connected to the input of the partial transfer memory register, the output of which

connected to the input of the subsequent group of summers, the output of the last register of the partial transfer memory is connected to the input of the last group of adders of the next line, the input of the register of storage of the partial amount is connected to the output of the amount of the corresponding group of adders in each row, and the output the lines, the outputs of the registers for storing the partial sums of the last line are connected to the output of the device and to the outputs of the buffer register whose outputs are connected to the inputs of the corresponding vuyuschih groups of the first row of adders.

The drawing shows a diagram of the proposed device, where adders i, registers 20-60, input buses 61, 62, output buses 63, 64.

The operation of the device is as follows.

The operands arrive synchronously from the external memory via the input buses 61, 62 to the registers 53, 46 of the first group of operands (4 bits of the multiplier and 15 bits of the multiplicand).

Claims (2)

Correction by the multiplier is carried out with simultaneously multiplying in each of the four steps (passes) by introducing the additions of the corresponding parts of the multiplier to the "free inputs of adders 4, I, 17, 18. In the fourth step, the product is corrected by the multiplicand on the last line of adders 18 , 19, 15, 16, And). Thus, the correction when multiplying operands in additional codes is carried out without time-consuming. The signal coming from the control unit of the digital computer (not shown in the drawing) records the multiplier, coming over the 4-bit bus 61 to the register 53, and multiplying, coming over the bus 62, to the register 46. Then the process starts. multiplying in the first stage of the device: the code multiplied from the output of the register 46 is fed to the adders 1,2, 3 of the first stage. The corresponding bits of the multiplier are fed to the gate inputs of these adders. The impulse coming from the control unit of the digital computer records the contents of registers 46, 53 into registers 47, 54, respectively. At the end of the summation time, the result of the summation appears simultaneously at the inputs of the register-zanchelka 20-25, forming the propagation front of the result moving along the multiplication matrix "diagonally." By a signal from the control unit of the digital computer, the summing result is recorded in the latch register 20-25 so that the transfer from the 1st adder is recorded into the bit 22 of the latch register 20-25, the four bits of the sum from the output of the 1st adder is written into the group of bits 23 of the latch register 20-25, the transfer of the adder 3 is recorded in bit 24, and the sum of the adder 3 is written into the group of bits 25 of the latch register. In the first step, zeroes are written to the four-bit groups 20, 21 of the latch 20-25. The same signal is used to write into the register of the multiplicand 48 and the register of the multiplier 55 of the second stage of the device from the registers 47, 54 of the first stage, respectively. Next, the multiplication process starts in the second stage, which is carried out similarly to the above, with the difference that, starting from the second stage, the multiplier addition is applied to the inputs of the adders 4, P, 17, 18 in case of a correction from the multiplier. The second step starts at the signal coming from the control unit of the digital computer, according to which the intermediate result in the register-latch 41-45 is recorded in the register 60. This signal will cope in time with the pulse on which the register 46 from the external memory The bus 62 is supplied with fifteen multiplicated bits. The next four bits of the multiplier are entered into register 53. The second and third tags are executed in the same way as the first and differ in the groups of bits located in the multiplier registers. In the fourth step, the addition of the multiplicand from the registers 48, 50, 52 enters the adders 10, 15, 16, 18, 19 in the case of correction from the multiplicand. This is possible for the reason that the mantissa of factors is equal to fifteen bits and in the fourth step the bottom row of adders 10, 15, 15, 18, 19 of the multiplication matrix is not occupied. The result of the fourth step from the latch register 41-45 is output to the external memory via the bus 64. The structure of the proposed device allows the simultaneous execution of four multiplications, each of which is carried out in the above manner in four steps. On the bus 63, lower order bits can be output, if necessary, to have a result with a doubled bit grid. Thus, the inclusion of the register-latch on the front of the distribution of the result allows to reduce the duration of the cycle of issuing the result, due to which it is possible to increase performance without significant equipment costs and, consequently, efficiency. Claims Conveyor multiplying device containing an adder matrix whose rows are divided into groups of two adders in each group combined with transfer tires, multiplier and multiplier registers, a buffer register, partial transfer registers and partial transfer registers, characterized in that the purpose of improving the speed of the device, in it the transfer output of each previous group of adders is connected to the input of the partial transfer memory register, the output of which is connected to the input the next group of adders, the output of the last register of partial transfer memory is connected to the input of the last group of adders of the next line, the register of storing the partial amount is connected to the output of the sum of the corresponding group of adders in each row, and the output is connected to the input of adders of the corresponding group of the next line, outputs of registers of partial memory the sums of the last line are connected to the output of the device and to the outputs of the buffer register, the outputs of which are connected to the inputs of the corresponding groups of total oops first line. Sources of information taken into account in the examination: 1. USSR Author's Certificate No. 324628, cl. G 06 F 7/39, 1969. 2. “Radio and Electronic Engineer, 1974, No. 44, No. i, pp. 21-26. ffi