JPS60200525A - Method for exposing pattern to light - Google Patents

Abstract

PURPOSE:To provide a method for transferring a large-size and high-resolution chip pattern by a method wherein the chip pattern is divided into several portions and each of the resultant patterns is exposed to light one after the other. CONSTITUTION:An aperture 9 is provided to occupy, for example, one fourth of a chip pattern 12. The aperture 9 covers an upper, left-hand area 12A, and alignment marks 13a, 13b. A support stage 4 with a wafer supporting table is adjusted so that the center of a first opening area 12A may coincide with an optical axis, that a first area 14A to be exposed may face the optical axis directly. An alignment unit 11 is used to have the alignment marks 13a, 13b meet 15a, 15b, respectively. When exposure is effected under these conditions, the area 12A may be thrown upon the area 14A to be exposed. The same procedure is followed for each of the other areas 12B, 12C, 12D so that all the areas belonging to the chip pattern 12 may be thrown upon the pattern 14. By this, a large-size, high-density chip with very fine features may be transferred.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pattern exposure method for transferring a horn onto a wafer surface, which is one of the manufacturing steps of a semiconductor device.

[Background technology]

Photolithography technology is essential in the manufacturing process of semiconductor devices such as ICs and LSIs, and this photolithography technology is used to transfer chip (element) patterns formed on photomasks onto wafers. In recent years, with the miniaturization and high integration of patterns in semiconductor devices, photomask patterns have become increasingly smaller and transferred onto wafers, but at the same time, improvements in resolution are required. For this reason, in this type of reduction type exposure apparatus, attempts have been made to improve the resolution by shortening the exposure wavelength to, for example, 365 nm or by increasing the numerical aperture.

However, as the numerical aperture increases, the field size (the plane dimension that can be exposed, the maximum chip size that can be exposed) is reduced, and becomes smaller than the current size.

On the other hand, it is presumed that LSIs and the like will be required to accommodate increased capacity and functionality.

The present inventor believes that with current exposure equipment and exposure methods, chip size and pattern refinement (resolution) are in an inverse relationship with each other, and it is difficult to expose a chip pattern with a large chip size and high resolution. [Objective of the Invention] The purpose of the present invention is to make it possible to expose large chip-sized chip patterns with high resolution; An object of the present invention is to provide a pattern exposure method that enables the manufacture of highly integrated pattern semiconductor devices.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, while using short wavelength light and an exposure device with a high numerical aperture, a large chip-sized chip pattern is divided into a plurality of parts, and each divided pattern is exposed to light to expose the entire chip pattern. This makes it possible to transfer a chip pattern with a large chip size and high resolution.

〔Example〕

1 to 3 are diagrams illustrating an embodiment of the present invention, and in the figures, reference numeral 1 denotes an exposure apparatus for carrying out the method of the present invention. This exposure apparatus 1 includes a light source 2 that emits light with a wavelength of 365 nm, for example, an illumination optical system 3 that irradiates a photomask M with light from the light source 2, a support stage 4 that supports the photomask M, and a pattern of the photomask M. The wafer W is provided with an imaging optical system 5 that forms an image on the wafer W, and a wafer support table 6 that supports the wafer W. The support stage 4 is moved to the planes X and Y by an attached drive mechanism 7.
The exposed area of the photomask M can be adjusted by appropriately setting the opening size of the aperture 9. The imaging optical system 5 reduces the pattern of the photomask M and forms an image on the wafer 71W, and its numerical aperture is made as large as possible to improve resolution. As a result, the exposure area of this optical system 5 becomes smaller by a factor of 10. Further, the support table 6 has a drive mechanism 10.
The loaded way/'W can be moved in the X, Y, and θ directions on the plane.

Note that the exposure apparatus 1 is equipped with an alignment device 11, which drives the wafer support table 6 using alignment marks formed on the photomask M and the wafer W, thereby positioning the photomask M and the wafer W relative to each other. ◇ On the other hand, on the photomask M, a chip pattern 12 of large chip size is formed approximately in the middle, and a tip pattern /1
Four alignment marks 13a+13b+13c*13d are formed at the outer center of each of the four sides of 1.
For this, the wafer/% pattern 14 formed on the wafer W up to the previous process (the pattern is at a stage where high-resolution processing is not required, and therefore the pattern is formed by the same method as in the past). Ajiiment marks 15at15b, 15c+15d are also placed on the outer center of the four sides.
is formed. It goes without saying that a known photoresist (IN) is formed on the surface of the wave SW.

Next, a non-lighting method of the present invention using the exposure apparatus 1 having the above configuration will be explained.

After placing the photomask M on the support stage 4 and placing the wafer W on the wafer support table 6, the aperture 9 is set to an opening approximately 1/4 the size of the chip pattern 12, and as shown in FIG. Chip pattern 1 as shown in (5)
2 upper left 1/4 range and alignment mark 13a
, 13b is opened. And this first
The support stage 4 is moved in X and Y so that the center of the aperture range 12A becomes the optical axis position. On the other hand, on the wafer 71W, as shown in FIG. 11, the shear alignment marks 13a and 13b are respectively 1
Alignment is completed to match 5a and 15b. In this state, the light I%t21. If exposure is performed using the illumination optical system 3 and the imaging optical system 5, the photomask M
The first opening range 12A of the chip pattern 12 is exposed onto the first exposure range 14A of the pattern 14 on the wafer W.

Next, the support stage 4 is operated and the aperture 9 is set to open the upper right quarter of the chip pattern 12 in the photomask M as the second opening range 12B, thereby simultaneously opening the second opening range 1211. Set to the optical axis position. At the same time, the wafer W side is also pattern 1.
The upper right quarter of 4 is set as the optical axis position as the second exposure range 14B, and here the alignment marks 13b and 13c,
15b and 15c to set the wafer/%W position with respect to the photomask M by the wafer support table 60
If exposure is performed in this state, the second opening range of the chip pattern will be exposed in the second exposure range 12B of the wafer "W".

Hereinafter, the same applies to the third section. The fourth opening ranges 12C112D are respectively set to the third opening ranges 12C and 112D of the wafer W. Fourth exposure range 14C, 14D
By sequentially exposing the chip pattern 12
The entire range of 0 can be exposed on the pattern 14. Here, at the boundary between each range, the patterns are exposed with some overlap, but the overlay accuracy is ±0.3 μm.
If it is below, the deviation etc. can be almost ignored. Incidentally, double exposure on the photoresist also poses almost no problem.

Therefore, according to this exposure method, the large chip size chip pattern 12 is divided into four parts, and the chip pattern is transferred as a whole by exposing the cracks individually. Depending on the light source wavelength and numerical aperture
) Pattern exposure of the required chip size can be performed even when the exposure range is narrowed. As a result, it is possible to transfer a chip pattern with a large chip size and 6D, but with a fine pattern and a high degree of integration.
Advantages for SI manufacturing (1) A chip pattern with a large chip size is divided into multiple areas, and the divided patterns are individually exposed to complete the exposure of the entire chip pattern. , a high-resolution exposure device that uses short wavelength light and a large numerical aperture, and therefore has a small exposure range, can realize exposure transfer of a chip pattern of a large chip size.

(2) Since it is possible to expose and transfer large chip-sized chip patterns using high-resolution exposure equipment, it is possible to transfer large chip sizes, fine patterns, and highly integrated patterns, making it extremely suitable for manufacturing VLSI, etc. Become valid.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist of the invention. For example, if there are 2, 3, or 5 or more chip patterns (generally an even number)
The number of divisions can be set as desired based on the relationship between the size of the exposure range of the exposure device and the chip size.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the technology for exposing chip patterns on semiconductor wafers, which is the field of application that formed the background of the invention. However, the present invention can be similarly applied to photolithography technology in other fields.

[Brief explanation of the drawing]

Figure 1 is a side configuration diagram of an exposure apparatus for carrying out the method of the present invention, Figure 2 is a schematic perspective view of the main parts, and Figure 3 (g), Q3) is the division state of each pattern of the photomask and wafer. 01... Exposure device, 2... Light source, 3... Illumination optical system, 4...
Support stage, 5... Imaging optical system, 6... Wave/support table, 9... Aperture, 11... Alignment device, 12... Chip pattern, 12A-1
2D... Divided opening range, 13axd... Alignment mark on mask, 14... Pattern, 14A
~14D... Divided exposure range, 15axd... Alignment mark on Ueno 1, M... Photomask,
W...Wafer. Agent Patent attorney Akira Takahashi Youngest brother 1 Figure

Claims (1)

[Claims] 1. When a large-sized pattern is exposed and transferred using an exposure device with a small exposure range, the pattern is divided into a plurality of ranges, and the pattern in each divided range is individually exposed and transferred. A pattern exposure method, characterized in that the exposure of the entire pattern is completed. 2. The pattern exposure method according to claim 1, wherein the side light device is a high resolution device that uses short wavelength light and a high numerical aperture imaging optical system. 3. The pattern exposure method according to claim 1, wherein a large chip size chip pattern is divided into four ranges, and each divided range includes an alignment mark.