JPS6019848B2 - voltage comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage comparison circuit, and more particularly to a voltage comparison circuit having highly accurate comparison capability.

2. Description of the Related Art A high-input impedance operational amplifier circuit including an offset correction circuit as shown in FIG. 1 is known as a high-precision voltage comparison circuit used in conventional AD converters and the like.

The circuit of FIG. 1 has switch 16 off, switches 17 and 5
0 is turned on to charge the capacitor 35 with a voltage that cancels out the error voltage of the amplifier 30, the switches 17 and 50 are turned off, and then the switch 16 is turned on, thereby grounding the signal voltage applied to the input terminal 101. This is to compare (detect) the magnitude of voltage with respect to a reference point with high precision. However, the conventional example shown in FIG. 1 requires two voltages, positive and negative, as operating power supply voltages for the operational amplifier, and has drawbacks such as the complicated circuit configuration of the operational amplifier itself. Further, since the offset correction operation is performed in a negative feedback loop with an extremely large amount of feedback, unstable factors such as oscillation and vibration may occur. These drawbacks have been a major undesirable constraint when realizing the circuit as a subsystem in an integrated circuit. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide a high-performance high-voltage comparator circuit.

The gist of the present invention is to provide a gate multiplier used in digital logic, provide a capacitor on the input side of the multiplier, and correct the threshold and value inherent to the gate multiplier with the capacitor. It is something.

The present invention will be explained in detail below. First, the premises of the present invention will be explained.

Figure 2 shows a MOS inverter intensifier (gate intensifier) 30
FIG. In the figure, 34, 35, 36 are E
type MOSFET, 37, 38, 39 are D type MOS
It is an FET. Terminal 500 is a power supply terminal. A gate intensifier 300 having such a configuration is equivalently shown in FIG. That is, the gate multiplier 3001, the ideal multiplier stage 31
input threshold and includes a value voltage source 40. In the present invention, such a gate intensifier 300 is actively utilized.

The problem with the gate multiplier 300 is the threshold voltage 40. It is necessary to perform correction to cancel this threshold value. For this purpose, a fourth correction capacitor 35 is installed at the input stage of the gate multiplier to cancel the value 40.
It is used in the configuration shown in the figure. However, since the intensifier is a gate-configured intensifier, it is actually necessary to instruct the capacitor 35 to charge and discharge based on timing. An embodiment of the present invention based on this viewpoint is shown in FIG. In FIG. 5, there is an inverter gate amplifier 300, and an FET switch (MOS transistor switch) 41, a capacitor 35, and an FET switch 42 are connected to its input stage. FE is connected to capacitor 35 and input terminal 10.
A T-switch 16 is connected, and a FET switch 17 is similarly connected between the capacitor 35 and the reference potential terminal 15. One of the FET switches 42 is a D-type FET (
A power supply terminal 500' is connected through a constant current circuit 70 formed by a depletion type FET 75. The output side of the gate amplifier 300 is connected to the negative input reset terminal R of the flip-flop 60 and to one input terminal of an AND gate 700.

The set input S of the flip-flop 60 is commonly connected to the gate electrode of the FET switch 41, and the control input terminal 60
I'm going to 1. The reset output Q of the flip-flop 60 is connected to the gate electrode of the FET switch 16 and the AND gate 7.
Connected to the 00 input. Further, the set output Q of the flip-flop is connected to the gate electrodes of FET switches 17 and 42, respectively. In the voltage comparator circuit of FIG. 5 having the above configuration, the input corresponds to the terminal 10, the output corresponds to the terminal 2.00, and the control input corresponds to the terminal 601.

Also, the value of the capacitor 35 is MO of about 10 to 10 F.
The current value of the constant current circuit 70 is approximately 1 μA. The operation of the voltage comparator circuit of FIG. 5 constructed as above will be explained in detail with reference to the operating waveforms of FIG. 6. Note that the symbols indicating each signal in Fig. 6 are number 5.
Corresponds to each symbol in the figure. First, prior to the voltage comparison operation, the control terminal 601 is set to T, as shown in the signal 601 in FIG.
A narrow pulse voltage is applied.

During the application period of this pulse, the FET switch 41 is turned on and the voltage at one terminal 350 of the capacitor 35 becomes zero.
At the same time, the output Q of the flip-flop 60 is "1", and Q is '
Since the state is '0'1, the FET switch 17 is turned on, the FET switch 16 is turned off, and the capacitor becomes the reference ground potential (terminal 15). In addition, the FET switch 42
is turned on, current flows from the constant current circuit 70 to the capacitor 35, and charging starts via the path from the capacitor 35 to the switch 17 to the terminal 15. This period is shown as L in FIG. 6 as an offset correction period. As charging progresses, the voltage at the terminal 350 of the capacitor 35 is just as high as the voltage at the gate amplifier 300.
When the threshold voltage Vth is reached, the output of the gate amplifier 300 is inverted and becomes "0", the flip-flop 60 is reset, Q becomes "0", Q becomes "1", and the FET
The switch 42 is turned off, the FET switch 17 is also turned off,
The FET switch 16 is turned on and the capacitor 35 is connected to the input terminal 1. The period after this becomes a comparison operation period, which is shown as t in the operation waveforms of FIG. The voltage comparator circuit during this period T3 is equivalently as shown in FIG. 4 above. That is, a capacitor 35 charged with a voltage equal to the threshold value of the gate amplifier is connected in series to the input of the gate amplifier 300. Therefore, depending on the magnitude of the signal voltage level applied to the input terminal 10 relative to the reference level, the output of the gate amplifier 300 changes accurately, and a rectangular wave with OV as the reference level is output to the output terminal 200 in FIG. can get. FIG. 6 shows the operating waveforms of each part when an input signal voltage having the shape shown in the figure is applied to the input terminal 10. As is clear from the above explanation, in the present invention, the operating amplification stage of the comparator circuit is based on an inverter gate amplifier commonly used in digital circuits as shown in Figure 2, so it operates on a single power supply. However, the circuit can be extremely miniaturized.

In addition, since the equivalent circuit voltage during the comparison operation period can be shown as shown in Figure 4, it is accurate, has little error, operates at high speed, and can handle continuous voltage input.In addition, the offset Vth correction operation is similar to the conventional one. Since the correction amount is detected based on the gate amplifier output relative to the logic level, regardless of the balance of the linear negative feedback circuit, there is no unstable factor associated with the negative feedback amount.Similarly, the offset correction amount The input side conversion of the gate amplifier due to the coupling to the next stage of the gate amplifier has a limited gain because the determination of the gate amplifier is not determined by the OV of the output of the gate amplifier but by the logic threshold value of the next stage. The effect of
- FIG. 7 shows a circuit diagram of another embodiment of the voltage comparator circuit of the present invention.

Further, FIG. 8 shows the operating waveforms of FIG. 7. The difference between FIG. 7 and the already explained configuration of FIG. 5 is that, first, the reference level during offset correction is not OV but an arbitrary reference voltage. This reference voltage source is 15 in FIG.
It is indicated by the code 0. Second, in order to shorten the offset correction time, the potential of the FET switch 41 at the time of initial setting is not set to OV, but is set to a voltage slightly lower than the threshold value voltage of the gate amplifier 300. This voltage source is shown as voltage source 450 in FIG. The other parts are the same as those shown in FIG. 5 described above.

The sequential operation order is the same as the detailed explanation of FIG. 6 and FIG. 6, so it will be omitted and only the different points will be explained. The operation of the circuit in FIG. 7 is as shown by the waveform of the capacitor 35 in the operating waveform in FIG. 8. When setting the period T, the voltage at one terminal of the capacitor is not set to OV, but is brought close to Vth by the power supply 450. Therefore, the amount of charge from the constant current circuit is small, and the offset correction period L can be shortened.

Further, as shown in the waveform diagram of the terminal 10 in FIG. 8, the voltage comparison level operates depending on the magnitude of the input with respect to the 0 voltage level V side of the voltage 150 used as the reference level for offset correction. In this way, the voltage comparator circuit of the present invention not only corrects the threshold value of the gate amplifier, but also
It can be easily and accurately set to any level including value voltage. This means that although it is a gated amplifier with synchronized input inputs, it essentially operates as an asynchronous voltage comparator with differential inputs; It is particularly useful for use in circuits, etc. According to the present embodiment described above, there are various effects as described below.

'1} The basic circuit is simple and can be made small.

{2) Operates with only a single power supply (positive voltage).

'31 High precision. '41 Operation speed is fast.

'5i Differential comparison is possible.

■ Effectively allows asynchronous input comparison.

{7) High stability of circuit operation.

'81 Wide input voltage range that can be operated.

Easy to manufacture using '91 MOS digital integration technology.

Since the voltage comparison circuit of the present invention determines the voltage comparison level based on the charge and discharge voltage of the capacitor connected in series to the input stage of the gate amplifier, the input side of the gate amplifier has a high input impedance and leakage current and stray capacitance are reduced. 4. It is desirable to design so that the A small transistor with high input impedance is suitable for the gate amplifier transistor. In the embodiment, a single channel MOS transistor is shown, but of course complementary MOS transistors and junction field effect transistors can also be used. The input/output polarity of the gate amplifier is not limited to the inverting one in the embodiment, but may be non-inverting, and both can be used. Further, in the above embodiment, the output of the flip-flop 60 is used as the gate signal for the gate 700, but a separately provided control signal such as a clock may also be used as the gate signal. Further, the logic circuit section for controlling each electronic switch has only been shown as a simple example that can satisfy the switching order of the switches, and various modifications can be made as necessary. According to the present invention described above, a high-performance voltage comparison circuit could be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional voltage comparison amplifier circuit with an offset correction function, Figure 2 is a circuit diagram of a MOS inverter gate amplifier, Figure 3 is an equivalent circuit diagram of Figure 2, and Figure 4 is a circuit diagram of the present invention. An equivalent circuit diagram for explaining the voltage comparison circuit of the present invention, FIG. 5 is a circuit diagram showing an embodiment of the voltage comparison circuit of the present invention,
6 is a waveform diagram showing operating waveforms of the circuit of FIG. 5, FIG. 7 is a circuit diagram showing another embodiment of the voltage comparison circuit of the present invention,
FIG. 8 is a waveform diagram showing operating waveforms of the circuit of FIG. 7. 300...gate multiplier, 35...capacitor, 60...
…flipflop. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 a first switch to which an input signal is applied to one end; a second switch to which a reference signal is applied to one end;
a capacitor in which the other ends of each of the first and second switches are commonly connected to one end thereof; and a gate amplifier in which the other end of the capacitor is connected to its own input terminal. At the same time, when adjusting the offset, the second switch is turned on to charge the capacitor by flowing current through the second switch, and after reaching the threshold voltage of the gate amplifier, the second switch is turned on. turning off the second switch and applying an input signal through the first switch;
In a voltage comparator circuit that uses a signal appearing on the output side of the gate amplifier in the process of applying this input signal to produce a voltage comparison result, a constant current source is connected to the input terminal of the gate amplifier. 3, a fourth switch whose one end is connected to the input terminal of the gate amplifier, and whose other end is connected to the reference potential, and a signal that temporarily turns on the fourth switch during offset adjustment. It has a flip-flop that is set and reset when the output of the gate amplifier is inverted and reaches a certain gate level, and the second and third switches are turned on by the set output of the flip-flop. , wherein the first switch is turned on by the reset output of the flip-flop.