JPS6019673B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6019673B2
JPS6019673B2 JP50145481A JP14548175A JPS6019673B2 JP S6019673 B2 JPS6019673 B2 JP S6019673B2 JP 50145481 A JP50145481 A JP 50145481A JP 14548175 A JP14548175 A JP 14548175A JP S6019673 B2 JPS6019673 B2 JP S6019673B2
Authority
JP
Japan
Prior art keywords
electrode
insulator
semiconductor device
base electrode
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50145481A
Other languages
Japanese (ja)
Other versions
JPS5268393A (en
Inventor
成通 長野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP50145481A priority Critical patent/JPS6019673B2/en
Publication of JPS5268393A publication Critical patent/JPS5268393A/en
Publication of JPS6019673B2 publication Critical patent/JPS6019673B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】 本発明は、少なくとも一個のトランジスタ(ホト・トラ
ンジスタやFETなどの特殊トランジスタをも含む)を
備えている半導体装置に係り、されに詳しくいえば、前
記トランジスタのベース電極(又はゲート電極)が静電
遮へいされている半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including at least one transistor (including special transistors such as phototransistors and FETs), and more specifically, the present invention relates to a semiconductor device including at least one transistor (including special transistors such as phototransistors and FETs), and more specifically, The present invention relates to a semiconductor device in which a gate electrode (or a gate electrode) is electrostatically shielded.

トランジスタには、ェミッタ電極(又はソース電極)、
コレクタ電極(又はドレィン電極)の外べ−ス電極(又
はゲート電極)が備えられているという事は周知の事実
であり、通常前記三電極とも電極又は電気回路部品等に
接続して用いられている。
The transistor has an emitter electrode (or source electrode),
It is a well-known fact that a base electrode (or gate electrode) is provided outside the collector electrode (or drain electrode), and the three electrodes are usually used by connecting them to electrodes or electrical circuit components. There is.

通常のェミッタ(又はソース)接地極の回路形式に於い
ては制御用電極としてはベース(又はゲート)電極が又
共通電極としてはェミッタ(又はソース)電極、出力用
電極としてはコレクタ(又はドレイン)電極がそれぞれ
用いられる。しかるに、特殊な用途に用いる場合(たと
えばホト.トランジスタを受光素子として用い、ある一
定の光入力に対して大きな出力電流を得ようとする場合
)には、ベース用電極に抵抗値の極めて大きな電気低抗
を接続するか、又はベース用電極に如何なる電気回路部
品をも接続せず、すなわちべース用電極を開放した状態
で使用されることがある。このような場合、従来の半導
体装置では、べ−ス電極がいわゆるアンテナとしての機
能を有し、又は電極を覆っている絶縁体の表面もしくは
表面近傍の絶縁体内部漏えい電流の入力端子として働き
、誤動作を生じ易いという欠点があった。
In a normal emitter (or source) grounded circuit type, the base (or gate) electrode serves as the control electrode, the emitter (or source) electrode serves as the common electrode, and the collector (or drain) serves as the output electrode. Electrodes are used respectively. However, when used for special purposes (for example, when using a phototransistor as a light-receiving element and trying to obtain a large output current for a certain amount of light input), an electric current with an extremely high resistance value is attached to the base electrode. It may be used with a low resistor connected or without connecting any electrical circuit components to the base electrode, that is, with the base electrode open. In such cases, in conventional semiconductor devices, the base electrode functions as a so-called antenna, or acts as an input terminal for leakage current inside the insulator at or near the surface of the insulator covering the electrode. The disadvantage is that malfunctions are likely to occur.

本発明の一つの目的は、前記欠点を解消した、誤動作の
生じ難い高性能半導体装置を提供することである。本発
明の他の目的は、前記高性能性を失うことなく低価格化
しうる半導体装置を得ることである。
One object of the present invention is to provide a high-performance semiconductor device that eliminates the above-mentioned drawbacks and is less likely to malfunction. Another object of the present invention is to obtain a semiconductor device whose cost can be reduced without losing the above-mentioned high performance.

本発明によれば、各種半導体装置における少なくとも一
個のトランジスタのベース用電極(又はゲート用電極)
を静電遮へいすることにより第1の目的が達成できる。
According to the present invention, the base electrode (or gate electrode) of at least one transistor in various semiconductor devices
The first objective can be achieved by electrostatic shielding.

さらに、本発明によれば、前記遮へいを行うための導電
性部材とベース用電極(又はゲート用電極)との間に設
ける絶縁体のみをその他の部分における絶縁体よりも気
密性および電気的絶縁性の優れた材質で形成することに
より第2の目的が達成出来る。以下、本発明について図
面を参照して詳細に説明する。
Further, according to the present invention, only the insulator provided between the conductive member for shielding and the base electrode (or gate electrode) has better airtightness and electrical insulation than the insulator in other parts. The second objective can be achieved by forming it from a material with excellent properties. Hereinafter, the present invention will be explained in detail with reference to the drawings.

第1図は、従釆の半導体装置の一例として、一個の発光
ダイオードと一個の受光トランジスタとを備えて成る光
結合半導体装置の斜視図である。図中、1および2はそ
れぞれ発光ダイオードの陽極用電極および陰極用電極、
3,4および5はそれぞれ受光トランジスタのェミッタ
用電極、ベース用電極およびコレクタ用電極、6は金属
容器、7は絶縁体を示す。電極1および電極2とに電源
を接続し電極(通常数ミリアンベアないし数百ミリアン
ベア)を適すると、前記ダイオードが発生し、受光トラ
ンジスタの電極3又は電極5から前記入力電流に対応し
た電流を取り出すことができる。このダイオード入力電
流に対する出力電流の比は通常CTR(CmrentT
鼠nsmISSIonRatio:電流伝達率)と呼ば
れており、該CTRは前記発光ダイオードおよび前記受
光トランジスタの性能に依存することは勿論、受光トラ
ンジスタのベース用電極4に接続される電気抵抗器の抵
抗値によっても影響を受ける。CTRの値は、一般に大
きい程望ましく、そのためには前記抵抗値を極めて大き
くするか、又はベース用電極に電気低抗器を接続しない
(すなわちベース電極を開放にする)事が必要である。
FIG. 1 is a perspective view of an optically coupled semiconductor device comprising one light emitting diode and one light receiving transistor as an example of a subordinate semiconductor device. In the figure, 1 and 2 are the anode electrode and cathode electrode of the light emitting diode, respectively;
Reference numerals 3, 4 and 5 respectively indicate an emitter electrode, a base electrode and a collector electrode of the light-receiving transistor, 6 a metal container, and 7 an insulator. When a power source is connected to the electrodes 1 and 2 and the electrodes (usually several milliamps to several hundred milliamps) are connected, the diode is generated and a current corresponding to the input current is extracted from the electrode 3 or electrode 5 of the light receiving transistor. I can do it. The ratio of output current to diode input current is usually CTR (CmrentT
The CTR depends not only on the performance of the light-emitting diode and the light-receiving transistor, but also on the resistance value of the electric resistor connected to the base electrode 4 of the light-receiving transistor. is also affected. Generally, the larger the CTR value is, the more desirable it is, and for this purpose, it is necessary to make the resistance value extremely large or to not connect an electric low resistor to the base electrode (that is, to leave the base electrode open).

しかるに、これら何れの場合でも前記ベース電極4がい
わゆるアンテナとして作用し、光結合半導体装置の使用
されている場所近傍に存在する何らかの電気信号を受信
してしまい前記半導体装置が誤動作を起こす可能性があ
った。この欠点は、電極4を短かく切り取って使用すれ
ばある程度防げるが、完全ではなく、また絶縁体7の表
面が汚れたり、あるいは表面に水分が付着したような場
合には前記絶縁体の表面又は該表面近傍の絶縁体内部を
通って流れる漏洩電流が増大し、該漏洩電流がベース電
極に流れ込むことによっても前記半導体装置は誤動作を
起こすという欠点がある。
However, in any of these cases, the base electrode 4 acts as a so-called antenna, and there is a possibility that the semiconductor device may malfunction due to reception of some electrical signal present near the location where the optically coupled semiconductor device is used. there were. This drawback can be prevented to some extent by cutting the electrode 4 short and using it, but it is not completely possible, and if the surface of the insulator 7 becomes dirty or moisture adheres to the surface, the surface of the insulator 7 or The leakage current flowing through the inside of the insulator near the surface increases and the leakage current flows into the base electrode, which also causes the semiconductor device to malfunction.

この欠点は特にモールド形半導体装置の場合に顕著であ
った。第2図は、本発明による一実施例である光結合半
導体装置の斜視図を示し、1なし、し7は第1図に示し
た1ないし7と本質的に同一のものを示す。
This drawback was particularly noticeable in the case of molded semiconductor devices. FIG. 2 shows a perspective view of an optically coupled semiconductor device according to an embodiment of the present invention, and 1 and 7 are essentially the same as 1 to 7 shown in FIG.

同図において、8は絶縁体7の表面に塗布又はスハッタ
等の方法でベース用電極4を包囲する如くに形成された
導電層を示し、かつ9は該導電層8に電気的に接続され
た接地用電極を示す。なお、図面から明らかな如く、ベ
ース用電極4と前記導電層8とは電気的に絶縁されてい
る。本実施例においては、仮りにベース用電極4を開放
で使用する場合においても、該電極4は絶縁体7の表面
に設けられた接地電位導電層8によって他の電極と静電
的に分離されているので、絶縁体表面の漏洩電流による
誤動作は生じない。
In the figure, reference numeral 8 indicates a conductive layer formed on the surface of the insulator 7 so as to surround the base electrode 4 by coating or scattering, and reference numeral 9 indicates a conductive layer that is electrically connected to the conductive layer 8. Shows the grounding electrode. Note that, as is clear from the drawings, the base electrode 4 and the conductive layer 8 are electrically insulated. In this embodiment, even if the base electrode 4 is used in an open state, the electrode 4 is electrostatically separated from other electrodes by the ground potential conductive layer 8 provided on the surface of the insulator 7. Therefore, malfunctions due to leakage current on the insulator surface will not occur.

また前記ベース用電極4を短かく切り取ってしまえば、
前記導電層の遮へい効果によってベース電極のアンテナ
作用が軽減され、したがって誤動作が生じなくなるとい
う特長がある。さらに本実施例では外観を一見するのみ
でベース電極がどの電流に相当するかを直ちに判別出来
るという特長もある。第3図は、本発明による他の実施
例の光結合半導体装置の斜視図を示し、1なし、し7は
第1図および第2図において説明した部材と本質的に同
一のものである。
Moreover, if the base electrode 4 is cut short,
The antenna effect of the base electrode is reduced due to the shielding effect of the conductive layer, which has the advantage that malfunctions do not occur. Furthermore, this embodiment has the advantage that it is possible to immediately determine which current the base electrode corresponds to just by looking at the exterior. FIG. 3 shows a perspective view of an optically coupled semiconductor device according to another embodiment of the present invention, in which 1 and 7 are essentially the same members as explained in FIGS. 1 and 2.

図中、10は絶縁体の丸棒状突起部を示し、該突起部1
0は絶縁体外径と同心状に配置されており、かつその表
面には接地用導電層18が設けられている。さらに、ベ
ース用電極4の中心軸は前記丸棒状突起部IDの中心軸
と一致する如くに配置されている。本実施例によれば、
ベース電極部はいわゆるシールド線形式又は同軸線路形
式となっており、第2図の実施例において説明したアン
テナ作用の軽減および漏洩電流の遮断作用の何れも達成
でき、したがって誤動作を生じない光結合半導体装置が
得られるという特徴をもつている。
In the figure, 10 indicates a round bar-shaped protrusion of the insulator, and the protrusion 1
0 is arranged concentrically with the outer diameter of the insulator, and a grounding conductive layer 18 is provided on its surface. Further, the center axis of the base electrode 4 is arranged so as to coincide with the center axis of the round bar-shaped protrusion ID. According to this embodiment,
The base electrode part is in the form of a so-called shielded wire or coaxial line, and is an optically coupled semiconductor that can both reduce the antenna effect and cut off leakage current as explained in the embodiment of Fig. 2, and therefore does not cause malfunction. It has the characteristic that a device can be obtained.

さらに、本実施例ではベース入力インピーダンスが小さ
くなるため特にベース用電極の開放状態で使用する場合
でも、ベース用電極を切り取るという作業は不必要であ
り、したがって作業能率が向上するという特徴もある。
なお、第3図に示した実施例では、突起部を絶縁体の中
心位置に配列した場合を示したが、必ずしも中心位置に
配列する必要はなく、任意の位置に設けても本発明によ
る効果は得られる。なお、以上の実施例においては静電
遮へい用導電部村8又は18が接地用電極と接続又は兼
用となっている場合について示したが、本発明は以上の
場合にのみ限定されるべきではなく、たとえば前記導電
性部材をェミッタ用電極(又はソース用電極)に接続し
ても全く同様な効果が得られる。
Furthermore, in this embodiment, since the base input impedance is reduced, there is no need to cut out the base electrode even when the base electrode is used in an open state, so that the work efficiency is improved.
Although the embodiment shown in FIG. 3 shows the case where the protrusions are arranged at the center of the insulator, it is not necessary to arrange them at the center, and the effect of the present invention can still be achieved even if the protrusions are arranged at any position. can be obtained. In addition, in the above embodiment, the case where the electrostatic shielding conductive part 8 or 18 is connected to or also serves as a grounding electrode is shown, but the present invention should not be limited only to the above case. For example, the same effect can be obtained even if the conductive member is connected to the emitter electrode (or source electrode).

第4図は本発明によるさらに他の実施例であるところの
モールド形光結合半導体装置の断面模形図を、第5図は
第4図に示された前装装置の右側から見た側面図を示し
、図中1なし、し5は第1図ないし第3図において説明
した1ないし5と本質的に同一の電極を示す。同図にお
いて11は発光ダイオード20の陽極と陰極1とを接続
するりード線を、13および14はそれぞれ受光トラン
ジスタ30のェミッタとェミツタ用電極3とを接続する
りード線およびベースとべ−ス用電極4とを接続するり
ード線を、40は電気的絶縁性・気密性共に優れた絶縁
部材を、5川ま通常のモールド半導体装置に使用されて
いる例えばシリコーン樹脂等の中程度の電気絶縁性およ
び気密性を有する比較的安価な電気絶縁体を、60は電
気的絶縁性・気密性共に良好で、かつ発光ダイオードの
発生する光(赤外線等の可視光以外の光をも含む)を透
過しうる電気的絶縁体を、28はェミッタ用電極3と一
体化されて、ベース用電極4を包囲する如くに構成され
た導電性部材を示す。本実施例によれば、ベース用電極
4を取り巻いている絶縁体40が絶縁性・気密性共に優
れている為に該絶縁体の内部漏洩電流は殆んど生せず、
また前記絶縁体表面が導電性液体等で汚染された場合で
もコレクタ用電極等からの表面漏洩電流は静電遮へい用
導鷺性部村28により遮へいされてベース用電極4に流
れ込むことはない。
FIG. 4 is a schematic cross-sectional view of a molded optically coupled semiconductor device according to still another embodiment of the present invention, and FIG. 5 is a side view of the front mounting device shown in FIG. 4, seen from the right side. 1 to 5 indicate essentially the same electrodes as 1 to 5 explained in FIGS. 1 to 3. In the figure, 11 is a lead wire that connects the anode and cathode 1 of the light emitting diode 20, and 13 and 14 are lead wires that connect the emitter and emitter electrode 3 of the light receiving transistor 30, and the base and base wires, respectively. 40 is an insulating material with excellent electrical insulation and airtightness; 60 is a relatively inexpensive electrical insulator that has good electrical insulation and airtightness, and transmits light generated by light emitting diodes (including light other than visible light such as infrared rays). Reference numeral 28 indicates a conductive member that is integrated with the emitter electrode 3 and surrounds the base electrode 4. According to this embodiment, since the insulator 40 surrounding the base electrode 4 has excellent insulation and airtightness, almost no internal leakage current occurs in the insulator.
Further, even if the surface of the insulator is contaminated with a conductive liquid or the like, surface leakage current from the collector electrode etc. is shielded by the electrostatic shielding conductive part 28 and does not flow into the base electrode 4.

したがって従来のモールド形光結合半導体装置でいよい
よ遭隅するところのモールド材質汚染の為に生ずる漏洩
ベース入力電流による前記装置の誤動作を防ぐことがで
きる。本発明によれば一部金属ケースを用にる半導体装
置と同程度の性能を有し、かつモールド形である為低価
格化しうるという特徴を持つてる。なお、本実施例にお
いてはベース用電極4を包囲する如くに設けられた導電
性部材28はェミツタ用電極3と一体化される製作さら
た場合について説明したが、第2図又は第3図に示した
実施例における如く前記部村23はェミッタ用電極と独
立に設けても良い。
Therefore, it is possible to prevent malfunction of the device due to leakage base input current caused by contamination of the mold material, which is a common problem in conventional molded optically coupled semiconductor devices. According to the present invention, the device has a performance comparable to that of a semiconductor device that uses a partially metal case, and because it is a molded device, the cost can be reduced. In this embodiment, a case has been described in which the conductive member 28 provided so as to surround the base electrode 4 is integrated with the emitter electrode 3. As in the embodiment shown, the section 23 may be provided independently of the emitter electrode.

また一般に半導体装置が液体等で汚染された場合、該装
置の絶縁体内部に於ける電導性は絶縁体表面から指数開
放的に減少するのが通例であるから絶縁体40と絶縁体
50とは必ずしも育質な部材で構成しなくても良く、ベ
ース用電極(又はベース用電極)を包囲する如くに形成
された導電性部材を、半導体装置を形成せる絶縁体表面
からある程度内部にまで伸長して設けておくだけでも、
本発明の目的を達成することができる以上、要するに本
発明によれば少なくとも一個のトランジスタを有する半
導体装置において、該トランジスタのベース用電極(又
はケート電極)を包囲する如くに導電性部村を設け、該
導電性部材を接地用電極又はェミッタ用電極(又はソー
ス電極)と接続ないし一体化して製作することにより誤
動作のない高性能半導体装置を得ることができる。
Furthermore, in general, when a semiconductor device is contaminated with a liquid or the like, the conductivity inside the insulator of the device usually decreases exponentially from the surface of the insulator. It does not necessarily have to be made of a high-quality material, and the conductive member formed to surround the base electrode (or the base electrode) can be extended to some extent inside from the surface of the insulator on which the semiconductor device is formed. Even if you just set it up,
As long as the object of the present invention can be achieved, in short, according to the present invention, in a semiconductor device having at least one transistor, a conductive region is provided so as to surround the base electrode (or gate electrode) of the transistor. By connecting or integrating the conductive member with a grounding electrode or an emitter electrode (or source electrode), a high-performance semiconductor device without malfunction can be obtained.

なお、以上の実施例では交結合半導体装置についてのみ
説明したが本発明はこれに限定ごらるべきではなく、他
の種々の半導体装置において静電遮へいを要するトラン
ジスタのベース用電極(又はゲート用電極)に対して本
発明の何れか一つ、又は適宜組合わせて適用することが
できる。
In the above embodiment, only a cross-coupled semiconductor device has been described, but the present invention should not be limited to this, and may be applied to a base electrode (or a gate electrode) of a transistor that requires electrostatic shielding in various other semiconductor devices. Any one of the present invention or an appropriate combination of the present invention can be applied to the electrode).

図面の簡単な説頚 第1図は従来の光結合半導体装置の斜視図、第2図およ
び第3図はそれぞれ本発明による一実施例および他の実
施例の斜視図、第4図は本発明によるさらに他の実施例
の断面模型図、第5図は第4図に示された実施例の右側
から見た側面図を示す。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a conventional optically coupled semiconductor device, FIGS. 2 and 3 are perspective views of one embodiment and another embodiment of the present invention, respectively, and FIG. 4 is a perspective view of a conventional optically coupled semiconductor device. FIG. 5 shows a side view of the embodiment shown in FIG. 4 as seen from the right side.

1および2はそれぞれ発光ダイオードの陽極用電極およ
び陰極用電極、3,4および5はそれぞれ受光トランジ
スタのェミッタ用電極、べ−ス用鰭極およびコレクタ用
電極、6は金属容器、7は絶縁体、8および18は導電
体層、9は接地用電極、10は絶縁体突起部、11,1
2および13はすべてリード線、2川ま発光ダイオード
、30は受光トランジスタ、60‘ま前記ダイオード2
0の発生する光を透過する絶縁体、4川ま絶縁性・気密
性共に優れた絶縁体、5川ま通常のモールド用絶縁体、
28は導電性部材を示す。
1 and 2 are respectively the anode electrode and the cathode electrode of the light emitting diode, 3, 4 and 5 are the emitter electrode, base fin electrode and collector electrode of the light receiving transistor, respectively, 6 is a metal container, and 7 is an insulator. , 8 and 18 are conductor layers, 9 is a grounding electrode, 10 is an insulator protrusion, 11, 1
2 and 13 are all lead wires, 2 rivers are light emitting diodes, 30 are light receiving transistors, and 60' are the aforementioned diode 2.
An insulator that transmits the light generated by 0, an insulator with excellent insulation and airtightness, an insulator for normal molding,
28 indicates a conductive member.

第1図 多2図 第3図 第4図 繁タ図Figure 1 Multi 2 drawings Figure 3 Figure 4 Traditional map

Claims (1)

【特許請求の範囲】[Claims] 1 制御用電極が電気的に浮遊状態にあるトランジスタ
を備える半導体装置において、該トランジスタの制御用
電極を包囲する如くに導電性部材が設けられ、該導電性
部材が共通電極に電気的に接続されていることを特徴と
する半導体装置。
1. In a semiconductor device including a transistor with a control electrode in an electrically floating state, a conductive member is provided to surround the control electrode of the transistor, and the conductive member is electrically connected to a common electrode. A semiconductor device characterized by:
JP50145481A 1975-12-05 1975-12-05 semiconductor equipment Expired JPS6019673B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50145481A JPS6019673B2 (en) 1975-12-05 1975-12-05 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50145481A JPS6019673B2 (en) 1975-12-05 1975-12-05 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5268393A JPS5268393A (en) 1977-06-07
JPS6019673B2 true JPS6019673B2 (en) 1985-05-17

Family

ID=15386241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50145481A Expired JPS6019673B2 (en) 1975-12-05 1975-12-05 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6019673B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02210179A (en) * 1989-02-09 1990-08-21 Hideo Otake Window frame of building

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125585U (en) * 1978-01-11 1979-09-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02210179A (en) * 1989-02-09 1990-08-21 Hideo Otake Window frame of building

Also Published As

Publication number Publication date
JPS5268393A (en) 1977-06-07

Similar Documents

Publication Publication Date Title
US5521431A (en) Semiconductor device with lead frame of molded container
JPS6387758A (en) Semiconductor device
US4481521A (en) Insulated gate field effect transistor provided with a protective device for a gate insulating film
US4396932A (en) Method for making a light-activated line-operable zero-crossing switch including two lateral transistors, the emitter of one lying between the emitter and collector of the other
US4284898A (en) High voltage stable optical coupler
JPS6019673B2 (en) semiconductor equipment
US4599631A (en) Semiconductor apparatus having a zener diode integral with a resistor-transistor combination
US6927427B2 (en) Bidirectional static switch responsive in quadrants Q4 and Q1
US3518504A (en) Transistor with lead-in electrodes
US4649414A (en) PNPN semiconductor switches
US4458408A (en) Method for making a light-activated line-operable zero-crossing switch
US5053847A (en) Semiconductor device
US5298785A (en) Semiconductor device
CA2046815C (en) Semiconductor integrating circuit
KR850001643A (en) Amplifier circuit
US3504220A (en) Cathode unit
JPS6129559B2 (en)
JP2001291980A (en) Frame-ground connection structure
WO2023182051A1 (en) Electronic component
US4348651A (en) Cascading diode switches
MX170833B (en) HERMETIC TERMINAL SET
JPS58105562A (en) Semiconductor device
JPS5928625Y2 (en) Antenna terminal
JPS61119061A (en) Semiconductor integrated circuit device
JPS5851556A (en) Semiconductor integrated circuit device