US5053847A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US5053847A US5053847A US07/600,172 US60017290A US5053847A US 5053847 A US5053847 A US 5053847A US 60017290 A US60017290 A US 60017290A US 5053847 A US5053847 A US 5053847A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000000153 supplemental effect Effects 0.000 claims abstract description 11
- 230000003071 parasitic effect Effects 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
- H01L29/7304—Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
Definitions
- the present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device in which a plurality of transistor units are provided on a common substrate, an emitter ballast resistor is connected to the emitter of each transistor unit, and a stabilizing resistor is connected between the base and emitter of each transistor unit.
- a semiconductor device having multiple transistor units connected in parallel and formed in a common substrate is a semiconductor device having a structure generally called a mesh-or multi-emitter structure, as illustrated by an equivalent circuit in FIG. 1.
- a multi-emitter structure may include an emitter ballast resistor 8, for example, made of a polycrystalline silicon resistor connected between an emitter contact electrode 22 of each transistor unit 21 and a common emitter electrode 23 so as to expand the area of safe operation of each transistor unit.
- a resistor 26 is connected between a common base electrode 25 and the common emitter electrode 23 for the sake of stabilization of the withstanding voltage between the collector and emitter of each transistor unit.
- FIG. 2 is a sectional view of an example of such a semiconductor device.
- An N-type collector region 2, a P-type base region 3 and an N-type emitter region 4 are successively formed in a substrate 1, and then the substrate 1 is coated with an insulating film 5 of silicon dioxide, SiO 2 .
- Base electrodes 6 of the respective transistor units are formed so as to contact the base region 3 through the holes of the insulating film 5.
- Base electrodes 6 of the respective transistor units are connected in parallel to each other, and a base terminal B is led out from a bonding portion (not shown) of the connection.
- the parallel connection of the respective base electrodes 6 is shown by lines in the form of an equivalent circuit.
- Emitter contact electrodes 7 of the respective transistor units are formed so as to contact with emitter region 4 through the holes of the insulting film 5.
- Emitter ballast resistors 8 of polycrystalline silicon film are formed on insulating film 5 so as to contact with the respective emitter contact electrodes 7.
- emitter electrodes 9 are provided on the insulating film 5 so as to connect with the respective emitter ballast resistor 8. Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is led out from the bonding portion (not shown) of the connection. In FIG. 2 the parallel connection of the respective emitter electrodes 9 is shown by lines in the form of an equivalent circuit.
- an elongated N-type region 41 of the same conductivity type as emitter region 4 is formed in the surface layer of base region 3, and insulating film 5 is removed to expose both ends 11 and 12 of region 41 so as to make contact with one base electrode 6 and one emitter electrode 9, respectively.
- the region 41 acts as a resistive region between base electrode 6 and emitter electrode 9, so that it is possible to ensure the stabilization of the withstanding voltage between the collector and the emitter of each transistor.
- an NPN transistor structure is formed by the region 41, and the respective portions of base region 3 and collector region 2, which are located just under region 41.
- These parasitic transistor effects are weak in the region near end 11 contacting with base electrode 6 since an emitter current flows into the emitter through resistive region 41.
- the parasitic transistor effects are strong near end 12 of region 41 contacting emitter electrode 9 since this region acts as an emitter. Therefore, there has been a problem in that the transistor formed in the region near end 12 is not protected by the emitter ballast resistor so that the area of safe operation of the transistor becomes smallest and the device breaks down in this portion, making it impossible to obtain a desired area of safe operation for the semiconductor device.
- the semiconductor device comprises a plurality of transistor units formed in one and the same substrate, an emitter ballast resistor being connected to an emitter of each the transistor units, a stabilizing resistive region having the same conductivity type as the emitter region, and another resistor being inserted between an emitter electrode and one end of the stabilizing resistive region connected to the emitter region.
- the inserted resistor is formed simultaneously with the emitter ballast resistors by use of the same resistance material.
- emitter ballast resistors are added to respective emitters to expand the area of safe operation of respective transistor units, a stabilizing resistive region is included in a substrate between a base and an emitter to stabilize the withstanding voltage of the semiconductor device, and a supplemental resistor for functioning as an emitter ballast resistor is forced so as to be added to the stabilizing resistive region simultaneously with the formation of the emitter ballast resistors so as to weaken the parasitic transistor operation of the stabilizing resistive region to prevent the reduction in the area of safe operation of the semiconductor device.
- a stabilizing resistor to be connected between the base and the emitter may be alternatively formed on the substrate in the same manner as the emitter ballast resistors so that no parasitic transistor effects are generated to enable only the transistor units, each having the area of safe operation expanded by the function of the emitter ballast resistor, to operate in the resultant semiconductor device.
- a semiconductor device having an expanded region of safe operation it is possible to obtain a semiconductor device having an expanded region of safe operation.
- the semiconductor device of this invention comprises a plurality of transistor units each including an emitter contact, a base contact, and a collector contact formed in a common substrate, a plurality of emitter ballast resistors each coupled to a corresponding emitter contact of each of the plurality of transistor units, a stabilizing resistive region located in the substrate between a selected base contact and a lead-out electrode, the stabilizing resistive region having the same conductivity type as the selected emitter region, an emitter electrode coupled to the corresponding emitter contact through the respective emitter ballast resistor, and a supplemental resistor located between a selected emitter electrode and the lead-out electrode for coupling the selected emitter electrode to the lead-out electrode and for reducing parasitic transistor effects in the stabilizing resistive region.
- the semiconductor device comprises a plurality of transistor units each including an emitter contact, a base contact, and a collector contact formed in a common substrate, a plurality of emitter ballast resistors, each is coupled to a corresponding emitter contact of each of the plurality of transistor units, an emitter electrode is coupled to the corresponding emitter contact through the respective emitter ballast resistor, and a stabilizing resistor is located between a selected emitter electrode and a selected base contact, the emitter ballast resistor and the stabilizing resistor are formed from the same material.
- FIG. 1 is an equivalent circuit of a conventional semiconductor device.
- FIG. 2 is a cross-sectional view of a conventional semiconductor device
- FIG. 3 is a cross-sectional view of an embodiment of the semiconductor device according to the present invention.
- FIG. 4 is a cross-sectional view of another embodiment of the semiconductor device according to the present invention.
- FIG. 3 shows a cross-sectional view of an embodiment of the semiconductor device according to the present invention where like reference numerals refer to like parts in FIGS. 2, 3 and 4.
- An N-type collector region 2, a P-type base region 3 and an N-type emitter region 4 are successively formed in a substrate 1, and then the substrate 1 is covered with an insulating film 5.
- Base electrodes 6 are formed so as to contact with the base region 3 through the holes of the insulating film 5.
- the base electrodes 6 of the respective transistor units are connected in parallel to each other, and a base terminal B is led out from the common connection.
- Emitter contact electrodes 7 are formed so as to contact with emitter region 4 through the holes of insulating film 5.
- Emitter ballast resistors 8 each made of a polycrystalline silicon film are provided on insulating film 5 so as to contact with emitter contact electrodes 7, and emitter electrodes 9 are provided on insulating film 5 so as to contact with the respective emitter ballast resistors 8.
- Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is led out from the common connection.
- N-type stabilizing resistive region 10 of the same conductive type as emitter region 4 is formed in the surface of the base region 3. Insulating film 5 is removed to expose both ends 11 and 12 of stabilizing resistive region 10 so as to get respective contacts of base electrode 6 with end 11 of region 10 and a lead-out electrode 13 with end 12 of region 10. Lead-out electrode 13 also contacts with a supplemental resistor 14 formed on insulating film 5.
- a stabilizing resistor made of the N-type stabilizing resistive region 10 and the supplemental resistor 14 are inserted between a base and an emitter.
- Supplemental resistor 14 may be formed simultaneously with the emitter ballast resistor 8 by using the same material.
- the resistance value of the emitter ballast resistor 8 is selected to be about 10 ohms
- the resistance value of the N-type stabilizing resistive region 10 is selected to be about 100 ohms
- the resistance value of the supplemental resistor 14 is selected to be greater than or equal to that of emitter ballast resistor 8.
- FIG. 4 shows a cross-sectional view of another embodiment of the semiconductor device according to the present invention.
- An N-type collector region 2, a P-type base region 3, and an N-type emitter region 4 are successively formed in a substrate 1, and then substrate 1 is covered with an insulating film 5.
- Base electrodes 6 are formed so as to contact with the base region 3 through the holes of the insulating film 5.
- the respective base electrodes 6 of the transistor units are connected in parallel to each other, and a base terminal B is lead out from the common connection.
- Emitter contact electrodes 7 are formed so as to contact with emitter region 4 through the holes of the insulating film 5.
- Emitter ballast resistors 8 of polycrystalline silicon film are provided on insulating film 5 so as to contact with the respective emitter contact electrodes 7, and emitter electrodes 9 are provided on insulating film 5 so as to contact with the respective emitter ballast resistors 8.
- Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is lead out from the common connection.
- a stabilizing resistor 20 of polycrystalline silicon film is formed on the insulating film between a base electrode 6 and an emitter electrode 9 so as to contact with the base electrode 6 and the emitter electrode 9.
- Stabilizing resistor 20 conditions as a base-to-emitter stabilizing resistor. Since the stabilizing resistor 20 may be formed simultaneously with the emitter ballast resistor 8, execution of an additional step is not necessary.
- the resistance value of the ballast resistor 8 is established to be about 10 ohms
- base-to-emitter stabilizing resistor 20 can be designed to have a resistance value within a range of up to several hundred ohms by suitably selecting its length and width.
- a resistor is further inserted between a stabilizing resistive region embedded in a substrate and an emitter.
- the added resistor acts as an emitter ballast resistor which weakens a parasitic transistor function generated in the stabilizing resistive region between an emitter and a base, thereby making it possible to expand the area of safe operation of the semiconductor device and to prevent the semiconductor device from breaking down.
- the resistor can be formed simultaneously with the emitter ballast resistor by using the same material, without complicating the manufacturing process.
- a stabilizing resistive region located between a base contact and an emitter electrode is formed by a resistive layer on a substrate, so that it is not necessary to form a stabilizing resistive region in the substrate and a parasitic transistor having a small area of safe operation is not formed in each transistor unit in parallel. Accordingly, the area of safe operation of the semiconductor device is not reduced.
- the stabilizing resistive region can be formed simultaneously with emitter ballast resistors by using the same material and the same process, without complicating the manufacturing process.
Abstract
A multi-emitter type semiconductor device having multiple transistors coupled in parallel which utilize a common substrate. Between a selected emitter electrode and a base contact, a stabilizing resistive region is formed in the common substrate. In order to reduce the parasitic effects due to this region an additional emitter ballast resistor may be formed on the surface of an insulating layer over the substrate. This supplemental resistor formed on the insulating layer is made from polycrystalline silicon. Alternatively, the supplemental resistor can be combined with the resistance of the stabilizing region in a single resistor located on the surface of the insulating layer.
Description
This application is a continuation of application Ser. No. 07/194,467, filed May 12, 1988 now abandoned.
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device in which a plurality of transistor units are provided on a common substrate, an emitter ballast resistor is connected to the emitter of each transistor unit, and a stabilizing resistor is connected between the base and emitter of each transistor unit.
2. Description of the Prior Art
An example of a semiconductor device having multiple transistor units connected in parallel and formed in a common substrate is a semiconductor device having a structure generally called a mesh-or multi-emitter structure, as illustrated by an equivalent circuit in FIG. 1. A multi-emitter structure may include an emitter ballast resistor 8, for example, made of a polycrystalline silicon resistor connected between an emitter contact electrode 22 of each transistor unit 21 and a common emitter electrode 23 so as to expand the area of safe operation of each transistor unit. Additionally, a resistor 26 is connected between a common base electrode 25 and the common emitter electrode 23 for the sake of stabilization of the withstanding voltage between the collector and emitter of each transistor unit.
FIG. 2 is a sectional view of an example of such a semiconductor device. An N-type collector region 2, a P-type base region 3 and an N-type emitter region 4 are successively formed in a substrate 1, and then the substrate 1 is coated with an insulating film 5 of silicon dioxide, SiO2. Base electrodes 6 of the respective transistor units are formed so as to contact the base region 3 through the holes of the insulating film 5.
Moreover, emitter electrodes 9 are provided on the insulating film 5 so as to connect with the respective emitter ballast resistor 8. Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is led out from the bonding portion (not shown) of the connection. In FIG. 2 the parallel connection of the respective emitter electrodes 9 is shown by lines in the form of an equivalent circuit.
In base region 3, an elongated N-type region 41 of the same conductivity type as emitter region 4 is formed in the surface layer of base region 3, and insulating film 5 is removed to expose both ends 11 and 12 of region 41 so as to make contact with one base electrode 6 and one emitter electrode 9, respectively. Thus, the region 41 acts as a resistive region between base electrode 6 and emitter electrode 9, so that it is possible to ensure the stabilization of the withstanding voltage between the collector and the emitter of each transistor.
However, owing to the provision of the N-type resistive region 41, an NPN transistor structure is formed by the region 41, and the respective portions of base region 3 and collector region 2, which are located just under region 41. These parasitic transistor effects are weak in the region near end 11 contacting with base electrode 6 since an emitter current flows into the emitter through resistive region 41. The parasitic transistor effects are strong near end 12 of region 41 contacting emitter electrode 9 since this region acts as an emitter. Therefore, there has been a problem in that the transistor formed in the region near end 12 is not protected by the emitter ballast resistor so that the area of safe operation of the transistor becomes smallest and the device breaks down in this portion, making it impossible to obtain a desired area of safe operation for the semiconductor device.
It is therefore an object of the present invention to solve the problems in the prior art.
It is another object of the present invention to provide a semiconductor device, wherein the breakdown of the resistive region connected between a base and an emitter is prevented and the area of safe operation expanded by adding emitter ballast resistors to the emitters is not reduced, and wherein the semiconductor device can be manufactured easily without an increase in the chip area.
It is a further object of the present invention to provide a semiconductor device in which a resistor is connected between a base and an emitter so that no parasitic transistor is formed and the area of safe operation expanded by adding emitter ballast resistors to the emitters is not reduced.
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
In order to attain the above and other objects, according to an aspect of the present invention, the semiconductor device comprises a plurality of transistor units formed in one and the same substrate, an emitter ballast resistor being connected to an emitter of each the transistor units, a stabilizing resistive region having the same conductivity type as the emitter region, and another resistor being inserted between an emitter electrode and one end of the stabilizing resistive region connected to the emitter region. Preferably, the inserted resistor is formed simultaneously with the emitter ballast resistors by use of the same resistance material.
According to the present invention, emitter ballast resistors are added to respective emitters to expand the area of safe operation of respective transistor units, a stabilizing resistive region is included in a substrate between a base and an emitter to stabilize the withstanding voltage of the semiconductor device, and a supplemental resistor for functioning as an emitter ballast resistor is forced so as to be added to the stabilizing resistive region simultaneously with the formation of the emitter ballast resistors so as to weaken the parasitic transistor operation of the stabilizing resistive region to prevent the reduction in the area of safe operation of the semiconductor device. Further, a stabilizing resistor to be connected between the base and the emitter may be alternatively formed on the substrate in the same manner as the emitter ballast resistors so that no parasitic transistor effects are generated to enable only the transistor units, each having the area of safe operation expanded by the function of the emitter ballast resistor, to operate in the resultant semiconductor device. Thus, it is possible to obtain a semiconductor device having an expanded region of safe operation.
To achieve the objects and in accordance with the purpose of the invention, as embodied and broadly described herein, the semiconductor device of this invention comprises a plurality of transistor units each including an emitter contact, a base contact, and a collector contact formed in a common substrate, a plurality of emitter ballast resistors each coupled to a corresponding emitter contact of each of the plurality of transistor units, a stabilizing resistive region located in the substrate between a selected base contact and a lead-out electrode, the stabilizing resistive region having the same conductivity type as the selected emitter region, an emitter electrode coupled to the corresponding emitter contact through the respective emitter ballast resistor, and a supplemental resistor located between a selected emitter electrode and the lead-out electrode for coupling the selected emitter electrode to the lead-out electrode and for reducing parasitic transistor effects in the stabilizing resistive region.
In another aspect of the invention, the semiconductor device comprises a plurality of transistor units each including an emitter contact, a base contact, and a collector contact formed in a common substrate, a plurality of emitter ballast resistors, each is coupled to a corresponding emitter contact of each of the plurality of transistor units, an emitter electrode is coupled to the corresponding emitter contact through the respective emitter ballast resistor, and a stabilizing resistor is located between a selected emitter electrode and a selected base contact, the emitter ballast resistor and the stabilizing resistor are formed from the same material.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the principles of the invention.
Other features and advantages of the present invention will be apparent from the following description taken in connection with the accompanying drawings, wherein:
FIG. 1 is an equivalent circuit of a conventional semiconductor device.
FIG. 2 is a cross-sectional view of a conventional semiconductor device;
FIG. 3 is a cross-sectional view of an embodiment of the semiconductor device according to the present invention; and
FIG. 4 is a cross-sectional view of another embodiment of the semiconductor device according to the present invention.
Embodiments of the semiconductor device according to the present invention will be described with reference to the drawings.
FIG. 3 shows a cross-sectional view of an embodiment of the semiconductor device according to the present invention where like reference numerals refer to like parts in FIGS. 2, 3 and 4. An N-type collector region 2, a P-type base region 3 and an N-type emitter region 4 are successively formed in a substrate 1, and then the substrate 1 is covered with an insulating film 5. Base electrodes 6 are formed so as to contact with the base region 3 through the holes of the insulating film 5. The base electrodes 6 of the respective transistor units are connected in parallel to each other, and a base terminal B is led out from the common connection.
An elongated N-type stabilizing resistive region 10 of the same conductive type as emitter region 4 is formed in the surface of the base region 3. Insulating film 5 is removed to expose both ends 11 and 12 of stabilizing resistive region 10 so as to get respective contacts of base electrode 6 with end 11 of region 10 and a lead-out electrode 13 with end 12 of region 10. Lead-out electrode 13 also contacts with a supplemental resistor 14 formed on insulating film 5. Thus, a stabilizing resistor made of the N-type stabilizing resistive region 10 and the supplemental resistor 14 are inserted between a base and an emitter.
Supplemental resistor 14 may be formed simultaneously with the emitter ballast resistor 8 by using the same material.
Preferably, the resistance value of the emitter ballast resistor 8 is selected to be about 10 ohms, the resistance value of the N-type stabilizing resistive region 10 is selected to be about 100 ohms, and the resistance value of the supplemental resistor 14 is selected to be greater than or equal to that of emitter ballast resistor 8.
FIG. 4 shows a cross-sectional view of another embodiment of the semiconductor device according to the present invention. An N-type collector region 2, a P-type base region 3, and an N-type emitter region 4 are successively formed in a substrate 1, and then substrate 1 is covered with an insulating film 5. Base electrodes 6 are formed so as to contact with the base region 3 through the holes of the insulating film 5. The respective base electrodes 6 of the transistor units are connected in parallel to each other, and a base terminal B is lead out from the common connection. Emitter contact electrodes 7 are formed so as to contact with emitter region 4 through the holes of the insulating film 5. Emitter ballast resistors 8 of polycrystalline silicon film are provided on insulating film 5 so as to contact with the respective emitter contact electrodes 7, and emitter electrodes 9 are provided on insulating film 5 so as to contact with the respective emitter ballast resistors 8. Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is lead out from the common connection.
Further, a stabilizing resistor 20 of polycrystalline silicon film is formed on the insulating film between a base electrode 6 and an emitter electrode 9 so as to contact with the base electrode 6 and the emitter electrode 9. Stabilizing resistor 20 conditions as a base-to-emitter stabilizing resistor. Since the stabilizing resistor 20 may be formed simultaneously with the emitter ballast resistor 8, execution of an additional step is not necessary. Although the resistance value of the ballast resistor 8 is established to be about 10 ohms, base-to-emitter stabilizing resistor 20 can be designed to have a resistance value within a range of up to several hundred ohms by suitably selecting its length and width.
As has been described above, according to the present invention, a resistor is further inserted between a stabilizing resistive region embedded in a substrate and an emitter. The added resistor acts as an emitter ballast resistor which weakens a parasitic transistor function generated in the stabilizing resistive region between an emitter and a base, thereby making it possible to expand the area of safe operation of the semiconductor device and to prevent the semiconductor device from breaking down. The resistor can be formed simultaneously with the emitter ballast resistor by using the same material, without complicating the manufacturing process.
Further, according to the present invention, a stabilizing resistive region located between a base contact and an emitter electrode is formed by a resistive layer on a substrate, so that it is not necessary to form a stabilizing resistive region in the substrate and a parasitic transistor having a small area of safe operation is not formed in each transistor unit in parallel. Accordingly, the area of safe operation of the semiconductor device is not reduced. Moreover, the stabilizing resistive region can be formed simultaneously with emitter ballast resistors by using the same material and the same process, without complicating the manufacturing process.
Claims (3)
1. A semiconductor device, comprising:
a plurality of transistor units formed in a common substrate, each including an emitter contact connected to an emitter region, a base contact connected to a base region, and a collector contact connected to a collector region;
a plurality of emitter ballast resistors each coupled to a corresponding emitter contact of each of said plurality of transistor units;
a stabilizing resistive region located in said base region between a selected base contact and a selected emitter contact, said stabilizing resistive region having the same conductivity type as said emitter region;
a selected emitter electrode coupled to the corresponding selected emitter contact by a respective emitter ballast resistor;
a lead-out electrode coupled to said stabilizing resistive region; and
a supplemental resistor located between said selected emitter electrode and said lead-out electrode for coupling said selected emitter electrode to said lead-out electrode and for reducing parasitic transistor effects in said stabilizing resistive region.
2. A semiconductor device according to claim 1, wherein said supplemental resistor is a resistive layer formed on said substrate, and wherein said emitter ballast resistor and said supplemental resistor are formed from the same material.
3. A semiconductor device according to claim 2, wherein said material is polycrystalline silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/687,029 US5298785A (en) | 1987-05-15 | 1991-04-18 | Semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11822987A JPH071934B2 (en) | 1987-05-15 | 1987-05-15 | CATV repeater |
| JP62-118299 | 1987-05-15 | ||
| JP19692687A JPS6439769A (en) | 1987-08-06 | 1987-08-06 | Semiconductor device |
| JP62-196926 | 1998-08-06 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US19446788A Continuation | 1987-05-15 | 1988-05-12 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/687,029 Continuation US5298785A (en) | 1987-05-15 | 1991-04-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5053847A true US5053847A (en) | 1991-10-01 |
Family
ID=26456258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/600,172 Expired - Lifetime US5053847A (en) | 1987-05-15 | 1990-10-19 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5053847A (en) |
| FR (1) | FR2615326B1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298785A (en) * | 1987-05-15 | 1994-03-29 | Fuji Electric Co., Ltd. | Semiconductor device |
| US5311055A (en) * | 1991-11-22 | 1994-05-10 | The United States Of America As Represented By The Secretary Of The Navy | Trenched bipolar transistor structures |
| DE19532990C1 (en) * | 1995-09-07 | 1996-11-14 | Telefunken Microelectron | Integrated NPN transistor circuit for signal amplification in receiver input stage |
| US5654562A (en) * | 1995-03-03 | 1997-08-05 | Motorola, Inc. | Latch resistant insulated gate semiconductor device |
| US5907180A (en) * | 1994-11-03 | 1999-05-25 | Telefonaktiebolaget L.M. Ericsson | Ballast monitoring for radio frequency power transistors |
| US20060138597A1 (en) * | 2004-12-24 | 2006-06-29 | Johnson David A | Combined high reliability contact metal/ ballast resistor/ bypass capacitor structure for power transistors |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298785A (en) * | 1987-05-15 | 1994-03-29 | Fuji Electric Co., Ltd. | Semiconductor device |
| US5311055A (en) * | 1991-11-22 | 1994-05-10 | The United States Of America As Represented By The Secretary Of The Navy | Trenched bipolar transistor structures |
| US5907180A (en) * | 1994-11-03 | 1999-05-25 | Telefonaktiebolaget L.M. Ericsson | Ballast monitoring for radio frequency power transistors |
| US5654562A (en) * | 1995-03-03 | 1997-08-05 | Motorola, Inc. | Latch resistant insulated gate semiconductor device |
| DE19532990C1 (en) * | 1995-09-07 | 1996-11-14 | Telefunken Microelectron | Integrated NPN transistor circuit for signal amplification in receiver input stage |
| US20060138597A1 (en) * | 2004-12-24 | 2006-06-29 | Johnson David A | Combined high reliability contact metal/ ballast resistor/ bypass capacitor structure for power transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2615326B1 (en) | 1990-08-31 |
| FR2615326A1 (en) | 1988-11-18 |
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