JPS60196090A - Chrominance signal discriminator - Google Patents

Abstract

PURPOSE:To secure the correct result of discrimination of chrominance signals without effect due to a fact that the level of a marker M showing the type of a chrominance signal C becomes obscure temporarily or dropped out, by detecting the discordance of contents between a reference chrominance signal and an input chrominance signal in a prescribed number of horizontal synchronizing sections and then charging and controlling the contents of the reference chrominance signal so as to obtain the coincidence with said input chrominance signal. CONSTITUTION:As shown in the diagram, a chrominance signal discriminnating circuit 45 compares a reproduction/demodulation signal RVIN with a reference level signal VREF through a level comparator 51. When the change of a color latch output CRH caused every one H is not coincident with the change of the logic level of a chrominance discrimination output signal CD caused every one H, the output EQ of a coincidence deciding circuit 61 rises up to logic H. Thus a discordance cycle counter 63 is not cleared any more and starts counting horizontal synchronizing signals HD. Then the signal CD is delivered with repetitive inverting actions at a logic level different from the output CRH. In case the abnormality of the signal RVIN lasts over a prescribed section, the contents of the signal CD are immediately inverted. Thus it is possible to obtain the signal CD showing the signal RVIN.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a color signal discrimination circuit, and is suitable for application to, for example, a video tape recorder (VTI) signal processing device.

[Background technology and its problems]

Conventionally, a VTR uses a video signal VIDE as shown in Figure 2.
Some devices use O for recording and reproduction. Video signal VI
DI! 0 is the color signal C which is time-axis compressed to 175 and the luminance signal Ytc which is time-axis compressed to 415 for each horizontal synchronization signal H.
It has a sequentially arranged configuration, and horizontal synchronization signal H and color signal C
A marker M indicating the type of color signal is inserted between the two. Here, the content of the color signal C of the video signal VIDEO has a signal format in which the color difference signal +1-Y or B4' is alternately switched for each IH (this is called a line order method), and the type of this color signal is To represent this, marker M has a signal level of 50 (IRE) when color signal C is color difference signal RY, and 0 (IRE) when color signal C is color difference signal B-Y.
It is set to have a signal level of .

However, since the insertion position of this marker M is selected during a relatively narrow time interval between the horizontal synchronization signal H and the color signal C, it is difficult to determine the signal level of the marker M from the transmitted video signal VIDEO. There is a risk of incorrect determination. For example, from the falling point of the horizontal synchronizing signal H, the marker M
The time TA until the start point is selected to be 3 (μs), and the time TB until the end point is selected to be about 4 [μ3]. In this way, the time interval at which the marker M is actually inserted is 1 [μs], which is quite narrow, so the video signal VI
If the characteristics of the transmission system that transmits DEO are poor, and the rising waveform of marker M becomes dull, the insertion time TB of marker M
~The signal level at TA may become unclear, leading to erroneous color signal discrimination.

In addition to this, especially VTI? In this case, the video signal VIDI
When playing back EO, it is inevitable to avoid signal dropouts, jitter, etc. Therefore, this short time interval marker M inserted in the playback video signal is set based on the horizontal synchronization signal. If the signal level of a color signal is determined based only on the time interval, there is a greater possibility that an image with correct colors cannot be reproduced.

For example, if we consider the case where the signal level of marker M is determined every time the horizontal synchronization signal H arrives, if the marker M is determined incorrectly, the color of the screen reproduced by controlling the color accordingly will be incorrect each time. color, and eventually the color control circuit controls the incoming video signal VID[! Even if it is working correctly to reproduce the color that matches the color signal of O, this is
This can lead to confusion.

One way to reduce this possibility is to perform marker M discrimination at predetermined intervals instead of every IH. Therefore, if the color change discrimination operation is incorrect, the incorrect state will continue for a relatively long time, and the color control function of the video signal processing device is still insufficient.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and is based on the color signal C.
To obtain a color signal discrimination device which can obtain correct discrimination results without being affected even when the level of a marker M representing the type of color temporarily becomes unclear or drops out. This is what I am trying to do.

[Summary of the invention]

In order to achieve such an object, in the present invention, an input color signal representing the type of color signal included in the video signal to be processed is formed, and a logic level is changed in response to a horizontal synchronization signal synchronized with the video signal to be processed. A reference color signal that changes alternately is generated, and when the content of the reference color signal and the content of the input color signal do not match for a predetermined number of horizontal synchronization intervals, this is detected and the content of the reference color signal is adjusted so as to match the content. Make changes controlled.

(Example) An embodiment of the present invention will be described in detail below with reference to the drawings.

The luminance signal Y is separated in a luminance signal/chrominance signal separation circuit 1, converted into a digital signal in an analog-to-digital conversion circuit 2, and then supplied to a time axis compression circuit 3.

The time axis compression circuit 3 is composed of a digital memory, and the frequency of its write clock WY is set to a relatively low frequency (16 (
MHz)) and the frequency of the read clock RY to be a high frequency (20 (Mb)), the time axis of the luminance signal Y is compressed to 475, and the synthesis circuit 4
give to.

Further, the color signal C separated in the luminance signal/color signal separation circuit 1 is decoded in the decoder 5 to produce a color difference signal W.
-Y and B-Y are generated and applied to analog-digital conversion circuits 6 and 7, converted into digital signals, and then applied to time axis compression circuits 8 and 9.

The time axis compression circuits 8 and 9 operate at a relatively low frequency (4 (Ml
lz) ) successive clocks -(RY) and -(B-Y
) performs a write operation, and a relatively high frequency (
The readout operation is performed by successive clock signals R(R-Y) and R(B-Y) of 20 (MHz)), and thus the color difference signals R-Y and B-Y are compressed into 115 time axes and sent to the synthesis circuit 4. Send to.

These write clock signals MY, Wf)l-Y'),
bit-Y) and read clock signal RY, R(RY),
m-Y) is a synchronization separation circuit 10 from the input video signal VIN.
A clock generating circuit 11 receives a horizontal synchronizing signal HD and a vertical synchronizing signal VD separated in the clock generating circuit 11.

The combined output thus obtained at the output end of the combining circuit 4 is converted into an analog signal in the digital-to-analog conversion circuit 12, and then FM modulated in the FM modulation circuit 13.
The signal is recorded on the tape 16 via the reproduction amplification circuit 14 and the recording head 15.

The playback yarn PB receives the video signal recorded on the tape 16 via the playback head 21 to the FM demodulation circuit 22, and the demodulated output RνIN is sent to the low-pass filter 23 and the analog-to-digital conversion circuit 24 to convert the brightness of the digital memory configuration. It is applied to the signal time axis expansion circuit 25 and the time axis expansion circuits 26 and 27 for the RY and BY signals.

The time axis expansion circuits 25, 26, and 27 each have 20 (M
Write clock signal -vP, W consisting of pulses of Hz)
(RY)P, W(B-Y)P is given, while the read o'7 signal RYP 5R(RY)P,
16 (MHz) as R(B-Y)P, respectively.
4 (MHz) and 4 (MHz) clock pulses are given. Thus, the time axis expansion circuit 25.26.27
The luminance signal Y, color difference signals R-Y and B-Y contained in the reproduced signal are respectively expanded in time by 574 times, 5 times, and 5 times to obtain component signals, which are sent to the digital-to-analog conversion circuit 28. 29. After converting to analog signal in 30, low pass filter 31.32.3
3 to a synthesizing circuit 34, and the synthesized output is sent out as a video playback output RVOLIT.

Write clock correction P , W(RY)P , W(B-Y)P and read clock RYP , R(RY)P , R(B-
Y) P is the synchronization signal separation circuit 4 from the reproduction demodulation output RVIN
It is generated in a reproduction control circuit 42 which receives the horizontal synchronization signal HD, vertical synchronization signal VD, and composite synchronization signal C5 separated at 1.

The reproduction control circuit 42 is configured to operate the corresponding time axis expansion circuit 26 or 27 depending on whether the color difference signal currently being sent out as the reproduction demodulated video signal RVIN is R-Y or B-Y. Therefore, the color signal discrimination circuit 45
The 0 color signal discrimination circuit 45, which is provided with a 0 color signal discriminating circuit 45, receives the horizontal synchronizing signal HD sent from the synchronizing signal separating circuit 41, and determines the time period TA- during which the marker M is inserted from the falling point of the horizontal synchronizing signal HD.
By determining the signal level of the reproduced demodulated video signal RVIN at TB (FIG. 2), the color difference signal included in the currently arriving reproduced demodulated video signal RVIN is determined as R-Y.
or B-Y, and sends a color discrimination output signal CD representing the judgment result to the reproduction control circuit 42.

As shown in FIG. 1, the color signal discrimination circuit 45 converts the reproduced recovered video signal RVIN (FIG. 5(A)) into a level comparison circuit 5.
1, it is compared with the reference level signal VREF-.

This reference level signal VRI! As shown in FIG. 2, if F is level 50 (I
RE ) and 0 indicating that marker M is BY.
(IRE), and thereby the signal level of the reproduced demodulated video signal RVIN is set to the reference level V
When it becomes lower than REF (indicating that the color signal is B-Y), it becomes logic rLJ, and conversely, the level of the reproduced demodulated video signal RVIN becomes the reference level signal VRI! When the signal level becomes higher than F (meaning that the color signal is RY), a comparison output RE that becomes logic "H" is sent to the latch circuit 52.

The latch circuit 52 is a D flip-flop circuit, and when the color discrimination clock signal CCL (FIG. 5(C)) sent from the color discrimination clock signal generation circuit 53 rises to logic rHJ, the comparison output R[! 0 color discrimination clock signal generation circuit 53c which latches the logic level of fJ
Horizontal synchronization signal H rising in synchronization with horizontal synchronization signal H included in ElN video signal RVIN (Fig. 5 (A))
D (Fig. 5(B)) consists of a mono-multi pipe rake, whose time limit is set by the marker M (Fig. 5(B)).
2) is selected as the time TC between the generation times TA and TB, and the output signal that rises to the logic rHJ at the elapsed time point of the time limit TC is sent out as the color discrimination clock signal CCL, and as a result, the latch circuit 52 outputs the current The color signal is logical rHJ or rL depending on whether it is R-Y or B-Y.
The color latch output CRH (FIG. 5(D)) which becomes J is sent out.

In this way, the level comparison circuit 51, the latch circuit 52,
A color signal input circuit 54 is formed by the color discrimination clock signal generation circuit 53, and the color latch output CRH is sent to the coincidence determination circuit 61 as a signal representing the content of the color signal of the currently arriving reproduced demodulated video signal RVIN. Ru. ' The coincidence judgment circuit 61 is composed of an exclusive OR circuit, and when the content of the output RCR of the reference color signal generation circuit 62 matches the color latch output CRH, the logic rLJ is obtained. G)) is given as a clear signal to the mismatch period counter 63, which is a 4-bit counter, for example.

The mismatch period counter 63 receives the horizontal synchronization signal HD as a clock input, and the logic level of the clear signal EQ is rHJ.
When the horizontal synchronization signal HD rises, a count operation is performed, and when the count reaches, for example, 8 (decimal number), the mismatch detection output NEQ (5th
(F)) is applied to the inversion control circuit 64.

The inversion control circuit 64 is constituted by an exclusive OR circuit, and provides an inversion command signal REV to the reference color signal generation circuit 62 when the mismatch detection output NEQ becomes logic "H".

The reference color signal generation circuit 62 is composed of a 079717071 circuit, receives the color discrimination clock signal CCL as a clock signal, and reads the logic level of the inversion command signal REV.

Then, the reference color signal generation circuit 64 converts the Q output into the reference color signal R.
cR is given as a second input condition signal to the inversion control circuit 64, and the Q output is sent out as a color discrimination output signal CD.

In the above configuration, playback iKm video fW No. RVIN
The content of the O color signal C is alternately changed to a color difference signal B-Y or R-Y for each IH as shown in FIG. 5(A)! (This is called alternating.) Therefore, the signal level of the marker M inserted before the color signal C is 50 (IRE) when the color difference signal is 11-Y. Since it becomes 0 (IRE) when the color difference signal B-Y, the logic level of the comparison output RE becomes 11i'' or rLJ accordingly. ,
This logic level change is caused by the color discrimination clock signal -+Ct;t
, & are latched in the latch circuit 52 and therefore colored. The output CRH0)86 alternates the logic rHJ or "L" for each lH.

If the logic level of the color discrimination output signal CD given to the coincidence determination circuit 61 as the other condition signal matches the color latch output CRH that changes in this way, the coincidence output EQ falls to the logic rLJ, Because of this, the mismatch period counter 63 does not perform a counting operation, so the mismatch detection output NEQ maintains the logic rLJ state, which is applied to the inversion control circuit 64 as a non-inverting input.

At this time, the inversion control circuit 64 enters a state in which the reference color signal RCR obtained from the Q output terminal of the reference color signal generation circuit 62 is directly applied as the inversion command signal REV to the D input terminal. Therefore, when the reference color signal generation circuit 62 is in the set state and the reference color signal RCR is logic rLJ, this is fed back to the D input terminal as the inversion command signal REV, so that when the next color discrimination clock signal CCL is given. The reference color signal generation circuit 62 performs a reset operation and causes the Q output to rise to logic [1-IJ. At this time, the reference color signal RCR formed by the Q output is directly fed to the D input terminal as the inversion command signal REV, so the reference color signal generation circuit 624 also performs a set operation at the next rise of the color discrimination clock signal CCL. Then, the Q output falls to the logic rLJ again. Thereafter, in the same manner, the reference color signal generation circuit RCR is activated at the logic "H" level by the rising edge of the color discrimination clock signal CCL.
” or “L” is generated, which means that the content of the color discrimination output signal CD obtained from the Q output terminal of the reference color signal generation circuit 62 is the content that alternates the logic rLJ or rHJ. It means that.

In this way, in the state where the coincidence is detected in the coincidence determination circuit 61, the color discrimination output signal CD;
.

1. is a change in the logic level of the color latch output CRII and therefore
□, □ represent changes in the marker M of the raw demodulated video signal RVIN.

On the other hand, when the change in the color latch output CRH for each IH does not match the change in the logic level for each IH of the color discrimination output signal CD, the output HQ of the match determination circuit 61 rises to logic H, and the mismatch period is The counter 63 is no longer cleared and starts counting the horizontal synchronization signal HD.

However, during this counting operation, the content of the mismatch detection output NEQ maintains the logic "■," state, so the inversion control circuit 64 controls the reference color signal generation circuit 62 in the same way as in the above case. Since the reference color signal RCR is fed back as is as the inversion command signal REV, the color discrimination output signal CD repeats the inversion operation at a logic level different from the color latch output CRI (in other words, it is assumed that there is still an error). (with unjudged content) will be output.

In this state, if the content of the color latch output CRH returns to match the color identification output signal CD before the count content of the mismatch period counter 63 reaches a predetermined number, that is, 8, the output EO of the match determination circuit 61 becomes a logic [ I7], the content of the mismatch period counter 63 is cleared, and the content of the color discrimination output signal CD and the content of the color latch output CR)I are returned to the same state.

A state in which such an operation may occur is that the marker M of the reproduced fj[Ml video signal RVIN is affected by the characteristics of the transmission path and the waveform becomes dull, and the color discrimination clock signal CCL rises. When the contents of the comparison output RE at a point in time are temporarily incorrect, or when the comparison output RE temporarily does not correctly represent the contents of the marker M due to dropout. Conceivable.

However, there is little possibility that such a state will continue for a long period of time, and therefore, it is considered that the mismatch period counter 63 is cleared before reaching the upper limit count number of the mismatch period counter 63. At this time, color latch output Cl1H
has returned to the correct alternate state, so it matches the content of the color discrimination output signal CD. In this way, even if a partial abnormality occurs in the reproduced demodulated video signal RVIN, the color discrimination output signal CD is a correct color discrimination output signal C.
This means that it is possible to continue outputting D.

However, if the abnormality of the reproduced demodulated video signal RVIN continues for a long time, the count content of the mismatch period counter 63 will eventually exceed the maximum coefficient value, and at this time, the mismatch detection output N
hQ rises to logic rHJ.

' In this state, the inversion control circuit 64 outputs an inversion command signal 1? having the content inverted from the logic level of the reference color signal RCR arriving at the other input terminal. EV will be generated. To explain this state with reference to FIG. 5, the color discrimination clock signal generation circuit 53 is triggered by the rise of the horizontal synchronization signal 11D (FIG. 5 (B)) at time t1, and the color discrimination clock signal CCL becomes the logic rLj. Standing (Fig. 5 (C)), time L2 when the time limit TC has elapsed
When the clock signal CCL rises to logic 1" HJ, the latch circuit 52 performs a latch operation (fifth
(D)), the reference color signal generation circuit 62 performs an inversion operation (FIG. 51)). However, at time L1, when the mismatch period counter 63 counts up and the mismatch detection output NEC rises to logic H (FIG. 5(F)), the reference color signal RCR, which is in the logic "1," state at this time, is inverted. Then, the state is changed so that the inversion command signal REV of logic "1" is fed back to the D input terminal. Therefore, at time L2, the color discrimination clock signal CCL is at logic 1.
' Each time HJ rises, the reference color signal generation circuit 62
is controlled so that it cannot perform an inversion operation, and thus the content of the color discrimination output signal CD (FIG. 5(E)) maintains the logic level before I11.

On the other hand, in the IH section, the color latch output C
Since R11 performs an inverting operation, the color discrimination output signal CD
Since CRH does not perform an inversion operation, its logic level matches that of the color latch output CRH.

In this state, the mismatch period counter 63 is immediately cleared by the output EQ of the match determination circuit 61, so the inversion control circuit 64 again uses the reference color signal RCR as it is as the inversion command signal 1? The state returns to the state where it is sent out as an EV, and thereafter the reference color signal generation circuit 62 performs an alternating operation, so that the content of the color discrimination output signal CD returns to the state representing the same content as the color latch output CRH.

Therefore, according to the configuration of FIG. 1, the reproduced demodulated video signal RV
[If the abnormality of N does not exceed a predetermined length, the color discrimination output signal CO performs the same alternate operation as in the case where no abnormality occurs, thereby making it possible to obtain a more stable color discrimination output signal CD. If the abnormality of the reproduced demodulated video signal RVIN persists for more than the predetermined period, the color discrimination output signal CD representing the reproduced demodulated video signal RVIN can be obtained by immediately inverting the content of the color discrimination output signal CD. can.

[Effects of the Invention] As described above, according to the present invention, even if the reproduced demodulated video signal becomes temporarily abnormal, it is possible to continue to obtain a correct color discrimination output signal without being affected by it, and also If an abnormality larger than the length occurs, the color discrimination output signal can be immediately changed to follow, so the marker M waveform may be distorted or dropout may occur based on the characteristics of the transmission system, making it difficult to discriminate the marker M. Since there is no need to redo color control each time the color control is temporarily disabled, it is possible to realize a video signal processing device that can perform highly stable color control.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of the color signal discrimination device according to the present invention, FIG. 2 is a signal waveform diagram showing the signal format of a video signal, and FIGS. 3 and 4 are color signals shown in FIG. 1. FIG. 5 is a block diagram showing a recording system and a reproducing system of a VTR to which the discrimination device is applied. FIG. 5 is a signal waveform diagram showing signals of each part of FIG. 1. 45... Color signal discrimination circuit, 51... Level comparison circuit, 52... Latch circuit, 53... Color signal clock signal generation circuit, 54... Color signal input circuit, 61... Match determination Circuit, 62... Reference color signal generation circuit, 63...
- Discrepancy cycle counter. Agent Keiki Tanabe

Claims (1)

[Claims] A color signal input circuit that forms an input color signal representing the type of color signal included in the video signal to be processed, and a reference color whose logic level alternately changes in response to a horizontal synchronization signal synchronized with the video signal to be processed. a reference color signal generation circuit that generates a signal; and a reference color signal generating circuit that detects and matches when the content of the reference color signal and the content of the input color signal match during a predetermined number of horizontal synchronization intervals. A color signal discriminating device comprising: a coincidence control circuit that changes and controls the content of a reference color signal of a generating circuit.