JPS60196049A - Carrier recovery circuit - Google Patents

Abstract

PURPOSE:To improve the stability of working and also to attain satisfactory high frequency characteristics and linearity for a reproduction circuit for carrier wave, by performing the signal processing at a base with said reproduction circuit used for synchronous detection of PSK modulated wave and at the same time using a multiplier which keeps balance with use of double balance type phase detectors. CONSTITUTION:A 4-phase PSK modulated wave is supplied to an input terminal 12 and applied to phase detectors 13 and 14 for synchronous detection. An oscillation wave (carrier wave) for synchronous detection delivered from a voltage control oscillator 16 is applied directly to the detector 13. While said oscillation wave is applied to the detector 14 via a -pi/2 phase shifter 15. The synchronous detection outputs given from both detectors 13 and 14 undergo deletion of carrier components through LPF17 and 18. The double balance type phase detectors 19, 20, 22, 23, 26 and 28 perform multiplications respectively. The output signal of a subtractor 29 is supplied to the oscillator 16 as an error signal via a loop filter 30. Then a carrier wave equivalent to the carrier wave obtained before modulation of the input 4-phase PSK modulated wave is delivered synchronously from the oscillator 16. Thus the detectors 13 and 14 can perform the correct synchronous detection.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a carrier wave regeneration circuit, particularly a carrier wave regeneration circuit used in a demodulator of a wireless communication device using a four-phase PSK modulated wave. The present invention relates to a carrier regeneration circuit configured according to a method for performing signal processing.

(Conventional examples and problems) Wireless transmission systems that use PSK modulation have a larger amount of information per unit time than wireless transmission systems that use frequency modulation, so they transmit a lot of information within a certain bandwidth. It is known as an advantageous transmission method for transmission, and in recent years, for example, when transmitting audio signals in satellite broadcasting,
4-phase PS is a digital signal made by converting an audio signal into PCM.
It is also well known that the four-phase PSK modulation method is often used for wireless transmission of various information, such as when transmitting as a K modulated wave.

As a means of demodulating the above-mentioned four-phase PSK modulated wave, a synchronous detection method is usually adopted, which shows excellent characteristics in various aspects such as transmission efficiency, noise resistance, and interference resistance. Although a carrier wave is required for synchronous detection of waves, the carrier wave is suppressed in PSK modulated waves, so in order to perform synchronous detection of PSK modulated waves,
A carrier wave recovery circuit is required to recover the carrier wave from the PSK modulated wave.

The above-mentioned carrier wave regeneration circuit is an important circuit that greatly affects the demodulation characteristics of PSK modulated waves. Conventionally, carrier wave regeneration circuits have been implemented using methods that perform signal processing in the carrier band to regenerate the carrier wave. A carrier wave regeneration circuit configured according to a multiplication method, a re-modulation method, an inverse modulation method, etc., which belongs to
Carrier regeneration circuits configured according to various formats have been proposed, such as carrier wave regeneration circuits configured according to the loop method and a modified method of the Costas loop method, but the recent trend is that the integrated circuits of recent years Due to significant advances in technology, multipliers have become cheaper, and signal processing is performed in a lower frequency band. Carrier wave regeneration circuits configured according to the loop method or a modified version of the Costas loop method are increasingly being used.

By the way, carrier wave regeneration circuits configured according to the Costas loop method or a modified method of the Costas loop method, in which signal processing is performed in the low frequency baseband as described above, have a phase-locked loop as the basic structure. It is particularly important that each circuit making up the phase-locked loop has good operational stability.

However, although baseband signals occupy a frequency band of several 100 KHz to several megahertz, it is difficult to operate an analog multiplier with good linearity stably in a frequency band of several megahertz. Traditionally, a double-balanced phase detector has often been used instead of an analog multiplier to perform multiplication operations, but double-balanced phase detectors also perform multiplication operations with good linearity. In addition to problems such as the output DC level fluctuating due to temperature fluctuations, it has become a problem that double-balanced phase detectors have a negative effect on the stability of phase-locked loop operation. It had become.

(Means for Solving the Problems) The present invention is a carrier wave regeneration circuit for regenerating a carrier wave used in synchronous detection of a 4-phase PSK modulated wave. means for supplying the PSK modulated wave to a first phase detector and a second phase detector to obtain respective J'L detection output signals from each phase detector; a first input terminal configured such that a detection output signal from the detector is supplied to a first input terminal;
The second input terminal of the double balanced phase detector is connected to the second input terminal of the double balanced phase detector.
of the first two phase detectors by supplying the detection output signal from the phase detector of
Means for obtaining a first multiplication output signal from the double-balanced phase detector and a signal obtained by inverting the phase of the detected output signal from the second phase detector are supplied to the first input terminal. The detection output signal from the first phase detector is supplied to the second input terminal of the second double-balanced phase detector, which is connected to the second double-balanced phase detector. means for obtaining a second multiplication output signal; means for supplying the first multiplication signal and the second multiplication signal to a first subtraction circuit to obtain a first subtraction signal; a first squared output signal from a third double-balanced phase detector configured such that the detected output signal from the phase detector is supplied to the first input terminal and the second input terminal; a means for obtaining the detected output signal from the first phase detector;
a fourth input terminal configured to be supplied to the input terminal of
means for obtaining a second squared output signal from the double-balanced phase detector;
means to obtain a second subtraction signal by supplying the second subtraction signal to the subtraction circuit; and a fifth double-balanced phase detector whose first input terminal is supplied with the second subtraction signal. means for supplying the above-mentioned first subtraction signal to the second input terminal to obtain a third multiplication signal; means for supplying a signal obtained by inverting the phase of the first subtraction signal to a second input terminal of the double-balanced phase detector to obtain a fourth multiplication signal; means for supplying the multiplication signal and the fourth multiplication signal to a third subtraction circuit to obtain an error output signal from the third subtraction circuit; and means for supplying the error output signal through a loop filter. means for outputting a carrier wave for coherent detection from a voltage controlled oscillator whose oscillation frequency is controlled by The present invention provides a carrier wave regenerating circuit which constitutes a phase locked loop with means for supplying a carrier wave to the above-mentioned second phase detector via a 90 degree phase shift circuit.

(Example) Hereinafter, specific contents of the carrier wave regeneration circuit of the present invention will be explained in detail with reference to the accompanying drawings of FIGS. 1 to 3. FIG. 1 is a block diagram for explaining the configuration principle of the carrier wave recovery circuit of the present invention, FIG. 2 is a block diagram of an embodiment of the carrier wave recovery circuit of the present invention, and FIG. 3 is for explaining the operation. FIG.

First, the principle of construction of the carrier wave recovery circuit of the present invention will be explained with reference to FIG. Now, to explain 4-phase PSK modulation using the case of Japanese satellite broadcasting as an example, in this case, binary data using play codes is converted into 2
By processing in series, the change period of data is as follows:
0 for (0,0), π/2 for (0,1)
, π for (1,1), 3π for (1,0)
/2.

The four phases P generated according to the phase change period as described above
The SK modulated wave is in a state where its carrier wave is suppressed, but if the phase change in the 4-phase PSK modulation can be canceled out by Kashi's method, the 4-phase PSK modulation wave can be suppressed.
It is possible to reproduce the carrier wave corresponding to the carrier wave before modulation from the carrier wave suppressed in the SK modulated wave, and in the carrier wave regeneration circuit of the present invention, by multiplying the penis band signal by 4, it is possible to reproduce the carrier wave corresponding to the carrier wave before modulation. The phase change of π/2 in the modulated wave becomes a phase change of 2π by multiplying by 4, and the phase change of π in the 4-phase PSK modulated wave becomes a phase change of (2π×2) by multiplying by 4. , the phase change of 3π/2 in the 4-phase PSK modulated wave is 4
Focusing on the fact that multiplication results in a -phase change of (2π x 3), which can cancel out one phase change in the 4-phase PSK modulated wave, synchronous regeneration of the carrier wave from the 4-phase PSK modulated wave can be performed. The block diagram of FIG. 1 shows a carrier recovery circuit constructed in accordance with the construction principle described above.

In Fig. 1, 1 is an input terminal, 2 and 3 are phase detectors,
4 is a π/2 phase shifter, 5 is a voltage controlled oscillator, 6.7 is a low-pass filter for removing carrier wave components, 8 to 10 are analog multipliers, and 11 is a loop filter.

Now, the 4-phase PS as the input signal supplied to input terminal 1
The K modulated wave is A2cos(ωt+φ), and the output oscillation wave of the voltage controlled oscillator 5 is Alcosωt (φ is the phase change in the 4-phase PSK modulated wave, 0°π/2.π,
3π/2), the output of the low-pass filter 6 is (Al・A2cos φ)/2, and
The output of the low-pass filter 7 is (A I・A 2
sin φ)/2 is obtained.

In the following explanation, for the sake of simplicity, the amplitude A
The description is omitted by omitting the display of I and A2 and focusing only on the change in phase.

In the analog multiplier 8, the output signal from the low-pass filter 6 (A 1 · A 2 cos φ)/2 and the output signal from the low-pass filter 7 (AI · A25in φ) /
2 and their output signal sin 2
φ is applied to the analog multiplier lo, and in the analog multiplier 9, the output (A 1
・Output signal -co which is A2 sin φ)/2 squared
s2φ is supplied to an analog multiplier 1o.

The analog multiplier 1o multiplies the two signals 5in2φ and -cos2φ supplied thereto, and then outputs a signal of -5in4φ.

The signal -5in4φ output from the analog multiplier 1o as described above is the 4-phase PSK signal supplied to the input terminal 1.
This is a state in which the phase change of the modulated wave is canceled out, and it corresponds to the phase error component detected by synchronous detection in phase detector 2 and phase detector 3 and the amplitude of the demodulated baseband signal. It is composed of components.

Since the output signal consisting of the above-mentioned components output from the analog multiplier 1o is supplied to the voltage-controlled oscillator 5 via the loop filter 11, only the above-mentioned phase error component is sent to the voltage-controlled oscillator 5. The oscillation frequency of the voltage controlled oscillator 5 is controlled by the voltage controlled oscillator 5. The oscillation wave of the voltage-controlled oscillator 5 is directly reflected in the phase detector 2, and the oscillation wave of the voltage-controlled oscillator 5 is supplied to the phase detector 3 via the -π/2 phase shifter 4. .

The feedback loop in the carrier wave recovery circuit shown in the first diagram having the above-mentioned configuration is a phase-locked loop itself, and may be considered to correspond to a modification of the well-known Costas loop.

By the way, in the carrier wave regeneration circuit shown in FIG. 1 used to explain the operating principle of the present invention described above, analog multipliers 8 to 10 are used for signal processing.
Analog multipliers are not suitable for use in high frequency bands due to limitations in frequency characteristics, so in reality analog multipliers 8
~10 is replaced by a double-balanced phase detector with good high-frequency characteristics that performs the multiplication operation, and the double-balanced phase detector has problems with linearity. The details are as described above.

Therefore, the carrier wave regeneration circuit of the present invention follows the configuration principle as already described with reference to FIG. The purpose of the present invention is to provide a carrier wave regeneration circuit which can obtain very good linearity even if the configuration is such that the carrier wave regeneration circuit according to the present invention is configured to perform a carrier wave regeneration circuit. The specific contents of the carrier wave regeneration circuit of the present invention will be explained in detail with reference to the waveform diagram (operational output waveform diagram) shown in FIG.

The waveform diagrams (operating output waveform diagrams) shown in FIG. 3 (a) to (k) are shown to facilitate understanding of the circuit operation of each component in the carrier wave regeneration circuit shown in FIG. For example, the waveform shown in FIG. 3(a) is the operating output waveform with a phase of cosφ from the low-pass filter 6 in FIG. 1, which was explained with reference to FIG. The same operating output waveform is indicated by the symbol a on the output side of the low-pass filter 17 in FIG.
The waveform obtained at point a shown in FIG. 3 and shown in FIG. The same operating output waveform as the output waveform is obtained at point b already indicated by the symbol on the output side of the low-pass filter 18 in FIG.
......Each waveform shown in (k) is
In the circuit arrangement after the output side of the low-pass filters 17 and 18 in FIG. 2, signal processing according to the operating principle as already described in FIG. The operating output waveform of the above-mentioned phase of cosφ on each output side of the low-pass filter 17 and 18 and sinφ
The operating output waveform of the phase is indicated by the symbol c ” k in FIG.
At each point shown in Fig. 3, (C)...
. . . This diagram illustrates and explains how the operational output waveform changes as shown in (k). Note that, in reality, the phase detectors 13 and 14 output demodulated outputs of digital data.

Now, in FIG. 2, 12 is an input terminal, and a 4-phase PSK modulated wave is supplied to this input terminal 12.

The four-phase PSK modulated wave is then given to phase detectors 13 and 14 for synchronous detection.
The oscillation wave (carrier wave) for synchronous detection oscillated by the voltage controlled oscillator 16 is directly applied to the phase detector 14, and the synchronous detection wave oscillated by the voltage controlled oscillator 16 is directly applied to the phase detector 14. Since the oscillation wave (carrier wave) for detection is provided via the -π/2 phase shifter 15, the phase detectors 13 and 14 described above each perform a synchronous detection operation.
Individual synchronous detection outputs are sent out from the phase detectors 13 and 14, respectively.

Then, the coherent detection output sent from the phase detector 13 described above is given to the low-pass filter 17, whereby the carrier component in the coherent detection output is removed. (a) of FIG. 3 is the operational output waveform of the portion a in FIG. 2. In addition, the synchronous detection signal sent out from the phase detector 14 described above -
The output is given to a low-pass filter 18, whereby the carrier component in the coherent detection output is removed. FIG. 3(b) is the operational output waveform of the portion b in FIG. 2.

19, 20, 22, 23, 26, 28 in Figure 2
is a double balanced phase detector, and each of the two shown in the figure
Double balanced phase detector 19, 20, 22, 23, 26.2
8, X is the first input terminal and Y is the second input terminal.

The signal output from the low-pass filter 17 described above is 2
The second input terminal Y of the double balanced phase detector 22, the first input terminal X of the double balanced phase detector 19, and the first input terminal Y of the double balanced phase detector 23. The signal output from the low-pass filter 18 is supplied to the second input terminals X and Y of the double-balanced phase detector 20. The signal is applied to the second input terminals X, Y and the second input terminal Y of the double-balanced phase detector 19, and the signal output from the low-pass filter 18 is sent to the inverting amplifier 21.
via the first input terminal X of the double balanced phase detector 22
is also supplied.

Therefore, in the double balanced phase detector 19 described above, the signal output from the low-pass filter 17 and the signal output from the low-pass filter 18 are multiplied, and the resulting output signal is is given to the subtractor 24 as the minuend signal. FIG. 3(c) shows the operational output waveform of the double balanced phase detector 19.

The output signal of the double-balanced phase detector 22 is supplied to the subtracter 24 as a subtraction signal, but the signal output from the double-balanced phase detector 22 is a double-balanced phase detector. It is obtained by multiplying the two signals supplied to the first input terminal X and the second input terminal Y of the detector 22 as described above by the double balanced phase detector 22. be.

FIG. 3(d) shows the operational output waveform of the double balanced phase detector 22. In FIG.

The subtracter 24 subtracts the output signal of the double balanced phase detector 22 from the output signal of the double balanced phase detector 19 to output a vertically symmetrical signal. FIG. 3(e) shows the operation output waveform of the subtracter 24.

Further, the above-mentioned double-balanced phase detector 20 has its first . Since the signal output from the low-pass filter 18 is supplied to the second input terminals X and Y, the double-balanced phase detector 20 receives the signal output from the low-pass filter 18. A signal obtained by squaring is output, and the signal is given to the subtracter 25 as a subtracted signal. (f
) is the operating output waveform of the double balanced phase detector 20.

The double balanced phase detector 23 has its first . Since the signal output from the low-pass filter ■7 is supplied to the second input terminals X and Y, the double-balanced phase detector 2
3 outputs a signal obtained by squaring the signal output from the low-pass filter 17, and this signal is given to the subtracter 25 as a subtraction signal.

The subtracter 25 subtracts the output signal of the double balanced phase detector 23 from the output signal of the double balanced phase detector 20 to output a vertically symmetrical signal. 3(g) shows the operating output waveform of the double balanced phase detector 23, and FIG. 3(11) shows the operating output waveform of the subtracter 25.

The output signal of the subtracter 24 is given to the input terminal Y of the double balanced phase detector 26 and also given to the inverting amplifier 27, and the output signal of the above-mentioned inverting amplifier 27 is given to the input terminal Y of the double balanced phase detector 26. It is supplied to the input terminal Y of the device 28.

Further, the output signal of the subtracter 25 is transmitted to the input terminal X of the double balanced phase detector 26 and the double balanced phase detector 28 described above.
is supplied to the input terminal X of. The two double-balanced phase detectors 26 and 28 described above perform a multiplication operation on the double sign supplied to their respective input terminals X and Y. The multiplication output signal is given to the subtracter 29 as its minuend signal, and the multiplication output signal from the double balanced phase detector 28 is given to the subtracter 29 as its subtrahend signal.

The subtraction output signal output from the subtracter 29 described above has a repetition frequency that is four times the frequency of the signal output from the low-pass filter 17 and the signal output from the low-pass filter 18. At the same time, the phase change corresponding to the modulation signal in the four-phase PSK modulated wave supplied to the input terminal 12 is canceled.

(i) in FIG. 3 shows the operating output waveform of the double balanced phase detector 26, and (j) in FIG. 3 shows the operating output waveform of the double balanced phase detector 28. (k
) shows the operation output waveform of the subtracter 29.

The output signal of the subtracter 29 is supplied as an error signal to the voltage controlled oscillator 16 via the loop filter 30, but the error signal supplied to the voltage controlled oscillator 16 is only an error component within the -circulating loop. Therefore, a carrier wave equivalent to the carrier wave before modulation of the input 4-phase PSK modulated wave is outputted from the voltage controlled oscillator 16 in synchronization with the phase detector for synchronous detection] 3.14 Then correct synchronous detection will be performed.

(Effects) As is clear from the detailed explanation above, the carrier regeneration circuit of the present invention has four
means for supplying the phase PSK modulated wave to the first phase detector 13 and the second phase detector 14 to obtain respective detected output signals from the respective phase detectors 13 and 14;
A second input terminal Y of the first double-balanced phase detector 19 is configured such that the detection output signal from the first phase detector 13 described above is supplied to the first input terminal X. means for supplying the detection output signal from the second phase detector 14 described above to obtain a first multiplication signal from the first double balanced phase detector 19; and the second phase detector 14 described above. A signal obtained by inverting the phase of the detection output signal from the first input terminal
The detection output signal from the first phase detector 13 described above is supplied to the second input terminal Y of the second double-balanced phase detector 22, which is configured to be supplied to the second double-balanced phase detector 22. means for obtaining a second multiplication signal from the double-balanced phase detector 22; means for obtaining a calculation signal;
From the third double-balanced phase detector 20, the detection output signal from the second phase detector 14 described above is supplied to the first input terminal X and the second input terminal Y. A detection output signal from the first phase detector 13 is connected to the first input terminal X and the second input terminal X.
means for obtaining a second squared signal from the fourth double-balanced phase detector 23, which is supplied to the input terminal Y of the first squared signal and the second squared signal. means for supplying the multiplication signal to the second subtraction circuit 25 to obtain a second subtraction signal; means for supplying the first subtraction signal to a second input terminal Y of the double-balanced phase detector 2G to obtain a third multiplication signal; A signal obtained by inverting the phase of the first subtraction signal described above is supplied to the second input terminal Y of the sixth double-balanced phase detector 28, which is supplied to the terminal X. 4 multiplication signal; and means for supplying the third multiplication signal and the fourth multiplication signal to the third subtraction circuit 29 to obtain an error output signal from the third subtraction circuit 29. and a means for outputting a carrier wave for synchronous detection from the voltage controlled oscillator 16 whose oscillation frequency is controlled by supplying the above-mentioned error output signal via the loop filter 30; The first phase detector 1 described above
3 and a means for supplying a carrier wave for coherent detection to the above-mentioned second phase detector 14 via a 90 degree phase shift circuit 15, forming a phase locked loop. Since the carrier wave regeneration circuit of the present invention performs signal processing in the baseband, the frequency handled is lower than that in the case where signal processing is performed in the carrier band, and therefore it is easy to increase the stability of operation. It is also ideal for integrated circuits.

Furthermore, since a double-balanced phase detector is used instead of an analog multiplier, no problems arise when used in high frequency bands. Furthermore, the double-balanced phase detector has poor linearity compared to the original analog multiplier.
In the carrier wave regeneration circuit of the present invention, by using a configuration in which two double-balanced phase detectors are used and balanced, the asymmetry of the operating waveform can be greatly improved, and as a result, It is possible to easily construct a carrier recovery circuit that can perform high-performance operations equivalent to those using analog multipliers with good linearity.

In addition, in the carrier wave regeneration circuit of the present invention, the problem of DC drift caused by temperature changes in the double-balanced phase detector can be greatly improved by the cancellation effect by subtraction, and this can also be solved by integrated circuits. In this way, an integrated circuit capable of highly stable operation can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration principle of the carrier wave recovery circuit of the present invention, FIG. 2 is a block diagram of an embodiment of the carrier wave recovery circuit of the present invention, and FIG. 3 is a waveform diagram for explaining the operation. be. 1.12...4-phase PSK modulated wave input terminal, 2, 3
．． 13゜14...Phase detector for synchronous detection, 4,15
...90 degree phase shifter, 6, 7, 17, 1B...Low pass filter, 8-10...Analog multiplier, 11.
30... Loop filter, 5, 16... Voltage controlled oscillator, 19, 20, 22, 23, 26, 2B... Double balanced phase detector, 21... Inverting amplifier, 24, 2
5.29...Subtractor, Figure 1 Figure 2

Claims (1)

[Claims] A carrier wave regeneration circuit for regenerating a carrier wave used in synchronous detection of a 4-phase PSK modulated wave, the 4-phase PSK modulated wave to be subjected to synchronous detection is means to obtain a detection output signal from each of the phase detectors, and a detection output signal from the first phase detector is supplied to a first input terminal. The detection output signal from the second phase detector described above is supplied to the second input terminal of the first double-balanced phase detector, which is configured as follows. means for obtaining a first multiplied signal from the detector; and a second means for obtaining a first multiplied signal from the above-mentioned second phase detector, the signal having the phase inverted of the detected output signal from the second phase detector being supplied to the first input terminal. The detection output signal from the first phase detector is supplied to the second input terminal of the double balanced phase detector, and the second multiplication signal is output from the second double balanced phase detector. means for obtaining the first subtraction signal by supplying the first multiplication signal and the second multiplication signal to the first subtraction circuit; means for obtaining a first squared signal from a third double balanced phase detector, the detection output signal being supplied to the first input terminal and the second input terminal; The detected output signal from the first phase detector is supplied to the first input terminal and the second input terminal. means for obtaining a signal;
means for supplying the multiplied signal and the second squared signal to a second subtraction circuit to obtain a second subtraction signal; the second subtraction signal is supplied to a first input terminal; means for obtaining a third multiplication signal by supplying the first subtraction signal to a second input terminal of a fifth double-balanced phase detector; A signal obtained by inverting the phase of the first subtraction signal is supplied to the second input terminal of the sixth double-balanced phase detector, which is supplied to the first input terminal. means for obtaining a multiplication signal of 4; supplying the third multiplication signal and the fourth multiplication signal to a third subtraction circuit;
means for obtaining an error output signal from a subtraction circuit; and means for outputting a carrier wave for synchronous detection from a voltage controlled oscillator whose oscillation frequency is controlled by supplying the error output signal through a loop filter. , means for supplying the carrier wave for coherent detection to the first phase detector, and supplying the carrier wave for coherent detection to the second phase detector via a 90 degree phase shift circuit; A carrier wave regeneration circuit that configures a phase-locked loop by