JPS60195980A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS60195980A JPS60195980A JP59050936A JP5093684A JPS60195980A JP S60195980 A JPS60195980 A JP S60195980A JP 59050936 A JP59050936 A JP 59050936A JP 5093684 A JP5093684 A JP 5093684A JP S60195980 A JPS60195980 A JP S60195980A
- Authority
- JP
- Japan
- Prior art keywords
- light
- film
- receiving element
- semiconductor substrate
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000010354 integration Effects 0.000 claims abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 108091008695 photoreceptors Proteins 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- 230000007257 malfunction Effects 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 3
- 239000012788 optical film Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- 241000276457 Gadidae Species 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- WYTGDNHDOZPMIW-RCBQFDQVSA-N alstonine Natural products C1=CC2=C3C=CC=CC3=NC2=C2N1C[C@H]1[C@H](C)OC=C(C(=O)OC)[C@H]1C2 WYTGDNHDOZPMIW-RCBQFDQVSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
- H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic Table
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は同一の半導体基板＋に受些素子とそれ以外の素
子とを一体に形成してなる半導体集積回路装置に関し１
％に光の影、響による誤動作の防止を図った装置に関す
るものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device in which a passive element and other elements are integrally formed on the same semiconductor substrate.
This relates to a device designed to prevent malfunctions caused by the influence of light and sound.
一般にホトセンサやＣＯＤ等の半導体降積回路装置は同
一半導体基板上に受光素子やそれ以外の、素子を一体に
形成しておき、外部からの光信号を受光二子により受信
してこれを電気信号に変換し、他の素子で種々の信号処
理を行なうようＫなっている。しかしながら、このよう
な装置では、受光素子以外の素子（以下、他の素子と称
する）に光、が照射されると素子、のＰＮ接合部或いは
それよりも、深い半導体基板中で光エネルギにより電荷
（電子と正孔）が発生し、素子の誤動作を誘起するとい
う問題が生じ易、い。In general, semiconductor drop-down circuit devices such as photosensors and CODs have a light-receiving element and other elements integrally formed on the same semiconductor substrate, and receive optical signals from the outside using the light-receiving pair and convert them into electrical signals. K is designed to convert the signal and perform various signal processing using other elements. However, in such a device, when an element other than the light-receiving element (hereinafter referred to as other element) is irradiated with light, a charge is generated by the light energy in the PN junction of the element or deeper in the semiconductor substrate. (electrons and holes) are generated, which tends to cause the problem of inducing device malfunction.
このため、従来では他の素子上にアルミニウム等の光不
透過部材からなる遮光膜を形成し、光が直接他の素子に
照射されないような対策が試みられている（たとえば雑
誌ｒＳｅｍｉｃｏｎｄｕｃｔｏｒＷｏｒｌｄＪ１９８２
年１２月号Ｐ５０〜５７）。For this reason, conventional measures have been taken to prevent light from directly irradiating other elements by forming a light-shielding film made of a light-impermeable material such as aluminum on other elements (for example, see the magazine rSemiconductor World J1982).
December issue P50-57).
しかしながら、受光素子と他の素子は同一半導体基板を
通して一体形成されているため、光が照射される受光素
子やこれより深い位置の半導体基することＫなり１．前
述見た誤動作を確実に防止す、・ることは困難であり、
装置の信頼性を低下させる １鴫・ “
原因になっている。また、と・のように受光！子と他の
素子とを同一半導体基板上に平面配置（−２次元）した
構成では集積度の向上には限度がある。However, since the light-receiving element and other elements are integrally formed through the same semiconductor substrate, the light-receiving element to which the light is irradiated and the semiconductor substrate at a deeper position may be affected. It is difficult to reliably prevent the malfunctions mentioned above.
In addition, in a configuration in which the light receiving element and other elements are arranged on the same semiconductor substrate in a plane (-2 dimension), the degree of integration decreases. There are limits to how much improvement can be made.
本発明の目的は光による素子の誤動作を防止して装置の
信頼性を向上するとｉＫ集ｉ゛度の向上な １図ること
のできる率゛導体集積回路装−を提耐る ′□“ことに
ある。The object of the present invention is to provide a high-conductor integrated circuit device that can improve the reliability of the device by preventing malfunctions of elements caused by light, thereby increasing the IK integration. be.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基板には直接他の素子を形成す金と共
Ｋ、その上層Ｋｇ光膜を形成し、この遮光ｉ上［４光素
子を形成することにより、他の素・子への光の影響を確
実に防止して誤動作の防止を図ると共に、−３次元構成
により集積度の向上を達成することができる。That is, a Kg optical film is formed on the semiconductor substrate along with the gold that directly forms other elements, and a Kg optical film is formed on top of the Kg optical film, and on this light shielding layer [4] By forming an optical element, light is transmitted to other elements/devices. In addition to reliably preventing the influence and preventing malfunctions, the -3-dimensional configuration can improve the degree of integration.
〔実施例１〕
第１図は本発明め一実施例の構成図であり、受光素子Ｄ
ＩないしＤｔ、受光素子以外の受動素子および能動素子
によ−て構成した内部回路Ａ、受光素子以外からの入力
信号用端子■、ないしｉ出力用端子０＋ 藻ｔ’ＬＯ，
ｉ＜’、て構成して、いる。[Embodiment 1] FIG. 1 is a block diagram of a first embodiment of the present invention, in which the light receiving element D
I to Dt, internal circuit A composed of passive elements and active elements other than the light receiving element, terminal ■ for input signals from other than the light receiving element, to i output terminal 0+, t'LO,
It is composed of i<'.
第２図はこの半導体集積回路装置の受光素子や内部回路
の断面図である。図にお℃・て、１はシリコン等の半導
体基板であり、この主面上にはＭＯ８型電界効果トラン
ジスタ２等の能動素子やその他の受動素子等を形成し、
これら能動素子と受動素子とで前記内部回路Ａを形成し
て（・る。そして、この内部回路Ａ上には５ｌｏｚやＰ
ＳＧ等の層間絶縁膜３を゛形成し、更Ｋ”＋の上にはＡ
！膜等の一光膜４を全面に形成゛シ文い′□る。この遮
光膜４は蒸着或いは他の方法により形成し、光を殆ん°
ど覇いし全ぐ透過しな□いように構成ｉれる。そして、
この遮光膜４上に前記蔓光素子Ｄ”ｒ“”：’ｐｔを形
成し′忙い°る。本例では受光素子（ＤＩで代表する）
はアモー゛１ファスｊｌＪコンにより下から１にＰ型層
６゜Ｉ型（真性）層７．？Ｊ型層８を形成しかつこれら
を所要の平省形袂にパタ一二”ｙｑしたホトダイオード
として構成して□いる。゛更眠最′上のＮ型′膚□８上
に入Ａ′ｌ［＃−らなる′電ｆｆｌ１．９濠形成し°た
１で、蚕体な光透過するパッジページ冒ン膜′１０′に
て被−している訃なお、前蛇蓮光膜４は前記ｐ型層６の
共通電極としても機能される。な釘、Ｐ’ＩＮ□ホト夛
イオードＤ、をアモルファスレ゛リコンモ形成している
のは、受光素手′Ｄ□のｉ成は内部゛回路Ａや遮光膜４
の形成後に行なうため□、内部回路Ａの特性を劣化させ
るような高温で形成するので好ましくないこと、また遮
光膜４をＡ！材で形成している場合に、Ａ４は５００℃
以上の温度で溶融等を起こすので、受光素子りをこれよ
りも低温で形成するためである。―みに、テモルファス
シリコンは。FIG. 2 is a sectional view of the light receiving element and internal circuit of this semiconductor integrated circuit device. In the figure, reference numeral 1 denotes a semiconductor substrate made of silicon or the like, on the main surface of which active elements such as an MO8 field effect transistor 2 and other passive elements are formed.
The above-mentioned internal circuit A is formed by these active elements and passive elements.
An interlayer insulating film 3 such as SG is formed, and A
! A light film 4 such as a film is formed on the entire surface. This light-shielding film 4 is formed by vapor deposition or other methods to block most of the light.
It can be configured in such a way that it is completely transparent. and,
The optical element D"r":'pt is formed on this light shielding film 4. In this example, a light receiving element (represented by DI) is used.
From the bottom, P type layer 6° I type (intrinsic) layer 7. ? A J-type layer 8 is formed and these are constructed as photodiodes patterned 12"yq in the required flattened area. In addition, the front serpentine light film 4 is covered with a light-transmitting Pudge Page film 10 formed by forming a moat 1. It also functions as a common electrode for the p-type layer 6. The nail, P'IN□ photodiode D, is formed by an amorphous silicone. and light shielding film 4
Since it is performed after the formation of □, it is undesirable because it is formed at a high temperature that deteriorates the characteristics of the internal circuit A. Also, the light shielding film 4 is formed after the formation of A! A4 is 500℃ if it is made of wood.
This is because the light-receiving element is formed at a lower temperature than this, since melting etc. will occur at a temperature higher than this. -What about temorphous silicon?
モノシラン（８１Ｈ，）ガスのブロー放電分−によっ℃
３００℃程度の低温で形成できる。Due to the blow discharge of monosilane (81H,) gas
It can be formed at a low temperature of about 300°C.
□以上の構成によれば、半導体集積回路装置の表面に光
を”′照射すれば受光素子り、から、電気信号が“出力
ぎれ、ぞして：、この信号は内部回路Ａにおいて処理さ
れる。このとき、受光素子Ｄ１に照射された光は遮光−
４により遮ら糺るため内部回路Ａ］な“いし半導体゛基
板ＩＫ′は絢ｉされない。これによ”□゛す、内″−回
路Ａや半導体基板１における電荷の発生ないし”キの影
−を確★−防正でき、ｉに内部回路ピおける誤動作を防
止して装置の信頼性を向上で毎る。まハ、受光素子Ｄ＋
は内部回路Ａとは上□下位置′１ンつ讐り”３次元的に
形成しているので；集積度の向上を図ることができる。□ According to the above configuration, when the surface of the semiconductor integrated circuit device is irradiated with light, the light receiving element is activated, and the electrical signal is outputted.This signal is then processed in the internal circuit A. . At this time, the light irradiated onto the light-receiving element D1 is blocked -
4, the internal circuit A and the semiconductor substrate IK' are not illuminated. This prevents the generation of electric charges in the internal circuit A and the semiconductor substrate 1, or the shadow of the internal circuit A and the semiconductor substrate IK'. It is possible to prevent malfunctions in the internal circuitry and improve the reliability of the device. Well, light receiving element D+
Since it is formed in a three-dimensional manner at the upper and lower positions of the internal circuit A, the degree of integration can be improved.
〔実施例２〕
第３図は本発明をＣ０Ｄ（電荷結合素子）を有する半導
体集積回路装置に適用した実施例である。[Embodiment 2] FIG. 3 shows an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a C0D (charge coupled device).
図に□お（：て、１１は半導体基板であり、その主面上
には前例と同様に内部回路入を形成し、その上に絶縁膜
１２を形成している。更にその上層にはＡ４膜からなる
遮光膜１３を形成し、その上ＫＣＣＤ素子１４を形成し
ている。このＣＯＤ素子１４は下から上に向かって絶縁
膜１５、転送用ゲート下部電極１６、下部絶縁騰１７、
アモルファスシリコン１８、上部絶縁膜１９．転送用ゲ
ート上部電極２０とで構成し、全体を透明保護膜２１で
被覆している。In the figure, 11 is a semiconductor substrate, on the main surface of which an internal circuit is formed as in the previous example, and an insulating film 12 is formed on it. A light shielding film 13 consisting of a film is formed, and a KCCD element 14 is formed thereon.This COD element 14 includes, from bottom to top, an insulating film 15, a lower transfer gate electrode 16, a lower insulating layer 17,
Amorphous silicon 18, upper insulating film 19. It is composed of a transfer gate upper electrode 20 and is entirely covered with a transparent protective film 21.
したがって、本例にあっても、ＣＯＤ素子１４に光を照
射して電気信号を出力させこれを内部回路Ａにおいて信
号処理するが、光は遮光膜１３により遮られて内部回路
Ａや半導体基板１１には到達しないため電荷の発生はな
く、誤動作が防止できる。また、ＣＯＤ素子１４と内部
回路Ａとの３次元構成により集積度の向上も達成できる
。Therefore, in this example as well, the COD element 14 is irradiated with light to output an electrical signal, which is processed as a signal in the internal circuit A. However, the light is blocked by the light shielding film 13 and the internal circuit A and the semiconductor substrate 11 Since it does not reach , no charge is generated and malfunctions can be prevented. Furthermore, the three-dimensional configuration of the COD element 14 and the internal circuit A can also improve the degree of integration.
（１）半導体基板上に形成した内部回路（受光素子以外
の素子）上に遮光膜を形成し、その上に受光素子を形成
し工いるので、受光素子に光が照射されても光は遮光膜
に遮られて内部回路や半導体基板上まで到達されること
はなく、これらにおける電荷の発生が防止されて素子の
誤動作が防止され。(1) A light-shielding film is formed on the internal circuit (elements other than the light-receiving element) formed on the semiconductor substrate, and the light-receiving element is formed on top of it, so even if the light-receiving element is irradiated with light, the light is blocked. It is not blocked by the film and does not reach the internal circuits or the semiconductor substrate, which prevents the generation of electric charge and prevents malfunction of the device.
装置の信頼性を向上することができる。The reliability of the device can be improved.
（２）内部回路の上層の遮光膜上に受光素子を形成した
３次元構成としているので、同一面積に対する集積度の
向上を図ることができる。(2) Since the three-dimensional structure has a light-receiving element formed on the light-shielding film on the upper layer of the internal circuit, it is possible to improve the degree of integration for the same area.
（３）受光素子はアモルファスクリコンにより形成し又
いるので内部回路や遮光膜を熱により損傷することはな
い。(3) Since the light receiving element is made of amorphous silicon, the internal circuitry and light shielding film will not be damaged by heat.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが１本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しナイ範囲で種々変更可
能であることはいうまでもない。たとえば、第１実施例
において遮光膜を絶縁材で形成してもよく、この場合に
はその直上に電極膜を付設する。また二上側の電極を透
明電極で形成し１これで受光素子な被覆してもよい。ま
た、第２実施例で遮光膜を絶縁膜で形成すれば。Although the invention made by the present inventor has been specifically described above based on examples, it is to be noted that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Not even. For example, in the first embodiment, the light shielding film may be formed of an insulating material, and in this case, an electrode film is provided directly above it. Alternatively, the upper electrode may be formed of a transparent electrode, and the light receiving element may be covered with this. Moreover, if the light shielding film is formed of an insulating film in the second embodiment.
その直上の絶縁膜は不要である。更に、受光素子の構造
は種々に変更できる。An insulating film directly above it is unnecessary. Furthermore, the structure of the light receiving element can be modified in various ways.
以上の説明では主として本発明者によってなされた発明
をその背景Ｅなりた利用分野であるホトダイオードやＣ
ＯＤ等の受光素子を有する半導体集積回路装置に本発明
を適用した場合について説明したが、それに限定される
ものではなく、化合物半導体のホトセンサを含む装置に
も適用できる。In the above explanation, the invention made by the present inventor will mainly be explained in relation to its background, which is the application field of photodiodes and C.
Although the present invention has been described in the case where it is applied to a semiconductor integrated circuit device having a light receiving element such as an OD, the present invention is not limited thereto, and can also be applied to a device including a compound semiconductor photosensor.
更に、内部回路もバイポーラ型素子、バイポーラ型とＭ
ＯＳ型の共存型であってもよく、その機能も信号の増幅
や記憶であってもよい。Furthermore, the internal circuit also includes bipolar type elements, bipolar type and M
It may be an OS type coexistence type, and its function may be signal amplification or storage.
第１図は本発明装置の全体構成図、
第２図は要部の断面図。
第３図は他の実施例の断面図である。
１・・・半導体基板、３・・・絶縁膜、４・・・遮光膜
、６・・・Ｐ型層、７・・・工型層、８・・・Ｎ型層、
９・・・電極。
１０・・・パッジページ請ン１１１．１１・・・半導体
基板、１３・・・遮光膜、１４・・・ＣＣＤ素子、１５
，１７゜１９・・・絶縁膜＋ １６．２０・・・電極、
１８・・・アモルファスシリコン、Ａ、Ａ・・・内部回
路、Ｄ、−Ｄｔ・・・受光素子（ホトダイオード）。
第 １ 図
Δ
第 ２ 図
第３図FIG. 1 is an overall configuration diagram of the device of the present invention, and FIG. 2 is a sectional view of the main parts. FIG. 3 is a sectional view of another embodiment. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Insulating film, 4... Light shielding film, 6... P type layer, 7... Engineering layer, 8... N type layer,
9...electrode. 10...Pudge page sign 111.11...Semiconductor substrate, 13...Light shielding film, 14...CCD element, 15
, 17° 19... Insulating film + 16.20... Electrode,
18... Amorphous silicon, A, A... Internal circuit, D, -Dt... Light receiving element (photodiode). Figure 1 Δ Figure 2 Figure 3
Claims (1)
幇一体的に形成するようＫした半導体集積回路装置にお
いて、半導一基板Ｋｇ接受光素子以外の素子を形成する
と共にその先層に！光線を形成し、この遮光膜上に前町
受光素子を形成ルたことを特徴とする半導体集積口７．
路装電０１２、受光素子は非昂質シリコンにて形成した
ＰＮ接合やＰＩＮ接合ホトダイオードとした特許請求の
範囲第１項記載の半導、、体集、！回路装置。、。 ３、 ３１１光膜をアルミニウム等の導率。材料により
形成して、これを電極として構成して在る特許、請求の
範囲第１項又は第２項記載の、半導体集積回路装置。[Claims] 11. In a semiconductor integrated circuit device designed to integrally form a light-receiving element and other elements on the same semiconductor substrate, the elements other than the light-receiving element are formed on one semiconductor substrate, and the elements other than the light-receiving element are formed on the next layer! 7. A semiconductor integration port characterized in that a light beam is formed and a Maemachi light receiving element is formed on the light shielding film.
Road equipment 012, the semiconductor according to claim 1, in which the light-receiving element is a PN junction or PIN junction photodiode formed of non-ironous silicon, collection! circuit device. ,. 3. Conductivity of 311 light film such as aluminum. A semiconductor integrated circuit device according to claim 1 or 2, which is made of a material and configured as an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050936A JPS60195980A (en) | 1984-03-19 | 1984-03-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59050936A JPS60195980A (en) | 1984-03-19 | 1984-03-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60195980A true JPS60195980A (en) | 1985-10-04 |
Family
ID=12872703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59050936A Pending JPS60195980A (en) | 1984-03-19 | 1984-03-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60195980A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63170958A (en) * | 1987-01-09 | 1988-07-14 | Agency Of Ind Science & Technol | Optoelectronic |
| JP2001015792A (en) * | 1999-04-28 | 2001-01-19 | Denso Corp | Photosensor |
-
1984
- 1984-03-19 JP JP59050936A patent/JPS60195980A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63170958A (en) * | 1987-01-09 | 1988-07-14 | Agency Of Ind Science & Technol | Optoelectronic |
| JP2001015792A (en) * | 1999-04-28 | 2001-01-19 | Denso Corp | Photosensor |
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