JPS60195795A - Dynamic ram - Google Patents

Abstract

PURPOSE:To make each voltage restoring time of an electrode and substrate coincident with each other, to enlarge a reading out level margin, to make the reading out operation higher in speed, and to simplify the constitution used for this purpose, by connecting the electrode of the capacitor for common storage of a pair of memory arrays with each other through a resistance means. CONSTITUTION:A pair of memory arrays M-ARY1 and M-ARY2 are arranged at the right and left sides and a pair of data lines DL are connected to the pair of input terminals of a sense amplifier SA between the memory arrays M-ARY1 and M-ARY2. Thus a one-intersecting point system is adopted. Plates PL1 and PL2 of the memory arrays M-ARY1 and M-ARY2 are connected with each other through a resistance element R. The value of the resistance element R is set so that the restored value of the coupling potential at each plate from a change can coincide with the voltage of a substrate and, accordingly, potential changes of the substrate voltage and plate become reverse in phase to each other. Moreover, the element R is formed with a fine aluminium wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a dynamic RAM (random access memory), and relates to a technique effective for, for example, a -intersection type dynamic RAM.

[Background technology]

In dynamic RAM, there is a two-intersection method in which a word line intersects a pair of complementary data lines arranged in parallel, and a memory cell is arranged at each intersection, and a two-intersection method in which a word line is arranged in parallel with a pair of complementary data lines and a memory cell is arranged at each intersection. A single intersection method has been considered in which memory cells are arranged by making a pair of arranged data lines intersect with a word line, respectively.

The inventor of the present invention has revealed that the following problem occurs in the above-mentioned -intersection type dynamic RAM.

That is, under the -intersection method, for example, when reading a memory cell in the right memory array, a dummy cell in the left memory array is selected to obtain a read reference voltage. At this time, as shown in the waveform diagram of FIG. 1, in the selected memory array side, if a large number of memory cells connected to each data line DL are held at a low level by the word line selection operation, The information storage capacitors of the memory cells are charged up all at once from each precharged data line DL. Therefore, the potential DL of all data lines decreases by several hundred mV. This level drop lowers the substrate voltage -vBB due to coupling due to parasitic capacitance between the data line and the substrate.

On the other hand, the common electrode (plate) PL of the information storage capacitor is raised to a high level due to the coupling in which the precharge level is transmitted from the data line.

Such a level change between the substrate voltage -Vaa and the shared electrode PL of the information storage capacitor changes the level of the data line through the parasitic capacitance with the data line. In this case, since the resistance value of the common electrode PL is relatively small, it immediately returns to the original level, whereas the substrate voltage -vB
B has a relatively large resistance value on the substrate, so
Recovery to that level will be delayed.

Therefore, as shown by the broken line in the figure, the potential of the data line DL on the selected memory array side is raised in the first half due to coupling with the plate, and in the second half, the potential of the data line DL on the side of the selected memory array is increased due to the influence of compression from the substrate voltage -vaB. received and degraded. Therefore, the data line potential VH for high-level reading and the data line potential VL for low-level reading are affected by an imbalance.

On the other hand, the read reference voltage Vref formed by selecting a dummy cell in an unselected memory array shows a similar change, but when viewed from the sense amplifier, it acts in the opposite phase as shown by the broken line in the figure. Become. Therefore, a serious problem arises in that the level margin between the reference voltage Vref and the low level VL becomes small at early timing, and the level margin between the reference voltage Vref and the high level VH becomes small at late timing.

(Object of the Invention) An object of the present invention is to provide a dynamic RAM with a simple configuration and an enlarged read level margin.

Another object of the present invention is to provide a large operating margin, and
The object of the present invention is to provide a dynamic RAM that operates at high speed.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by connecting the electrodes of the information storage canisters in the -intersection type memory array through resistance means, the voltage recovery time of the common electrodes can be reduced to the voltage recovery time of the substrate voltage. This is to offset the influence on the data line.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the invention. The placement numbers of each circuit program in the same figure are drawn in the same way as the layout and numbers in an actual semiconductor integrated circuit. In addition, each circuit block in the same figure is a well-known MO5
Integrated circuit manufacturing techniques are formed on semiconductor substrates such as single crystal silicon.

Although not particularly limited, a pair of memory arrays M-ARY
1 and memory array M-ARY2 are arranged on the left and right.

A sense amplifier SA is provided between the two memory arrays M-^RY1 and M-ARY, and configures the left memory array M-ARYI and the right memory array M-ARY2 with respect to the pair of input terminals. A pair of data lines D
A single intersection method is adopted in which L and DL are connected.

Each of the above memory arrays M-ARYI and memory array M-A
RY2 has dummy arrays D-ARYl and D-, respectively.
ARY2 is provided.

In addition, although not particularly limited, both of the memory arrays M-A
In the intermediate part between RYI and memory array M-ARY2, there is a column switch for selectively connecting a pair of common data lines CD, CD and the above-mentioned pair of data lines DL-51 running in the vertical direction in the figure. A Y address decoder Y-DCR is arranged to form CW and seven selection signals.

Furthermore, below each memory array M-ARYI, M-ARY2, there are X address decoders X-DCRI and X-DC for selecting word line WL and dummy word line DWL.
H2 is provided. These X address decoders are configured such that, for example, the X address decoder
When selecting a memory cell, the X address decoder X-DCH2 always operates to select the dummy word line DWL and select the dummy array D-ARY2. Conversely, the X address decoder X-DCR2 selects the word line according to the address signal to
When selecting the memory cell Y2, the X address decoder X-DCRI always operates to select the dummy word line DWL and select the dummy array D-ARY 1.

Although not particularly limited, address buffer ADB takes in X address signals AXO to AXi in synchronization with row address strobe signal RAS, and
Send to DCRI, X-DCH2. Further, the Y address iN%AYo to IAYl input later than this is taken in in synchronization with the column address strobe signal CAS and sent to the Y address decoder Y-DCH.

The common data lines CD and CD are connected to the data output buffer D.
It is connected to the input terminal of OB and the output terminal of data input buffer DIB, respectively. Then, the read output Dout is sent out to the outside via the data output buffer DOB, and the write data Din is supplied via the data input buffer D I B+.

Each of the circuit blocks described above each performs a series of write or read operations in accordance with a timing signal formed by a timing control circuit (not shown) that receives address strobe signals RAS, CAS and a write enable signal WE, although this is not particularly limited.

FIG. 3 shows a perspective cross-sectional view of the element structure of one embodiment of the above memory cell.

In the figure, 1 is a P-type semiconductor substrate, 2 is a relatively thick insulator III (hereinafter referred to as field insulator film), and 3 is a third insulator.
3a is a high dielectric constant dielectric film, 4 and 5 are N0-type semiconductor regions, 6 is a first polycrystalline silicon layer, 7 is a second polycrystalline silicon layer, 8 is an aluminum layer, and 9 is a thin layer. This is the first gate insulating film (510, film).

MO3FE for address selection in one memory cell MC
TQm has a substrate, a source region, a drain region, a gate electrode and a P-type semiconductor substrate 1, N
Medium-sized semiconductor region 4, N medium-sized semiconductor region 5, third gate insulator Ill made of semiconductor oxide (S 5021111
) a and a second polycrystalline silicon layer (second conductive polysilicon layer) 7, respectively. The second conductive polysilicon layer 7 is connected to the aluminum layer 8 as the word line W, although not particularly limited thereto. Although the N medium semiconductor region 5 is not particularly limited, the data line D (
D) is used.

On the other hand, in the storage capacitor C3 in the memory cell MC, one electrode, a dielectric layer, and the other electrode are a first polycrystalline silicon layer (first conductive polysilicon layer) 6, an insulating film (semiconductor oxide film, or A two-layer insulating film consisting of the first game diagonal Il!!9 and a semiconductor nitride, that is, S I * Nm layer)
and N medium-sized semiconductor regions 4, respectively. A power supply voltage Vcc is applied to the upper electrode (first polycrystalline silicon layer 6) of this capacitor Ca.

The first conductive polysilicon layer 6 constituting the storage capacitor is shared (in a plate structure) in each of the memory arrays M-ARYI and M-ARY2, as shown in FIG.

In this embodiment, each of the memory arrays M-ARY
Plate PL in I and memory array M-ARY2
I and PL2 are connected via a resistance element R. The resistance value of this resistance element R is, in FIG.
Alternatively, by inserting such a resistor R, which is set so that the recovery of the change in the force and pulling potential at PL2 is the same as the substrate voltage -van, as shown by the broken line in the same figure, the substrate voltage -vse and the plate This is intended to cause the potential change to be in opposite phase to that of PL. Although not particularly limited, the resistance element is formed of fine aluminum wiring.

〔effect〕

+1) By connecting the plates constituting the information storage capacitor in the pair of memory arrays through a resistive element with a relatively large resistance value, potential changes between the substrate voltage -Vaa and the plate voltage at the time of reading can be suppressed. can be generated in reverse phase. by this,
This affects the high level VH and low level VL of the data line DL (DL) and the reference voltage Vref in opposite phases to each other. Therefore, data line DL (DL
) high level VH, low level VL and reference voltage Vr
In ef, since the changes in the substrate voltage -vea and the plate voltage can be offset, it is possible to prevent deterioration of the level margin, thereby achieving the effect that the operating yardage can be increased.

(2) Since the level margin can be expanded by the above (1), the operation timing of the sense amplifier can be made faster, so that high-speed reading can be achieved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the resistive element R for canceling the coupling noise can take various embodiments, such as one using a conductive polysilicon layer. In addition to the two memory arrays described above, the memory array may have a number of embodiments such as a four memory array in which a pair of memory arrays is arranged below the X address decoder. In other words, the pair of memory arrays M-ARYI and M-ARY2 may be used as the minimum unit, and a plurality of pairs may be combined to form a structure.The structure of the memory cell may be modified according to various embodiments. It is something that can be taken. Further, the address signal may be multiplexed and supplied using a common address terminal, or may be supplied from each address terminal.

Further, in the above embodiment, the insulating film is composed of a semiconductor oxide film and a semiconductor nitride film in order to increase the capacitance value of the capacitor, but the invention is not limited to this. For example, the insulating film is composed of a semiconductor oxide film Alternatively, the data line may be composed of a conductive polysilicon layer.

Further, the N-type semiconductor region 4 does not need to be formed; that is, an N-type inversion layer (forming the electrode on the 11h side of the capacitor Cs) is induced on the surface of the P-type semiconductor substrate 10 by the power supply voltage Vcc. It is from.

[Field of Application] The present invention can be widely used in dynamic RAMs in which a memory array is constructed using the -intersection method.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram for explaining the dependence of read patterns in a memory array of the -intersection method. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram of a memory cell. FIG. 4 is a perspective sectional view of an element structure showing an embodiment. FIG. 4 is a configuration diagram of a plate showing an outline of the present invention. M-ARYI, M-ARY...Memory array, D-AR
Yl, D-ARY2...Dummy array, SA...Sense amplifier, CW...Column switch, Y-DCR...X address decoder, X-DCRl, X-DCR2...X address decoder, DOB...Data output buffer , D.I.
B...Akio Takaran on behalf of the data person

Claims (1)

[Claims], 1. a pair of memory arrays arranged on both sides of the sense amplifier, each of which has a data line and a word line arranged in a single intersection system; a dynamic memory cell provided at each intersection of the data line and the word line; It is characterized by comprising: a common electrode of the information storage capacitor in each memory array and to which a predetermined voltage is supplied; and a resistance means for connecting between the common electrodes of the information storage capacitor in both memory arrays. Dynamic RAM. 2. The dynamic type according to claim 1, wherein the resistance means for connecting the common electrodes of the information storage capacitors in both memory arrays is constituted by fine aluminum wiring. RAM.