JPS6019526B2 - auto clear circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to an auto clear circuit.

In digital control circuits such as electronic desktop calculators,
The auto clear circuit includes various memory circuits such as flip-flop circuits, and outputs a clear signal to automatically set these memory circuits to initial values when the power is turned on.

This auto-clear circuit inverts the clear signal formed with the rise of the power supply voltage by the output of a pulse counting circuit that receives a predetermined timing pulse, such as a word pulse, formed based on the oscillation output of an oscillation circuit. , a device that performs clearing is being considered. In this auto clear circuit, which forms the above-mentioned predetermined timing pulse mainly based on the oscillation output of the CR type oscillation circuit, when the power supply voltage is below the stable operating voltage of the oscillation circuit, the oscillation frequency is This causes an abnormal oscillation phenomenon in which the voltage increases, so when the rise of the power supply voltage is slow, this abnormal oscillation period becomes short.

Therefore, since the above-mentioned timing pulse is formed based on this abnormal oscillation output, it has been found that there is a problem that the clearing operation is performed at an early timing, and as a result, the clearing operation cannot be performed reliably. . The present invention was made in order to provide an auto-clear circuit that can perform a reliable clearing operation that is not affected by the rise of the power supply voltage. o In one embodiment of the present invention, it is detected that the power supply voltage has reached the lower limit voltage required for stable operation of the oscillation circuit, and based on this detection output, a pulse counting operation for clearing release operation is performed.

The present invention will be specifically explained below with reference to Examples.
FIG. 1 is a circuit diagram showing an embodiment of the present invention.

la to lc are pulse counting circuits for forming a clear signal ACL. These circuits la to lc are based on complementary MIS logic circuits (C-MIS) configured by a combination of a p-channel MISFET (insulated gate type 0 field effect transistor) and an n-channel MISFET, and have a gate electrode in the channel region. MISFETs with arrows pointing in the opposite direction, such as MISFETQ, 4,
Q, 3, etc. are p-channel type MISFETs, and the channel region is marked with an arrow pointing toward the gate electrode.
ISFETs, such as MISFETQ, . , Q, 2 etc. are n
It is a channel type MISFET.

Each of the circuits la to lc constituting the pulse counting circuit is composed of the same circuit, and for example, the first stage circuit la includes MISFETQ, . ．． A series circuit consisting of Q,2 and a capacitor C, and a parallel MISFET connected in series to the skin SFETQ,5, which receives the output of this capacitor C, as an input.
A circuit composed of Q, 6, Q, 7 and a depletion type MISFET Q, 4 as a load of this logic block, and a MISFET whose input is the output of this logic circuit.
Q, 8. The MISFET Q,2 of the series circuit is equipped with an inverter circuit consisting of a MISFET Q,9, and an inverted signal of a timing pulse to be counted, and a MISFET of a logic circuit.
Q, 6 contains timing pulses to be counted, MISFE
The outputs of the output inverter circuits are applied to TQ and 7, respectively.

Note that the other MISFETQ, . The output of the voltage detection circuit, which will be described later, is applied to the enhancement type MISFET Q, 3, which is installed between the output of the series circuit and the power supply voltage terminal, and the capacitor C is connected to the capacitor C when the power is cut off.
, and there is a similar MI between the outputs of the output inverter circuits Q, 8, Q, 9 and the power supply voltage terminals.
It is desirable to provide an SFET (not shown).

The second stage circuit lb and output stage circuit lc are also the same circuits as the first stage circuit, and the MISFET (
Q2,,Q. . . . (not shown) receives the output of the previous stage circuit as an input.

2 is a voltage detection circuit, which includes a voltage dividing circuit MISFET false, Qo2, which divides the power supply voltage Voo, and an inverter circuit N.
.

5 constitutes a voltage detection circuit, and the output inverter circuit No. 6 as a waveform shaping circuit constitutes the above-mentioned MISFETQ,
．． It forms the control signal C of.

This circuit is for detecting that the power supply voltage Voo has reached the stable operating voltage of the oscillation circuit 3, which will be described later.The circuit uses the temporary logic threshold voltage VT of the inverter circuit N as a reference voltage, and uses a voltage divider circuit to provide three levels. By comparing the shifted power supply voltage, the stable operating voltage V as described above is determined.
This is to detect T'. 3 is an oscillation circuit, and inverter circuit No. 3 is connected in series. This is a CR type oscillation circuit composed of 4, a capacitor Co, and a resistor Ro.

Inverter circuit No. 4 is a waveform shaping circuit. This oscillation circuit 3 is for forming various timing pulses in the digital control circuit, and the frequency dividing circuit 4
For example, two-phase clock pulses a. ◇ Form b. Reference numeral 5 denotes a timing pulse generation circuit, which receives the above-mentioned clock pulse as input and is composed of a ring counter, etc., and generates bit pulses, digit pulses,
Forms a timing pulse such as a word pulse.

In this embodiment, the word pulse ◇W is used as a timing pulse for the pulse counting circuit 1 constituting the auto clear circuit.

It will be understood that the object of the present invention can be achieved by explaining the operation of this circuit with reference to the operation waveform diagram shown in FIG. 2 below.

When the power is turned on, the power supply voltage Vo.

Suppose that it gradually rises. When this power supply voltage Voo is lower than the stable operating voltage VT' of the oscillation circuit 3, the oscillation circuit 3 oscillates at a high frequency due to abnormal operation. Therefore, the frequency of various timing pulses formed based on this oscillation output also increases, but since the output C of the voltage detection circuit 2 is at a low level, the MISFE of the pulse counting circuit 1
TQ,. is off, and even if MISFETQ,2 is turned on by the word pulse dW input during this time,
Capacitor C is not charged. On the other hand, when the power is turned on, this pulse counting circuit becomes depletion type MI.
SFET (Q.8, Q28, Q8......
(not shown), the output inverter circuit of each circuit is supplied with a high level, so the outputs of each stage A, B, A
All CLs are defined at low level.

A clearing operation is performed by using the output of this final stage as an auto clear circuit ACL. However, it goes without saying that this clearing operation is executed from the time when the power supply voltage Voo reaches the lower limit voltage for operation of various memory circuits. Next, the power supply voltage V.

. When reaches the stable operation lower limit voltage of the oscillation circuit 3, the output of the voltage detection circuit 2 becomes /. level, and the MISFET
Q. turns on. After this, the first arriving word pulse JW causes MISFETQ. 2 is turned on, capacitor C is charged up, and MISFET Q and 5 are turned on. At this time, MISFETs Q and 6 are off, so the inputs of the output inverter circuits Q, 8, Q, and 9 are as follows.
remains at a high level. When the word pulse ■w changes to a high level "0" and the MISFET Q, 8 is turned on, the input of the output isoverter circuit Q side Q, 9 becomes a low level, so that its output becomes a high level. Once the inverter circuits Q, 8, Q, 9 reach the /. level, the MISFETs Q, 7 in the previous stage logic block are turned on, so it is irrelevant to the word pulse OW, in other words, the subsequent ON/OFF of MISFETs Q, 6. The output A of the first stage circuit is held at a high level regardless of the current state. This first stage circuit la
When the output A changes to the level, the next stage MISFET Q2 is turned on.

Therefore, with the arrival of the next word pulse ◇w, the capacitor C2 at the next stage is charged up, and at the back edge of this pulse, the output B of this circuit lb changes to high level. The output stage circuit lc is similarly inverted by the third word pulse W, and clearing is automatically performed.
Auto clear signal can be obtained. According to this example circuit, since clearing is performed by outputting the counted word pulses after the oscillation circuit has stably operated, the time necessary for the clearing operation can be secured, and the above-mentioned malfunction can be avoided. It is possible to obtain an auto clear circuit that can prevent the above problems and operate reliably.

The present invention is not limited to the embodiments described above, and, for example, the operation of the oscillation circuit 3 or the timing pulse generation circuit may be controlled by the output of the voltage detection circuit.

Possible methods for this control include providing a gate circuit at the output and controlling this gate circuit using the above-mentioned self-voltage detection output, or cutting off the oscillation circuit or the feedback loop of the ring counter. Further, the pulse counting circuit may be of any type.

However, in order to simplify the circuit, it is desirable to have a circuit that first stabilizes at a certain level when the power is turned on, as in the circuit of the above embodiment. That is, in this embodiment circuit, the capacitor C is used to store the Patals count and also to define the output level when the power is turned on.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a diagram of its operating waveforms. la~lc...Pulse counting circuit, 2...
・Voltage detection circuit, 3...Oscillation circuit, 4...
... Frequency divider circuit, 5... Timing pulse generation circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. An auto-clear circuit configured to cancel a clear signal formed at the rise of the power supply voltage by the output of a counting circuit that receives a predetermined timing pulse formed based on the output signal of a timing pulse forming circuit. An auto clear circuit comprising a detection circuit for detecting that the power supply voltage has reached a voltage required for stable operation of the timing pulse forming circuit, and causing the counting circuit to perform a counting operation based on the detection output. .