JPS60192444A - Data transmitter - Google Patents

Abstract

PURPOSE:To transmit data with high accuracy by using an output of a logic circuit ORing an output pulse of a differentiation circuit and an inverting signal of an output signal of a pulse generating circuit as a clear signal of a counter circuit generating a synchronizing pulse of a control circuit. CONSTITUTION:A reception data signal P1 as shown in the figure (1) is transmitted from a reception circuit 1. A differentiation circuit 5 receives the reception data signal P1 and generates a pulse P2 as shown in the figure (2) at the falling of the reception data signal P1. A pulse generating circut 4 receives the reception data signal P2 and generates a pulse P3 as shown in the figure (3) at the rising of the reception data signal P2. A gate circuit 6 ANDs the inverted pulse of the pulse P3 from the pulse generating circuit 4 and the pulse P2 from the differentiation circuit 5 and transmits a pulse P4 as shown in the figure (4). The inhibition period of a clear pulse of a counter circuit 7 is provided by using the pulse generating circuit 4 in this way to prevent distortion of the pulse width of a transmission data signal.

Description

[Detailed description of the invention] Technical field The present invention relates to a data transmission device that transmits data.

BACKGROUND ART FIG. 1 is a block diagram showing the overall configuration of a prior art data transmission device. The control circuit b1 includes a receiving circuit d1,
Transmission IT: +1 path el, and processing device λ1 respectively f
'L connection. The control circuit b2 is connected to the receiving circuit d2. 'f:fL' is connected to the transmitting circuit e2 and the electronic control device 32. The control circuit bn includes a receiving circuit dn and a transmitting circuit en.
, and a processing device an. Transmission interval W
je l is sequentially negatively connected to the receiving surface l approximately d2, and the transmitting circuit e2 is negatively connected to the receiving circuit dn. The receiving circuit d1 is
Connected to the transmitting circuit en.

The embedded devices a1 to an are implemented by computers and terminals, and mutually transmit and receive data and control signals. The serial data f is converted into data I and sent out via transmitting circuits e1 to en, respectively. for example,
The data from the processing device a1 is converted to serial data by the control amount pasting 1, and the serial data l of j is the transmission plane 1.
The signal is transmitted to the receiving circuit d2 via e1.

(1) 2 converts the serial data received by the receiving circuit d2 into parallel data and supplies it to the 4-wire circuit a2. In this way, the data from the lσto-embedded storage a1 is transmitted to the stomach 32,
The data from the processing Wl&an is sent to (11 Riso+tttt a 1 to 11(2)) and then sent to EkenC.

For example, the serial data 22 from the sending R1r11 path e1 is the open flag 2 as shown in
The J and O's flags 23 are transmitted in a th-h format. The control circuit b1 receives the received amount % d l from Fig. 3 i.
The received data signal Q1 shown at ll is internally routed to the third FJl12+ based on the 1i-il) tl, l a link signal Q2.

Generally, this recycle a check signal Q2 is the received data signal Q.
It is reset at the falling edge of , and at a certain time after t, 1/i
After the elapse of tD, the pulse becomes synchronized with the received data signal Q1. The control circuit b1 receives the received data signal Q1 at the rising edge of the synchronized clock signal Q2.

Furthermore, in the -rape mode Q, the control Km circuit 1]1 sends out a completed transmission data signal Q3 as shown in FIG. 3(3) at the falling edge of the a-link signal Q2. However, loop mode means, for example, that the output data of the processing device a1 is transferred to the processing device a.
2, transmit the output data of processing device 1 "qa2" to processing device Man, and transmit the output data of processing device 1 "qa2" to 14
B Transmit the data to the processing device a1 (Cl7) (8 pieces).

As shown in FIG. 3, in the prior art, the received data signal Q1
Since the synchronizing signal Q2 is reset at the falling edge of the signal, if the received data signal Q1 repeats the logic [OJ, [IJ], the puff width of the transmitted data signal Q3 becomes short.

Therefore, the pulse width of the D8 signal becomes shorter and P decreases each time the C transmission is interrupted. Therefore, if a loop is fused with multiple transmission lines, the Makubu device will be unable to generate a bit error. 18 data transmission becomes less accurate.
The control circuits b1 to bn shown in (2) process the received data D.
There are cases in which the M devices a1 to an receive the signal nine times, and cases in which the signal is used as a repeater and transmits immediately after receiving C.

Purpose It is an object of the present invention to provide a data transmission device capable of solving the technical problems mentioned above and transmitting highly accurate data.

Embodiment FIG. 4 is an example of the present invention! /Iu example'I'4i Kiki 1
FIG. 1 is a block diagram showing a 1η configuration. In FIG. 4, the receiving circuit 1 is the 1st I+8! , 1 corresponds to the receiving circuits d1 to dn shown in FIG. 1, and the transmitting surface @2 corresponds to the transmitting circuits e1 to en shown in FIG. Control-1 path 3 receives C via line e1-
1 way IK is connected and line/! 2 to the C transmitting circuit 2. The receiving circuit 1 is connected to a C pulse generating circuit 4 and a differentiating circuit 5 via a line e1. The pulse generating circuit 4 is connected to one input terminal of the C gate 1-161 through the line e6, and the differentiating circuit 5 is connected to one input terminal of the C gate 6 through the line /7. The output terminal of the gate circuit 6 is connected to a counter circuit 7 via a line e5.The counter circuit 7 is connected to a counter circuit 8 via a line e4, and the output terminal of the gate circuit 6 is connected to a counter circuit 7 via a line e4. Connected to CIIJ's W13 via e3.

Hereinafter, one example of the C5 4th □□□ will be described with reference to the timing timing chart shown in FIG. The data signal sent from the transmission (g)lFPJ of rf+1 via line e11 is received by receiving circuit 1, and from receiving circuit 1 >
-Z 5 As shown in FIG. 1(1), q received data signal P1 is sent f. The differentiating circuit 5 receives this received data signal P1.
, and generates a full pulse P2 as shown in FIG. 5(2) at the falling edge of the received data signal P1.

The pulse generating circuit 4 receives the received data signal P2, and
+31 K in Figure 5 at the rising edge of the received data signal P2
A pulse P3 shown is generated. The pulse width of this pulse P3 is set in advance by the data transmission line -'+W. For example, the received data signal P2 has more than 5 bits of logic “1”.
If the data transmission condition is 8, the pulse width of the pulse pulse P3 should be set longer than the time corresponding to the 5 bits. Taking the logic II4! between the inverted pulse of pulse P3 from the differential circuit 5 and the pulse P2 from the differentiating circuit 5, 1'
The Hapulus P4 is sent out as shown in Figure 85 (4). The old counter 11dδ7 clears C by the parity signal P4 received via the line e5, counts the negative signal from the negative signal generating circuit 8, and outputs the negative signal to the line e3 as shown in FIG.
), the Hapulse P5 is sent out. The control circuit 3 is
Receive the received data signal P1 and create a C5 pulse as a pulse P5e as shown in FIG.
Send 6. This pa? The response P6 is a signal similar to the received data jj signal P] shown in FIG. 5(1).

Therefore, even when the control circuit is used in the loop mode V, a signal similar to the received data signal can be transmitted.

By using the pulse generation -1 path 4 in this way, the clear pulse of the counter circuit 7 is inhibited +9111JI is #
data transmission can be performed with high accuracy without distorting the pulse width of the transmitted data signal.

Effects As described above, according to the present invention, a prohibition period can be set for the clear signal of the C counter circuit by the differentiating circuit and the pulse generating circuit, and stable data with high precision can be transmitted. can.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a prior art data transmission device;
The figure is a diagram to explain the form of the signal by which serial data is transmitted.
64 is a timing chart for explaining the operation of the embodiment shown in FIG. 4. FIG. 5 is a timing chart for explaining the operation of the embodiment shown in FIG. DESCRIPTION OF SYMBOLS 1... Receiving circuit, 2... Transmitting circuit, 3... Control circuit, 4... Pulse generation circuit, 5... Differentiating circuit, 6...
... Gate circuit, 7... Counter circuit, 8... Kurovuku generation circuit, e1-e12... Line agent Masuriju Nishi Kyoukei part

Claims (1)

[Claims] The received data signal sent from the transmission line is given to a control circuit, a differentiation circuit, and a pulse generation circuit. The JJJC branch circuit generates each pulse when the distribution data signal changes from one level to the level of capability, and the pulse generating circuit generates a pulse when the received data signal changes from the level of capability to one level. The level of the output signal from the pulse generation circuit is changed, and the output of a logic circuit that ORs the output pulse of the first differential path and the inverted signal of the output signal of the pulse generation circuit is used to generate a synchronization pulse for the control circuit. A data transmission device characterized in that the control circuit sends out the received data signal as a transmission data signal in synchronization with a synchronization pulse from the counter circuit, using a clear signal from the counter circuit.