JPS60192434A - Fault detecting circuit - Google Patents

Fault detecting circuit

Info

Publication number
JPS60192434A
JPS60192434A JP59049733A JP4973384A JPS60192434A JP S60192434 A JPS60192434 A JP S60192434A JP 59049733 A JP59049733 A JP 59049733A JP 4973384 A JP4973384 A JP 4973384A JP S60192434 A JPS60192434 A JP S60192434A
Authority
JP
Japan
Prior art keywords
signal
level
output
circuit
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59049733A
Other languages
Japanese (ja)
Other versions
JPH0349220B2 (en
Inventor
Osamu Yamanaka
治 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59049733A priority Critical patent/JPS60192434A/en
Priority to US06/687,761 priority patent/US4658206A/en
Priority to DE19853500896 priority patent/DE3500896A1/en
Publication of JPS60192434A publication Critical patent/JPS60192434A/en
Publication of JPH0349220B2 publication Critical patent/JPH0349220B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/14Monitoring arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To detect a fault of a circuit through which a burst signal is transmitted easily with simple circuit constitution accurately by detecting whether or not the level of an output signal of the transmission circuit is within a prescribed range and using an exclusive OR with an input signal to detect the fault. CONSTITUTION:An intermediate frequency band directional coupler 10 (same as 5-7), a diode detector 11 and a DC amplifier 12 are fitted to an output/input section (or transmission frequency converter input section) of a fault detection circuit, a comparator 13 is connected to obtain a rectangular wave in response to an input burst signal. On the other hand, a comparator 14 detecting that the level is over L1 and a comparator 15 detecting that the level is below L2 are fitted to a signal detection circuit of the output side of the transmitter. Thus, when both rectangular wave signals are exclusively ORed by exclusive OR circuits 16, 17, 18, a fault of a device (in this case a transmission frequency converter 2 and a power amplifier 3) is detected independently of the presence of the signal.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はTDMA (Time Di vis ion
 Mul tiPle Access)用送信機等のバ
ースト状の信号を伝送する送信装置(送信周波数変換器
、電力増幅器等)の正常。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is based on TDMA (Time Division).
The normality of the transmitter (transmission frequency converter, power amplifier, etc.) that transmits burst signals, such as the transmitter for MultiPle Access.

異常の動作を検出する為の回路に関するものである。This invention relates to a circuit for detecting abnormal operation.

〔従来技術〕[Prior art]

近年、衛星通信等の分野においては、時分割多元接続方
式(TDMA方式)等の採用により、送信周波数変換器
、電力増幅器等の信号伝送装置においては自装置の障害
等の検出においても新たな技術が要求されるようになっ
てきている。第1図に従来のFDM−FM方式における
障害検出回路の一例を示す。図中の変調器(1)よりの
信号は送信周波数変換器(2)に入力され、周波数変換
された後、電力増幅器(3)を経て、アンテナ装置(4
)より送信される。
In recent years, in fields such as satellite communications, with the adoption of time division multiple access (TDMA), new technology has been developed for detecting faults in signal transmission equipment such as transmission frequency converters and power amplifiers. is increasingly required. FIG. 1 shows an example of a fault detection circuit in a conventional FDM-FM system. The signal from the modulator (1) in the figure is input to the transmission frequency converter (2), frequency converted, and then passed through the power amplifier (3) to the antenna device (4).
).

このような装置において、信号が正しく送信されている
かどうかを検出する方法として同図に示すように、送信
機出力に方向性結合器(5)を用い、送信出力の一部を
検波器(6)あるいは電力センサー等を用いて検出し、
直流増幅器(7)を通した後、ウィンドコンパレータ(
8)等を用いてその出力レベルが許容範囲(一定レベル
以上で一部レベル以下)にあるかどうかによって、装置
の異常を検出する方法がある。とれは、従来のFl)M
−FM方式においては出〃の電力1が常時は一定レベル
である為、にこの ・ような方法による検出が可能であ
ったことによる。
In such a device, as shown in the figure, a directional coupler (5) is used for the transmitter output, and a part of the transmitted output is sent to a detector (6) to detect whether the signal is being transmitted correctly. ) or detected using a power sensor, etc.
After passing through the DC amplifier (7), the window comparator (
There is a method of detecting an abnormality in the device based on whether the output level is within a permissible range (above a certain level and below a certain level) using, for example, 8). Tore is the conventional Fl) M
- In the FM method, the output power 1 is always at a constant level, so detection using this method was possible.

同様の回路を送信周波数変換器(2)の出力部に取付け
れば送信周波数変換型造の異常を検出することができる
If a similar circuit is attached to the output section of the transmitting frequency converter (2), abnormalities in the transmitting frequency converter structure can be detected.

しかしながら、このような方法では送信出力をたえず0
N10FFするような、いわゆるバーストモードの送信
伝送においては、出力の信号レベルが一定とならない為
に障害検出回路としては機能し得ない。しかも、T’D
MAのような通信方式においては送信バースト長9間隔
等も必ずしも一定せず、何種類ものバースト信号が送信
される故、上記回路の時定数を大きく取って平均出力電
力を検出する様にしても十分機能し得ない。
However, with this method, the transmission output is constantly reduced to 0.
In so-called burst mode transmission such as N10FF, the output signal level is not constant, so it cannot function as a failure detection circuit. Moreover, T'D
In a communication system such as MA, the transmission burst length 9 interval etc. are not necessarily constant and many types of burst signals are transmitted, so even if the time constant of the above circuit is set large to detect the average output power. cannot function adequately.

従って各バースト毎の出力電力を判定する為には端局よ
りのキャリア0N10FF信号をゲート信号を用いた。
Therefore, in order to determine the output power for each burst, the carrier 0N10FF signal from the terminal station was used as a gate signal.

高速のサンプルホールド回路とその出力のレベルを判定
する比較器回路により障害を検出する必要があるが、回
路が複雑になりすぎ又ゲート信号の受け渡し等端局装置
とのインターフェイスが増えて全体として監視等の信頼
度が落ちると云う欠点がある。
It is necessary to detect faults using a high-speed sample-and-hold circuit and a comparator circuit that determines the level of its output, but the circuit becomes too complex and the number of interfaces with end station equipment such as gate signal exchange increases, making it difficult to monitor the entire system. The disadvantage is that the reliability of the

〔発明の概要〕[Summary of the invention]

本発明はこのようにバースト状の信号伝送における機器
の障害検出を出力レベルが一定の範囲内にある事を確認
し且つ入力信号と出力信号の排他的論理和をとることに
より容易にかつ簡単な回路にて実現しようとするもので
ある。
The present invention makes it easy and simple to detect failures in equipment during burst signal transmission by confirming that the output level is within a certain range and by calculating the exclusive OR of the input signal and output signal. This is what we are trying to achieve with a circuit.

原理を第2図で説明する。伝送回路の遅延時間がないも
のと仮定すると、入力信号Aと出力信号Bの存在する時
間は、(イ)に示すように一致する。
The principle will be explained with reference to FIG. Assuming that there is no delay time in the transmission circuit, the times at which input signal A and output signal B exist coincide as shown in (a).

ところが、いずれかの信号の一部が欠落すると、(ロ)
に示すようにt、からt2の間に排他的論理和が成立す
る。従って、排他的論理和が成立すれば、伝送回路に異
常が生じたと判断できる。
However, if part of one of the signals is missing, (b)
As shown in , an exclusive OR is established between t and t2. Therefore, if the exclusive OR is established, it can be determined that an abnormality has occurred in the transmission circuit.

以上の判断は出力信号Bの有無によって異常を判断する
ものであるが、出力信号Bのレベルがレベルト1以上で
レベルト2以下である事をも確認するようにすれば、伝
送回路の異常の検出精度が更に向上する。
The above judgment determines an abnormality based on the presence or absence of output signal B, but if it is also confirmed that the level of output signal B is higher than level 1 and lower than level 2, it is possible to detect abnormalities in the transmission circuit. Accuracy is further improved.

衛星通信においては、地上局から衛星へ向って送信され
る電波のレベルは自局の回線品質の確保と他局への妨害
を抑える為非常に厳しく制約されており、自局の送信レ
ベルの監視は不可欠となっている。
In satellite communications, the level of radio waves transmitted from the ground station to the satellite is extremely strictly limited in order to ensure the line quality of the own station and to prevent interference with other stations, so it is necessary to monitor the transmission level of the own station. has become essential.

第2図(イ)に示す入力信号Aと出力信号Bとを通常の
排他的論理和回路に導入しても、その両端では波形にヒ
ゲが生じ、判断し難くなる事もあり得る。そこで、一方
の信号を遅延させて、その立−ヒリ、又は立下りに他方
の信号が存在するか否かで判断する方が得策である。出
力信号は入力信号に比し時間的に遅れるのが通常である
から、特に遅延回路を設けなくて済む場合もあり得る。
Even if the input signal A and the output signal B shown in FIG. 2(a) are introduced into a normal exclusive OR circuit, a whisker may appear in the waveform at both ends, making it difficult to judge. Therefore, it is better to delay one signal and determine whether the other signal is present at the rising edge or falling edge of the signal. Since the output signal is usually delayed in time compared to the input signal, there may be cases where it is not necessary to provide a particular delay circuit.

〔発明の実施例〕[Embodiments of the invention]

第8図に本発明による障害検出回路の一実施例の系統図
を示す。図中、(2)〜(7)は第1図と同様の機能ブ
ロックを示し、(9)は例えばTDMA用変調器又は変
復調器を薔むTDMA端局装置であり、その出力は送信
周波数変換器(2)へ送出されるが、本発明ではこの出
力部(又は送信周波数変換器入力部)に(5)〜(7)
と同様の中間周波数帯方向性結合器θQ。
FIG. 8 shows a system diagram of an embodiment of the fault detection circuit according to the present invention. In the figure, (2) to (7) indicate the same functional blocks as in FIG. However, in the present invention, signals (5) to (7) are sent to this output section (or transmission frequency converter input section).
An intermediate frequency band directional coupler θQ similar to .

ダイオード検波器αVおよび直流増幅器θカを取付け、
これに比較器0■を接続して入力のバースト信号に応じ
た矩形波が得られるようにしている。一方送何機出力側
の信号検出回路にもレベルト1以上であることを検出す
る比較器04)とレベルト2以下であることを検出する
比較器αOを取付ける。このようにして両者の矩形波信
号の排他的論理和を排他的論理和回路OQ、0η、08
)で収れば、信号の有無にかかわらず機器(この場合は
送信周波数変換器(2)および電力増幅器(3))の異
常を検出することができる。
Install diode detector αV and DC amplifier θ,
A comparator 0■ is connected to this so that a rectangular wave corresponding to the input burst signal can be obtained. On the other hand, a comparator 04) for detecting that the level is 1 or more and a comparator αO for detecting that the level is 2 or less are attached to the signal detection circuit on the output side of the transmitter. In this way, the exclusive OR circuit OQ, 0η, 08
), it is possible to detect an abnormality in the equipment (in this case, the transmission frequency converter (2) and the power amplifier (3)) regardless of the presence or absence of the signal.

σ9は入力信号Aの立上り時に出力信号Bが存在するか
否かを判断できるよう入力信号Aを遅延させる遅延回路
である。比較器α優、αGは演算増幅器を用いて簡単に
構成できる。
σ9 is a delay circuit that delays the input signal A so that it can be determined whether the output signal B exists at the rising edge of the input signal A. Comparators αY and αG can be easily configured using operational amplifiers.

OQおよびα力は通常のエツジトリガ形Dフリップフロ
ップ回路でT端子への入力の立上り時にD端子がHレベ
ルなら出力り端子もHレベルとなる回路、翰は遅延回路
で、通常単安定マルチバイブレ−タ等を利用して構成さ
れる。08)はOR回路であり、排他的論理和が成立し
たときは、このOR回路から警報信号が出力される。
The OQ and α forces are normal edge-trigger type D flip-flop circuits, and if the D terminal is at H level when the input to the T terminal rises, the output terminal also goes to H level. It is constructed using data such as data. 08) is an OR circuit, and when the exclusive OR is established, an alarm signal is output from this OR circuit.

第4図は第8図の各部分の波形説明図でこれを用いて第
8図の回路の働きを説明する。
FIG. 4 is a waveform explanatory diagram of each part of FIG. 8, and the operation of the circuit of FIG. 8 will be explained using this diagram.

第4図(a)で示される入力信号Aは比較器03で矩形
波に変換され、遅延回路00により遅延され、(b)で
示される波形となる。第4図(c)で示される出力信号
Bについては図示のようにt、 t2間の伝送は正常だ
が、伝送異常により1314間ではレベルが低下し、t
5t6間ではレベルが高くなり過ぎたとする。
The input signal A shown in FIG. 4(a) is converted into a rectangular wave by the comparator 03 and delayed by the delay circuit 00, resulting in the waveform shown in FIG. 4(b). Regarding the output signal B shown in FIG. 4(c), the transmission between t and t2 is normal as shown in the diagram, but due to transmission abnormality, the level decreases between 1314 and t.
It is assumed that the level becomes too high between 5t6.

このような場合、出力信号Bは(a)に示すレベルL1
のとき出力する比較器αΦとレベルト2以上のとき出力
する比較器(1Gにより各々(e) 、 ’ (f)の
ように波形変換される。時間t、 t2における伝送異
常の有無の判断は遅延された入力信号の立上り時t12
においてDフリップフロップ回路Qf19.α力に出力
があるかどうかにより判断される。Dフリップフロップ
α力のQ出力を(g)に00の4出力を(h)に示す。
In such a case, the output signal B is at the level L1 shown in (a).
The comparator αΦ outputs when the level is 2 or higher, and the comparator outputs when the level is 2 or higher (1G converts the waveforms as shown in (e) and '(f), respectively. Judgment of the presence or absence of transmission abnormality at times t and t2 is delayed. At the rising edge of the input signal t12
In D flip-flop circuit Qf19. It is judged by whether or not there is an output in α force. The Q output of the D flip-flop α force is shown in (g), and the 4 outputs of 00 are shown in (h).

時間t1.t2においては比較器αaは出力しているの
でDフリップフロップαQのQ出力はLレベルとなり、
比較器αOは出力していないのでDフリップフロップα
力のQ出力はLレベルとなり、OR回路(ト)の出力は
Lレベルとなる。
Time t1. At t2, the comparator αa is outputting, so the Q output of the D flip-flop αQ becomes L level,
Comparator αO is not outputting, so D flip-flop α
The Q output of the power becomes L level, and the output of the OR circuit (G) becomes L level.

時間t3t4においては比較器Q41.Qυは出力して
いないので入力信号の立上り時t34においてDフリッ
プフロップ0すのQ出力はHレベル、Dフリップフロッ
プ<171の出力はLレベルとなり、OR回路(ト)か
ら警報信号が出力される。t、 t6間においては比較
器Q4)、Q5)はともに出力しているので入力信号の
立上り時t56においてDフリップフロップ0QのQ出
力はLレベル、Dフリップフロップα力の出力はHレベ
ルとなり、OR回路(ハ)から警報信号が出力される。
At time t3t4, comparator Q41. Since Qυ is not output, at t34 when the input signal rises, the Q output of D flip-flop 0 becomes H level, the output of D flip-flop <171 becomes L level, and an alarm signal is output from the OR circuit (G). . Between t and t6, comparators Q4) and Q5) both output, so at t56 when the input signal rises, the Q output of the D flip-flop 0Q becomes L level, and the output of the D flip-flop α becomes H level. An alarm signal is output from the OR circuit (c).

上記はOR回路(ト)を用いて警報出力としているがフ
リップフロップ回路αQ、αカの各出力をそのまま用い
れば、レベルHgh又はLoWの区別をして警報出力を
出すことも出来る。
In the above example, an OR circuit (G) is used to generate an alarm output, but if the outputs of the flip-flop circuits αQ and αF are used as they are, an alarm output can be output by distinguishing between levels Hgh and LowW.

以上説明したように本回路を用いれば、入力の信号の立
上り後一定時間後において、出力の信号のレベルが一定
の範囲内かどうかを判定する為、入力される信号のバー
スト長(パルス巾)やその間隔に影響されず、極めて容
易に正常、異常の判定を下すことができ、かつ通常用い
られる外部よりのキャリア0N10FF信号(ゲート信
号)も不要であるという特長がある。
As explained above, if this circuit is used, the burst length (pulse width) of the input signal can be used to determine whether the level of the output signal is within a certain range after a certain period of time after the rise of the input signal. It has the advantage that it is possible to very easily determine whether it is normal or abnormal without being affected by the distance between the two, and there is no need for the normally used carrier 0N10FF signal (gate signal) from the outside.

また、以上の説明はもっばらTDMA信号を例として説
明したが、音声の有無によってキャリアが断/接される
5CPCのようなシステム又変調器のキャリア0N10
 F F回路の検出等にも有効である。
In addition, although the above explanation has mainly been made using TDMA signals as an example, it is also possible to use a system such as 5CPC where the carrier is disconnected/connected depending on the presence or absence of voice, or the carrier 0N10 of the modulator.
It is also effective for detecting FF circuits.

〔発明の効果〕〔Effect of the invention〕

この発明は伝送回路の出力信号のレベルが一定の範囲内
かどうかを検出したうえで入力信□号との排他的論理和
により、障害を検出するようにしたので、バースト状の
信号が伝送される回路の障害を容易にしかも簡単な回路
構成で精度良く検出できる効果がある。
This invention detects whether the level of the output signal of the transmission circuit is within a certain range and then performs an exclusive OR with the input signal □ to detect a fault, so that burst signals are not transmitted. This has the effect that failures in circuits can be easily detected with high accuracy using a simple circuit configuration.

更に□、入力信号の立上り信号により他方の信号が存在
する1か否かによって、排他的論理和を構成すれば、誤
判断がなくなるという効果がある。
Furthermore, if an exclusive OR is formed depending on whether the other signal is 1 or not depending on the rising edge of the input signal, there will be no erroneous judgment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の信号検出回路の例、第2図は本発明の原
理を示す波形説明図、第8図は本発明による信号検出回
路の一実施例、第4図は第8図の波形説明図である。 図において、(2)は周波数変換器、(3)は電力増幅
器、(5)、αQは方向性結合器、(6) 、 (11
)は検波器、Q椴。 04)、Qυは比較器、0す、α力はDフリップフロッ
プ回路、に)はOR回路、θ旧よ遅延回路である。 各図中の同一符号は同−又は相当部分を示す。 代理人 大岩増雄 第1図 第2図 第4図 り 手続補正書(自発) 1、事件の表示 特願昭59−49788号3、補正を
する者 代表者片山仁八部 5、補正の対象 (1)図面 6、補正の内容 (])図面の第8図を別紙のとおり訂正する。 7、 添付書類の目録 (1)図面 1通 以上 101−
Fig. 1 is an example of a conventional signal detection circuit, Fig. 2 is a waveform explanatory diagram showing the principle of the present invention, Fig. 8 is an embodiment of the signal detection circuit according to the present invention, and Fig. 4 is the waveform of Fig. 8. It is an explanatory diagram. In the figure, (2) is a frequency converter, (3) is a power amplifier, (5), αQ is a directional coupler, (6), (11
) is the detector, Q-sen. 04), Qυ is a comparator, 0, α is a D flip-flop circuit, 2) is an OR circuit, and θ is a delay circuit. The same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 4 Draft procedure amendment (voluntary) 1. Indication of case Japanese Patent Application No. 59-49788 3. Person making the amendment Representative Hitoshi Katayama 5. Subject of amendment (1) ) Drawing 6, contents of amendment (]) Figure 8 of the drawings is corrected as shown in the attached sheet. 7. List of attached documents (1) Drawings 1 or more 101-

Claims (2)

【特許請求の範囲】[Claims] (1)バースト状の信号波を伝送する無線通信機器の出
力信号が第1のレベルL1より大であることを検出する
第1の比較器と、前記出力信号が第2のレベルL2 (
L2> Lt )より大であることを検出する第2の比
較器と、前記無線通信機器の入力信号を波形整形する第
8の比較器と、この第8の比較器の出力の立上り時に前
記第1および第2の比較器の出力を判定する回路とを備
えた障害検出回路。
(1) A first comparator that detects that an output signal of a wireless communication device that transmits a burst signal wave is higher than a first level L1, and a first comparator that detects that the output signal is higher than a first level L2 (
a second comparator that detects that the input signal of the wireless communication device is larger than L2>Lt); and a circuit for determining the outputs of the first and second comparators.
(2)無線通信機器が周波数変換器又は増幅器を含むも
のであることを特徴とする特許請求の範囲第1項記載の
障害検出回路。
(2) The fault detection circuit according to claim 1, wherein the wireless communication device includes a frequency converter or an amplifier.
JP59049733A 1984-01-18 1984-03-13 Fault detecting circuit Granted JPS60192434A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59049733A JPS60192434A (en) 1984-03-13 1984-03-13 Fault detecting circuit
US06/687,761 US4658206A (en) 1984-01-18 1984-12-31 Fault detector for communications equipment using exclusive or circuitry
DE19853500896 DE3500896A1 (en) 1984-01-18 1985-01-12 FAULT DISPLAY DEVICE FOR TRANSMISSION ROUTES WITH BURST SIGNAL INSERTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59049733A JPS60192434A (en) 1984-03-13 1984-03-13 Fault detecting circuit

Publications (2)

Publication Number Publication Date
JPS60192434A true JPS60192434A (en) 1985-09-30
JPH0349220B2 JPH0349220B2 (en) 1991-07-26

Family

ID=12839389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59049733A Granted JPS60192434A (en) 1984-01-18 1984-03-13 Fault detecting circuit

Country Status (1)

Country Link
JP (1) JPS60192434A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9266319B2 (en) 2010-11-04 2016-02-23 Yugengaisha Misatomirai21 Printing device using endless belt-shaped printing plate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9266319B2 (en) 2010-11-04 2016-02-23 Yugengaisha Misatomirai21 Printing device using endless belt-shaped printing plate

Also Published As

Publication number Publication date
JPH0349220B2 (en) 1991-07-26

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