KR0174669B1 - Failure Detection Device in Sept Transmission Equipment - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION The invention described in the claims belongs to: A device for detecting a disturbance occurring in a sept transmission device.

2. Technical problem to be solved by the invention: a fault detection circuit for detecting a fault generated during the optical communication line or MUX conversion to the processor and a processor for receiving and managing the fault history transmitted from the fault detection circuit at regular intervals In the conventional failure detection apparatus, when a failure occurs between read time periods, the failure history is lost, and thus there is a problem that the user cannot be notified of the failure.

3. Summary of the Solution of the Invention: A fault detection circuit that detects a fault occurrence in the Sept transmission device and transmits a fault history, and a fault that maintains and transmits the fault history transmitted from the fault detection circuit until a lead time occurs. And a processor for managing a fault history read after reading the fault history transmitted from the fault storage circuit at a lead time having a predetermined period.

4. Significant use of the invention: sept transmission equipment.

Description

Failure Detection Device in Sept Transmission Equipment

Figure 1 is a block diagram of a typical sept transmission equipment.

2 is a block diagram of a conventional failure detection apparatus.

3 is a failure history diagram detected by a conventional failure detection apparatus.

4 is a block diagram of a failure detection apparatus according to the present invention.

5 is a failure history detected by the failure detection apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: optical system 11: MUX system

12 processor 13 fault collection system

14: W / S 20: Fault detection circuit

40: fault storage circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a septum transmission device, and more particularly, to a failure detection device that accurately detects a failure when a hardware failure occurs.

In general, the septal transmission is a European postal equivalent to the telecommunication standardization body in Europe. Signaling device as defined by the Conference of European Postal and Telecom munications Administrations (CEPT).

The general configuration of thecept transmitter is as shown in FIG. Referring to FIG. 1, the optical system 10 converts an optical signal received by being connected to an optical cable into an electrical signal by photoelectric conversion or by converting the electrical signal into an optical signal by converting the optical signal into an optical signal. Say. The MUX system 11 transmits data in a frequency band division or time division scheme or the like when multiple transmissions are performed using one broadband transmission path for transmitting data. The processor 12 primarily collects the failures generated in the optical system 10 and the MUX system 11. The fault collection system 13 collectively collects the fault details collected by the processor 12 first. The W / S 14 receives the failure details generated in the optical system 10 and the MUX system 11 from the processor 12 and processes them graphically so that the failure occurrence details can be confirmed.

Conventionally, the configuration of the failure detecting apparatus is as shown in FIG. Referring to FIG. 2, the fault detection circuit 20 detects a fault generated during an optical communication line or MUX conversion and transmits the fault to the processor 12. The fault transmission in the fault detection circuit 20 transmits a high signal when a fault occurs with a read time input from the processor 12 and a low signal when there is no fault or is released. .

For example, the result of the failure detected by the fault detection apparatus of FIG. 2 is as shown in FIG.

Referring to FIG. 2 and FIG. 3, a failure detection process is detected by the failure detection circuit 20. The failure history transmitted by the failure detection circuit 20 is read time. It is read and managed by the processor 12 in cycles.

In the read time of step 310 of FIG. 3, the processor 12 detects a fault transmitted from the fault detection circuit 20 through a bus. The processor 12 records and manages the detected a fault. In addition, in step 312, the processor 12 detects the d fault transmitted from the fault detection circuit 20 through the d bus, and releases the a fault detected in step 310. The processor 12 records and manages the detected d failure.

However, the processor 12 does not detect the b failure transmitted from the fault detection circuit 20 through the b bus between steps 314 and 316, a read time of step 316, and detects it in step 312 in step 314. Release the fault. In operation 318, the next read time, a failure transmitted through the a bus is detected and managed as data. As a result, the processor 12 recognizes that b failure has not occurred in the failure detection process, and finally does not transmit the occurrence of b failure to the failure collection system 13 shown in FIG.

As described above, in the conventional failure detection apparatus, when a failure occurs between read time periods, the failure history is lost, and thus there is a problem that the user cannot be notified of the failure.

Accordingly, an object of the present invention is to provide a failure detection apparatus that maintains a failure history until a read time occurs when a failure occurs.

The present invention for achieving the above object is characterized in that it comprises a fault storage circuit for maintaining the fault history until the processor reads the fault history generated in the fault detection circuit.

Hereinafter, the present invention will be described in detail with reference to the attached drawings.

The configuration of the fault detection apparatus for carrying out the present invention is as shown in FIG. Referring to FIG. 4, the failure detection circuit 20 detects a failure and transmits a failure history through the buses a, b, c, and d. The fault keeping circuit 40 transmits fault details transmitted from the fault detecting circuit 20 through buses a, b, c, and d through buses a ', b', c ', and d'. Until the set pulse for changing the fault history is transmitted from the processor 12, the fault history of the high level for notifying the occurrence of the fault is maintained. When the set pulse is transmitted, the stored fault history is changed to a low level. The processor 12 is provided through the buses a ', b', c ', and d' from the fault keeping circuit 40 at a read time generated according to a read time period. The fault details are managed by data, and when the fault details are transmitted, a set pulse for setting the fault details maintained in the fault storage circuit 40 is transmitted. The fault detection circuit 20 and the fault storage circuit 40 are embedded in the optical system 10 or the MUX system 11 shown in FIG. The processor 12 is identical to the processor shown in FIG.

For example, the result of the fault detected by the fault detecting apparatus of FIG. 4 is as shown in FIG.

Therefore, an embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

The processor 12 detects that there is no fault history from the fault storage circuit 40 at the read time of step 510 of FIG. 5. However, the fault keeping circuit 40 receives a fault from the fault detection circuit 20 through the a bus after the read time of step 510 occurs, and transmits a fault level of the high level through the a 'bus. Done. The processor 12 reads a fault history transmitted from the fault storage circuit 40 at a read time of step 512 to form a data, and manages a set pulse. Set the fault history that is being transmitted and maintained at low level. The fault keeping circuit 40 receives b faults from the fault detection circuit 20 through the b buses after the read time of step 512 has occurred, and b faults of the high level b faults. Will be sent through. The processor 12 reads b error history transmitted from the fault storage circuit 40 at a read time in step 514 to data and manages the set fault, and sets the fault pulse to the fault storage circuit 40. Set the fault history that is being transmitted and maintained at low level.

In addition, the processor 12 detects that there is no fault history from the fault storage circuit 40 at the read time of step 516, and releases the fault history transmitted in step 514. The fault storage circuit 40 receives b, c, d faults from the fault detection circuit 20 through the b, c, d buses after the read time of the step 516 occurs, and then b of high level b. , c, d faults are transmitted through the b ', c', and d 'buses, respectively. The processor 12 reads b, c, and d failure details transmitted from the fault keeping circuit 40 at a read time in step 518 and manages them by data, and sets a set pulse to the fault. The fault history, which is transmitted to the storage circuit 40 and held, is set at a low level. In addition, the fault storage circuit 40 receives b, d faults from the fault detection circuit 20 through the b, d buses after the read time of the step 518 occurs, b, d faults of a high level. The details are transmitted via the b 'and d' buses. The processor 12 reads b and d failure details transmitted from the fault storage circuit 40 at a read time of step 520 to data and manages them, and sets a set pulse in the fault storage circuit. The fault history, which is transmitted to 40, is held at low level.

The fault keeping circuit 40 receives b faults from the fault detection circuit 20 through the b buses after the read time of the step 520 occurs, and then checks the b faults of the high level b faults. Will be sent through. The processor 12 reads b error history transmitted from the fault storage circuit 40 at a read time of step 522 and manages it by data, and sets a set pulse to the fault storage circuit 40. Set the fault history that is being transmitted and maintained at low level.

As described above, the present invention has an effect of allowing the user to cope with the occurrence of a failure by completely transmitting the generated failure details even when the failure occurs aperiodically.

Claims (2)

A failure detection apparatus for detecting a failure occurring in an optical communication line or a MUX in acept transmission device, comprising: a failure detection circuit for detecting a failure and transmitting a failure history, and a lead time for the failure history transmitted from the failure detection circuit; And a processor for maintaining and transmitting the fault history, which is maintained until the fault is stored, and a fault history read after the fault history transmitted from the fault storage circuit is read at a lead time having a predetermined period. The method of claim 1, wherein the processor reads the fault history maintained in the fault storage circuit in response to the occurrence of a lead time and transmits a set pulse for setting the fault history maintained in the fault storage circuit to the fault storage circuit. Failure detection device characterized in that.