KR970072798A - Failure detection device in acept transfer device - Google Patents

Failure detection device in acept transfer device Download PDF

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Publication number
KR970072798A
KR970072798A KR1019960010805A KR19960010805A KR970072798A KR 970072798 A KR970072798 A KR 970072798A KR 1019960010805 A KR1019960010805 A KR 1019960010805A KR 19960010805 A KR19960010805 A KR 19960010805A KR 970072798 A KR970072798 A KR 970072798A
Authority
KR
South Korea
Prior art keywords
fault
failure
history
detection circuit
processor
Prior art date
Application number
KR1019960010805A
Other languages
Korean (ko)
Other versions
KR0174669B1 (en
Inventor
윤일혁
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019960010805A priority Critical patent/KR0174669B1/en
Publication of KR970072798A publication Critical patent/KR970072798A/en
Application granted granted Critical
Publication of KR0174669B1 publication Critical patent/KR0174669B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/15—Performance testing
    • H04B17/17—Detection of non-compliance or faulty performance, e.g. response deviations

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. Technical field to which the invention described in the claims belongs

셉트 전송장비에서 발생되는 장애를 검출하는 장치A device for detecting faults occurring in acept transfer device

2. 발명이 해결하려고 하는 기술적 과제2. Technical Challenges to be Solved by the Invention

광통신 선로 또는 MUX변환 중 발생되는 장애를 검출하여 프로세서로 전송하는 장애검출회로와, 상기 장애 검출회로로부터 전송되는 장애 내역을 일정 주기로 전송받아 관리하는 프로세서로 구성되는 종래의 장애 검출 장치에서는 장애가 리드타임(Read Time) 주기 사이에 발생되는 경우에는 장애 내역을 잃어버리게 되어 사용자에게 장애 발생을 알리지 못하는 문제가 있었다.A fault detection circuit for detecting a fault occurring during an optical communication line or MUX conversion and transmitting the detected fault to the processor and a processor for receiving and managing the fault history transmitted from the fault detection circuit at a constant cycle, (Read Time) cycle, the trouble history is lost, and the user is not notified of the occurrence of the trouble.

3. 발명의 해결방법의 요지3. The point of the solution of the invention

셉트 전송장비에서 장애 발생을 검출하여 장애 내역을 전송하는 장애검출회로와, 상기 장애검출회로로부터 전송된 장애 내역을 리드 타임이 발생될 때까지 유지하여 전송하는 장애보관회로와, 일정주기를 가지는 리드 타임에 상기 장애보관회로로부터 전송되는 장애 내역을 읽어들인 후 읽어 들인 장애 내역을 관리하는 프로세서로 구성되는 장애 검출 장치.A failure detection circuit for detecting a failure occurrence in the accept transfer device and transmitting the failure breakdown; a failure storage circuit for maintaining and transmitting the failure history transmitted from the failure detection circuit until a lead time occurs; And a processor for reading the fault details transmitted from the fault storage circuit at the time and managing the fault details read.

4. 발명의 중요한 용도4. Important Uses of the Invention

셉트 전송장비Accept transfer equipment

Description

셉트 전송장비에서 장애 검출장치.Failure detection device in acept transfer equipment.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제4도는 본 발명에 따른 장애 검출장치의 블럭 구성도, 제5도는 본 발명에 따른 장애 검출장치에 의해 검출되는 장애 내역도.FIG. 4 is a block diagram of a fault detection apparatus according to the present invention; FIG. 5 is a fault history chart detected by the fault detection apparatus according to the present invention; FIG.

Claims (2)

셉트 전송장비에서 광통신선로 또는 MUX에서 발생되는 장애를 검출하는 장애 검출장치에 있어서, 장애 발생을 검출하여 장애 내역을 전송하는 장애검출회로와, 상기 장애 검출회로로부터 전송된 장애 내역을 리드타임이 발생될 때까지 유지하여 전송하는 장애보관회로와, 일정주기를 가지는 리드타임에 상기 장애보관회로로부터 전송되는 장애 내역을 읽어들인 후 읽어들인 장애 내역을 관리하는 프로세서로 구성됨을 특징으로 하는 장애검출장치.A fault detection apparatus for detecting a fault occurring in an optical communication line or MUX in acept transfer apparatus, the fault detection apparatus comprising: a fault detection circuit for detecting a fault occurrence and transmitting a fault history; And a processor for reading the fault history transmitted from the fault storage circuit at a lead time having a predetermined period and managing the read fault history. 제1항에 있어서, 상기 프로세서는 리드타임 발생에 대응하여 상기 장애보관회로에서 유지되는 장애 내역을 읽어들인 후 상기 장애보관회로에서 유지되는 장애 내역을 세트하는 세트펄스를 상기 장애보관회로로 전송함을 특징으로 하는 장애 검출 장치.2. The fault management system according to claim 1, wherein the processor reads a fault history held in the fault storage circuit in response to the occurrence of a lead time, and then transmits a set pulse to the fault storage circuit to set a fault history maintained in the fault storage circuit The fault detection apparatus comprising: ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010805A 1996-04-10 1996-04-10 Failure Detection Device in Sept Transmission Equipment KR0174669B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960010805A KR0174669B1 (en) 1996-04-10 1996-04-10 Failure Detection Device in Sept Transmission Equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960010805A KR0174669B1 (en) 1996-04-10 1996-04-10 Failure Detection Device in Sept Transmission Equipment

Publications (2)

Publication Number Publication Date
KR970072798A true KR970072798A (en) 1997-11-07
KR0174669B1 KR0174669B1 (en) 1999-04-01

Family

ID=19455438

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960010805A KR0174669B1 (en) 1996-04-10 1996-04-10 Failure Detection Device in Sept Transmission Equipment

Country Status (1)

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KR (1) KR0174669B1 (en)

Also Published As

Publication number Publication date
KR0174669B1 (en) 1999-04-01

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