JPS60192334A - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPS60192334A
JPS60192334A JP4757984A JP4757984A JPS60192334A JP S60192334 A JPS60192334 A JP S60192334A JP 4757984 A JP4757984 A JP 4757984A JP 4757984 A JP4757984 A JP 4757984A JP S60192334 A JPS60192334 A JP S60192334A
Authority
JP
Japan
Prior art keywords
etching
insulating film
gas
cross
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4757984A
Other languages
Japanese (ja)
Inventor
Kazuo Matsuzaki
松崎 一夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP4757984A priority Critical patent/JPS60192334A/en
Publication of JPS60192334A publication Critical patent/JPS60192334A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to bring the shape of etching cross-section of an insulating film into an arbitrarily and easily controllable state using a cylindrical plasma etching device by a method wherein the amount of side etching given to the film to be etched is controlled by the partial voltage ratio of the inert gas for reaction gas. CONSTITUTION:When a microscopic work is going to be performed on the insulating film consisting of a poly silicon film, a silicon nitride film, a silicon nitride film and the like using a cylindrical plasma etching device, the partial voltage ratio of dilute gas with Freon gas is brought to 1 or above by performing an etching wherein dilute gas is mixed to Freon gas, for example, if said insulating film is to be formed in the vertical cross-sectional form same as the size of photoresist coated on the insulating film. Also, when an inclination is given to the cross-sectional form of the insulating film for the purpose of preventing generation of an unsatisfactory step coverage, a plasma etching is performed in the state wherein the partial voltage ratio is brought to 1 or below. Through the above-mentioned procedures, the cross-sectional form after etching performed on the insulating film can be determined arbitrarily.

Description

【発明の詳細な説明】 r発明の属する技術分野〕 本発明は半導体素子に設けられる絶縁膜などの薄膜を微
細加工するドライエツチング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field to Which the Invention Pertains The present invention relates to a dry etching method for finely processing thin films such as insulating films provided on semiconductor devices.

〔従来技術とその問題点〕[Prior art and its problems]

例えば集積度の高い半導体集積回路などでは微細なパタ
ーンを形成するための微細加工法とじてエツチング技術
の向上が期待されている。このエツチング過程は一般に
例えば第1図に断面図で示すようにシリコン基板lの表
面に絶縁膜2を設け、その上にフォトレジスト3による
バターニングを行いレジスト3をマスクとして絶縁膜2
の不要部分をエツチング除去することが行われており、
エツチングの方法は化学溶液を用いて化学反応を利用す
るウェットエツチングまたは減圧された容器内でガスを
高周波で放電させてラジカルで行うドライエツチングが
ある。
For example, improvements in etching technology are expected as a microfabrication method for forming fine patterns in highly integrated semiconductor integrated circuits. Generally, in this etching process, an insulating film 2 is provided on the surface of a silicon substrate 1, as shown in the cross-sectional view in FIG.
Etching is performed to remove unnecessary parts of the
Etching methods include wet etching, which utilizes a chemical reaction using a chemical solution, and dry etching, which uses radicals by discharging gas at high frequency in a reduced pressure container.

しかしウェットエツチングはエツチングされる絶縁膜2
の縦方向と横方向へのエツチング速さがいずれの方向に
もほぼ同じ割合で進行するので第2図に断面図で示すよ
うに絶縁膜2はシリコン基板1に対して断面形状が台形
状になりやすく、アンダカットされてレジスト3の寸法
より小さな仕上りとなる。これに対し、シリコンウェハ
の大口径化に伴いエツチング加工精度、エツチングの均
一性などにすぐれたドライエツチング法が多用されるよ
うになった。ドライエツチングは例えば第3図に要部断
面図を示した円筒形プラズマエツチング装置が用いられ
る。第3図においてプラズマ保護用石英管4内のエッチ
トンネル5を介シてウェハボート6に支持されたウェハ
7が配置され、石英管4の外周に設けられた高周波電極
8からの高周波出力により反応ガス人口9から導入され
る例えば酸素を含むフレオンCCFa)ガスの弗素が活
性ラジカルとなりウェハ7がエツチングされるが、この
方法もウェットエツチングの場合と同様に、マスク材の
端から横方向へエツチングが大きく食い込み微細パター
ンの形成には問題がある。
However, in wet etching, the insulating film 2 to be etched is
Since the etching speed in the vertical and horizontal directions progresses at approximately the same rate in both directions, the insulating film 2 has a trapezoidal cross-sectional shape with respect to the silicon substrate 1, as shown in the cross-sectional view of FIG. This tends to cause undercutting, resulting in a finished product that is smaller than the resist 3 dimension. On the other hand, with the increase in the diameter of silicon wafers, dry etching methods, which are superior in etching accuracy and etching uniformity, have come into widespread use. For dry etching, for example, a cylindrical plasma etching apparatus whose main part is shown in cross section in FIG. 3 is used. In FIG. 3, a wafer 7 supported by a wafer boat 6 is placed through an etch tunnel 5 in a quartz tube 4 for plasma protection, and is reacted by high frequency output from a high frequency electrode 8 provided on the outer periphery of the quartz tube 4. For example, the fluorine of the freon (CCFa) gas containing oxygen, which is introduced from the gas port 9, becomes active radicals and etches the wafer 7, but in this method, as in the case of wet etching, etching is performed laterally from the edge of the mask material. There is a problem in forming a fine pattern with large intrusion.

この問題を回避するためにエツチングに異方性をもたせ
ることができ、フォトレジストの寸法通りサイドエツチ
ングが少ない平行平板形の反応性イオンエツチングも行
われている。例えば第4図はこの平行平板形の反応性イ
オンエツチング装置の要部断面図を示したものであり、
反応容器10の中に高周波電極11と被エツチングウェ
ハ12を対向せしめ反応ガス人口13からエツチングガ
スを導入して高周波電圧を印加することによりウェハ1
2のエツチングが行われる。
In order to avoid this problem, etching can be made anisotropic, and parallel plate type reactive ion etching has also been carried out, which causes less side etching in accordance with the dimensions of the photoresist. For example, FIG. 4 shows a cross-sectional view of the main parts of this parallel plate type reactive ion etching apparatus.
The high-frequency electrode 11 and the wafer to be etched 12 are placed opposite each other in the reaction vessel 10, and an etching gas is introduced from the reaction gas port 13, and a high-frequency voltage is applied to the wafer 1.
2 etching is performed.

しかしながらこのドライエツチング方法は、エツチング
後第5図に示すように例えばシリコン基板1に設けたポ
リシリコン酸化膜2はフォトレジスト3直下で垂直にエ
ツチングされるが、その後の工程でレジスト3を除去し
、配線金属膜14を被着したとき第6図のようなステッ
プカバレージ不ツチング方式は従来のプラズマエツチン
グ装置と同様な早扱いができるという点はあっても例え
ば円筒形プラズマエツチングに比べて処理能力が%とな
り、絶縁膜のサイドエツチング量の制御がむずかしいな
どの欠点をもっている。
However, in this dry etching method, as shown in FIG. 5, after etching, for example, the polysilicon oxide film 2 provided on the silicon substrate 1 is vertically etched directly under the photoresist 3, but the resist 3 is removed in the subsequent process. When the wiring metal film 14 is deposited, the step coverage etching method as shown in FIG. 6 can be used as quickly as a conventional plasma etching device, but it has a lower throughput than, for example, cylindrical plasma etching. %, and it has drawbacks such as difficulty in controlling the amount of side etching of the insulating film.

r発明の目的〕 本発明の目的は上述の欠点を除去し、円筒形のプラズマ
エツチング装置を用いて絶縁膜のエツチング断面形状を
任意にしかも容易に行うことができるドライエツチング
方法を提供することにある。
OBJECT OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a dry etching method that allows etching of an insulating film to any desired cross-sectional shape using a cylindrical plasma etching device and easily. be.

r発明の要点〕 本発明は円筒形のプラズマエツチング装置を用いポリシ
リコンや窒化シリコン膜などからなる絶縁膜を微細加工
するに際して、これら絶縁膜に塗布したフォトレジスト
寸法通りの垂直な断面形状をもつように形成するときは
フレオンガスに希ガスを混合したエツチングガスを用い
てフレオンガスに対する希ガスの分圧比を1以上にし、
またステップカバレージ不良を防止するために絶縁膜の
断面形状に傾斜をもたせるときはエツチングガスの分圧
比を1以下としてプラズマエツチングを行うことにより
、絶縁膜のエツチング後の断面形状を任意に定めること
ができるようにしたものである。
[Summary of the Invention] The present invention uses a cylindrical plasma etching device to finely process insulating films made of polysilicon, silicon nitride, etc., so that the photoresist coated on these insulating films has a vertical cross-sectional shape that matches the dimensions. When forming as shown in FIG.
Furthermore, when the cross-sectional shape of the insulating film is made to have a slope in order to prevent defective step coverage, by performing plasma etching with the partial pressure ratio of the etching gas set to 1 or less, the cross-sectional shape of the insulating film after etching can be determined arbitrarily. It has been made possible.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.

まずシリコン基板の表面に厚さ0.5μmのポリシリコ
ン絶縁膜を形成し、この絶縁膜の所定の個所にフォトレ
ジストを塗布した後、これを円筒形プラズマエツチング
装置に装入して、例えば4%の酸g(02)を含むフレ
オン(CF4)カスにヘリ(5) ラム(He)ガスを混合した反応ガスを装置内に導入し
フレオンガスに対するヘリウムガスの分圧比を変化させ
この分圧比とサイドエッチ量との関係をめた。サイドエ
ッチ量は第7図に第2図と同じ断面図を昇揚して示した
通り、シリコン基板lとレジスト3の間に形成された絶
縁膜2の台形状の断面形状に関して底辺の長さtと上辺
の長さSとの差L−sをもって表わし第1表の結果を得
た。
First, a polysilicon insulating film with a thickness of 0.5 μm is formed on the surface of a silicon substrate, a photoresist is applied to predetermined locations on this insulating film, and then the film is loaded into a cylindrical plasma etching device. A reaction gas, which is a mixture of Freon (CF4) gas containing % of acid g(02) and Helium (He) gas, is introduced into the apparatus, and the partial pressure ratio of helium gas to Freon gas is changed, and this partial pressure ratio and side We looked at the relationship between the amount of sex. The side etch amount is determined by the length of the base of the trapezoidal cross-sectional shape of the insulating film 2 formed between the silicon substrate 1 and the resist 3, as shown in FIG. The results shown in Table 1 were obtained by expressing the difference L-s between t and the length S of the upper side.

なおtはジャストエッチのためレジスト3の巾寸法とほ
ぼ同じである。第1表中Xは4インチ径のシリコン基板
内5点についての平均値である。
Note that t is approximately the same as the width of the resist 3 due to just etching. In Table 1, X is the average value for five points within a 4-inch diameter silicon substrate.

第1表 第1表からフレオンガスに対するヘリウムガスの分圧比
が高くなるにしたがってエツチング速度は遅くなるがサ
イドエッチ量は減少することがわかる。とくに分圧比が
1を超えるとサイドエヴチ(6) 量は大巾に減少するようになる。したがってフレオンガ
スに対するヘリウムガスの分圧比が冒まるにつれてエツ
チング後の絶縁膜の傾斜角度は急峻となるがこの傾斜角
度は所定の膜厚に対して分圧比とサイドエッチ量から見
積ることができるのでこのこと力)らレジスト寸法通り
の微細加工を行うことが可能となる。第1表の結果につ
いてフレオンガスに対するヘリウムガスの分圧比と絶縁
膜の傾斜角度の関係を第8図に示す。
From Table 1, it can be seen that as the partial pressure ratio of helium gas to Freon gas increases, the etching rate slows down, but the amount of side etching decreases. In particular, when the partial pressure ratio exceeds 1, the side effect (6) amount begins to decrease significantly. Therefore, as the partial pressure ratio of helium gas to Freon gas increases, the inclination angle of the insulating film after etching becomes steeper; however, this inclination angle can be estimated from the partial pressure ratio and side etching amount for a given film thickness. It becomes possible to carry out microfabrication according to the resist dimensions from (force). Regarding the results shown in Table 1, FIG. 8 shows the relationship between the partial pressure ratio of helium gas to Freon gas and the inclination angle of the insulating film.

なおフレオンガスに混合する布カスには本実施例におい
てはヘリウムを用いた場合を述べたが、ヘリウムに限ら
れることなく、例えばアルゴン(Ar)などその他の不
活性ガスを用いても同様の結果が得られる。
In this example, helium was used as the cloth waste to be mixed with the Freon gas, but the same results can be obtained by using other inert gases such as argon (Ar), without being limited to helium. can get.

〔発明の効果〕〔Effect of the invention〕

半導体素子に設けられた絶縁膜などの微細加工を行うに
当り、円筒形プラズマエツチング装置を用いてドライエ
ツチングをするとき、従来サイドエッチ量が大きくなり
レジスト直下で基板に対して垂直なエツチングができず
そのため処理能力が低いlども拘らず、平行平板形のエ
ツチング装置が多用されているのに対し、本発明の方法
によれば円筒形プラズマエツチング装置を用いてエツチ
ングガスに希ガスを混合し、その分圧比を1以上にする
ことにより再現性よく平行平板形と同程度の垂直エツチ
ングが可能となるばかりでなく、エツチングガスの分圧
比を必要に応じて適当な値に定めることにより分圧比1
以下でレジスト直下の絶縁膜のエツチング角度を半導体
基板に対して傾斜をもたせるようにしてステップカバレ
ージ不良を避けることもできる。
When dry etching is performed using a cylindrical plasma etching device for microfabrication of insulating films and the like provided on semiconductor devices, conventionally the amount of side etching becomes large and etching perpendicular to the substrate cannot be performed directly under the resist. For this reason, parallel plate type etching equipment is often used despite its low processing capacity.However, according to the method of the present invention, a cylindrical plasma etching equipment is used and a rare gas is mixed with the etching gas. By setting the partial pressure ratio to 1 or more, it is not only possible to perform vertical etching with good reproducibility to the same degree as the parallel plate type, but also by setting the partial pressure ratio of the etching gas to an appropriate value as necessary, it is possible to achieve a partial pressure ratio of 1.
In the following, defective step coverage can be avoided by making the etching angle of the insulating film directly under the resist inclined with respect to the semiconductor substrate.

すなわち本発明の方法はエツチングガスと希ガスの分圧
比を適宜選択して被エツチング膜のサイドエッチ量を任
意に制御することかできるとともに円筒形プラズマエツ
チング装置を用いた量産効果も得られるものである。
That is, the method of the present invention allows the amount of side etching of the film to be etched to be arbitrarily controlled by appropriately selecting the partial pressure ratio of the etching gas and the rare gas, and also provides mass production effects using a cylindrical plasma etching apparatus. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体素子のエツチング前の部分的断面図、第
2図は同じくウェットエツチング後の部分的断面図、第
3図は円筒形プラズマエツチング装置の要部断面図、第
4図は平行平板形反応性イオンエツチング装置の要部断
面図、第5図は第4図の装置によるエツチング後の部分
的断面図、第6図はステップカバレージ不良を示す部分
的断面図、第7図はサイドエッチ量の説明図、第8図は
ガスの分圧比と絶縁膜の傾斜角度との関係を表ゎした線
図である。 1・・・シリコン基板、2・・・ポリシリコン絶縁膜、
3・・・フォトレジスト、14・・・配線金属。 う (9) 第1図 第2図 第3図 11 第4図 第5図 4 第6図
Fig. 1 is a partial cross-sectional view of a semiconductor element before etching, Fig. 2 is a partial cross-sectional view of the same after wet etching, Fig. 3 is a cross-sectional view of a main part of a cylindrical plasma etching apparatus, and Fig. 4 is a parallel plate. 5 is a partial sectional view after etching by the apparatus shown in FIG. 4, FIG. 6 is a partial sectional view showing poor step coverage, and FIG. 7 is a partial sectional view showing side etching. FIG. 8 is a graph showing the relationship between the gas partial pressure ratio and the inclination angle of the insulating film. 1... Silicon substrate, 2... Polysilicon insulation film,
3... Photoresist, 14... Wiring metal. (9) Figure 1 Figure 2 Figure 3 Figure 11 Figure 4 Figure 5 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】 l)プラズマエツチング装置を用い、反応ガスに不活性
ガスを混合して、半導体素子の微細パターンを加工する
方法において1反応ガスに対する不活性ガスの分圧比に
より、被エツチング膜のサイドエッチ量を制御すること
を特徴とするドライエツチング方法8 2、特許請求の範囲第1項記載の方法において、不活性
ガスは1−1eまたはArであることを特徴とするドラ
イエツチング方法。
[Scope of Claims] l) In a method of processing fine patterns of semiconductor devices by mixing an inert gas with a reactive gas using a plasma etching apparatus, the film to be etched is A dry etching method characterized by controlling the amount of side etching 82. A dry etching method according to claim 1, characterized in that the inert gas is 1-1e or Ar.
JP4757984A 1984-03-13 1984-03-13 Dry etching method Pending JPS60192334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4757984A JPS60192334A (en) 1984-03-13 1984-03-13 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4757984A JPS60192334A (en) 1984-03-13 1984-03-13 Dry etching method

Publications (1)

Publication Number Publication Date
JPS60192334A true JPS60192334A (en) 1985-09-30

Family

ID=12779157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4757984A Pending JPS60192334A (en) 1984-03-13 1984-03-13 Dry etching method

Country Status (1)

Country Link
JP (1) JPS60192334A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145575A (en) * 1977-05-25 1978-12-18 Hitachi Ltd Plasma etching method
JPS54125979A (en) * 1978-03-24 1979-09-29 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145575A (en) * 1977-05-25 1978-12-18 Hitachi Ltd Plasma etching method
JPS54125979A (en) * 1978-03-24 1979-09-29 Hitachi Ltd Manufacture of semiconductor device

Similar Documents

Publication Publication Date Title
US4676868A (en) Method for planarizing semiconductor substrates
US4256534A (en) Device fabrication by plasma etching
US4310380A (en) Plasma etching of silicon
EP0663690B1 (en) An ashing method for removing an organic film on a substance of a semiconductor device under fabrication
US4764245A (en) Method for generating contact holes with beveled sidewalls in intermediate oxide layers
JP3390814B2 (en) Method for etching object to be processed including oxide part or nitride part
US4522681A (en) Method for tapered dry etching
KR830000595B1 (en) Manufacturing method of semiconductor device
US4465552A (en) Method of selectively etching silicon dioxide with SF6 /nitriding component gas
US4615764A (en) SF6/nitriding gas/oxidizer plasma etch system
US6008139A (en) Method of etching polycide structures
US5522966A (en) Dry etching process for semiconductor
GB2069936A (en) Two-step plasma etching process
JPH05102107A (en) Manufacture of semiconductor device
JP2700316B2 (en) Organic material surface modification method
US6069087A (en) Highly selective dry etching process
JPS6356312B2 (en)
JPS60192334A (en) Dry etching method
JPS60120525A (en) Method for reactive ion etching
US4465553A (en) Method for dry etching of a substrate surface
JPS61131456A (en) Dry etching gas for silicon compound
JP2639402B2 (en) Oxide layer taper etching method
JPS5887276A (en) Treatment after dry etching
JPS6043829A (en) Dry etching method
JPH0253513B2 (en)