JPS60191519A

JPS60191519A - Josephson junction logical circuit element

Info

Publication number: JPS60191519A
Application number: JP4772884A
Authority: JP
Inventors: Hidekazu Goto; 英一後藤
Original assignee: RIKEN Institute of Physical and Chemical Research
Current assignee: RIKEN Institute of Physical and Chemical Research
Priority date: 1984-03-13
Filing date: 1984-03-13
Publication date: 1985-09-30

Abstract

PURPOSE:To obtain a logical function based on a flowing curent by applying weight addition to plural magnetic flux inputs representing logical variables and applying the result to a Josephson junction. CONSTITUTION:Superconduction magnetic flux transformers T1, T2 and T3 having 1:1 of winding ratio, the Josephson junction (j), a load superconduction inductance LL are connected in series so as to form a loop circuit. Then input magnetic fluxes (x), (y), (z) represent a binary logical value by using respectively magnetic flux value + or -phi0/4. The input magnetic fluxes are superimposed via the transformers T1-T3 and the synthesized magnetic flux phi (=x+y+z) is fed to the junction (j). An output magnetic flux phif proportional to the current I flowing to the junction (j) represents a parity check function of three inputs. When the winding ratio is different, the weight addition in response to the winding ratios is applied.

Description

【発明の詳細な説明】本発明は論理回路要素に係るものである。[Detailed description of the invention] The present invention relates to logic circuit elements.

本発明の目的は種々の論理関数を実現することのできる
、消費電力が少なく、スイッチング速度の速い論理回路
要素を提供することであり、この目的は論理変数を表わ
す複数の磁束人力を重畳して、少なくとも１個のジョセ
フソンジャンクションに印加し、このジョセフソンジャ
ンクションに流れる電流を出力負荷超伝導インダクタン
スに流してこのインダクタンスに生ずる磁束を論理出力
とするジョセフソンジャンクション論理回路要素により
達成される。The purpose of the present invention is to provide a logic circuit element with low power consumption and high switching speed that can realize various logic functions, and this purpose is to superimpose multiple magnetic fluxes representing logic variables. is applied to at least one Josephson junction, the current flowing through the Josephson junction is passed through an output load superconducting inductance, and the magnetic flux generated in this inductance is achieved by a Josephson junction logic circuit element.

ｇ３ｔ　明の便宜上先ずジョセフソンジャンクションｊ
と超伝導インダクタンスＬＬとの直列回路ループの特性
を第１．２図を参照して説明する。g3t For the convenience of Ming, first go to Josephson Junction J
The characteristics of a series circuit loop between the superconducting inductance LL and the superconducting inductance LL will be explained with reference to FIG. 1.2.

第１図はジョセフソンジャンクション」と超伝導インダ
クタンスＬＬ　との直列回路ループを示し、そしてこの
ループに磁束φを外部から加えた場合磁束φとループに
流れる電流Ｉとの関係を第２図に示す。第２図のグラフ
で横軸は基本量子磁束Φ。Figure 1 shows a series circuit loop of a Josephson junction and a superconducting inductance LL, and when a magnetic flux φ is externally applied to this loop, Figure 2 shows the relationship between the magnetic flux φ and the current I flowing through the loop. . In the graph of Figure 2, the horizontal axis is the fundamental quantum magnetic flux Φ.

（＝２Ｘ１０−’ガウスｃｆｆｌ　）で正規化した外部
磁束を、そして縦軸は電流Ｉをそれぞれ示している。The external magnetic flux normalized by (=2X10-'Gauss cffl) is shown, and the vertical axis shows the current I.

ジョセフソンジャンクションの超伝導臨界電流をＩ、ｌ
　とすると、微小信号に対するジョセフソンジャンクシ
ョンの等価インダクタンスＬＪ　は、Ｌ、にΦ。Ｉ２π
１．となる。ジョセフソンジャンクションに外部磁束φ
が印加されるとＬＪ　よりも充分に小さい超伝導負荷イ
ンダクタンスＩ−Ｌ　に電流Ｉが流れ、この電流■によ
って磁束φｒ（−Ｌｌ。The superconducting critical current of the Josephson junction is I, l
Then, the equivalent inductance LJ of the Josephson junction for a small signal is L, and Φ. I2π
1. becomes. External magnetic flux φ at Josephson junction
When is applied, a current I flows through the superconducting load inductance IL which is sufficiently smaller than LJ, and this current ■ causes a magnetic flux φr(-Ll.

・■）が生じる。外部磁束φと電流Ｉとの関係は次式に
より決定され、これをグラフに表わすと第２図のように
なる。・■) occurs. The relationship between the external magnetic flux φ and the current I is determined by the following equation, and this is graphed as shown in FIG. 2.

１−１．、５ｉｎ（２ｒｒφ／Φ０）　（１）第３図は
３人力の奇偶検査回路に適用した本発明によるジョセフ
ソンジャンクション論理回路要素の実施例を示す。第３
図に示すように、捲線比がｌ；ｌの３個の超伝導磁束変
圧器”ｌ’、、Ｔ２　、Ｔ３　と１個のジョセフジンジ
ャンクンヨン」と出力負荷超伝導インダクタンスＬＬ　
（ＬＬ　＜ＬＪ　）とが直列に接続されてループ回路を
形成している。1-1. , 5in (2rrφ/Φ0) (1) FIG. 3 shows an embodiment of the Josephson junction logic circuit element according to the present invention applied to a three-man-operated odd-even check circuit. Third
As shown in the figure, there are three superconducting flux transformers "l', , T2, T3 and one Joseph Jin Jiang Kun Yong" with winding ratio l; l and the output load superconducting inductance LL.
(LL<LJ) are connected in series to form a loop circuit.

３個の入力磁束ｘ、ｙ、ｚはそれぞれ磁束値±Φ。The three input magnetic fluxes x, y, and z each have a magnetic flux value ±Φ.

Ｉ４によって２値論理値を表わす。これらの人力磁束は
超伝導磁束変圧器Ｔ＋　、　Ｔ２、ｉ”３を介して重畳
され、そしてその合成磁束φ（＝　ｘ　十ｙ　＋Ｚ）は
ジョセフソンジャンクションＪに印加スる。A binary logical value is represented by I4. These human magnetic fluxes are superimposed via superconducting flux transformers T+, T2, i''3, and the combined magnetic flux φ (= x y + Z) is applied to the Josephson junction J.

このときジョセフソンジャンクション、１に流れる電流
Ｉ　（第２図）の真理値表は表１のようになり、この電
流Ｉに比例する出力磁束φ、は３人力の奇偶検査関数（
ｆ＝ｘ■ｙ■２）を表わすこと５なる。At this time, the truth table of the current I flowing through Josephson junction 1 (Fig. 2) is as shown in Table 1, and the output magnetic flux φ, which is proportional to this current I, is the three-way odd-even test function (
It becomes 5 to express f=x■y■2).

Ｘ　ｙ　ｚ　φ　１ −１　−１　−］　−３−１川 −川　−１＋１．　−１　−１ −１　＋１　−］、−Ｉ１　−１ −１１川　＋１　＋１４川ｌ川　−１’　−１−１−川＋１−］　＋］　＋１　−１Ｎ＋］　＋１　−１　＋１　−１１＋１　−１−１　＠−１＋３　−１表　１第４図は３人力の多数決回路に適用した本発明のジョセ
フソンジャンクション論理回路要素の実施例を示してい
る。X y z φ 1 -1 -1 -] -3-1 River - River -1+1. -1 -1 -1 +1 -], -I1 -1 -11 river +1 +14 river l river -1' -1-1-river +1-] +] +1 -1N +] +1 -1 +1 -11 +1 -1 -1 @-1+3 -1 Table 1 FIG. 4 shows an embodiment of the Josephson junction logic circuit element of the present invention applied to a three-person majority circuit.

第４図でｘ、ｙ、ｚは第３図の実施例と同様の人力磁束
であり、Ｔ、　、Ｔ２、Ｔ３は超伝導磁束変圧器であっ
て、Ｔ１　は］：］、Ｔ２　と′１゛３　は１：　’Ａ
（Ｄ捲ｍ比をもつ。ジョセフソンジャンクションは２個
使用し、それぞれに磁束φ−ｘ＋（ｙ十Ｚ）Ｉ２と、φ
２−（ｙ−１ｚ）Ｉ２とが印加し、それぞれのジョセフ
ソンジャンクションに流れる電流１１、Ｉ２　との合成
電流１　（＝　Ｉ＋　＋１２　）が負、荷インダクタン
スＬｌ、にながれる。この場合の真理値表を表２にしめ
ず。この表から明らかなように１　（φ、も同し）は３
人力ｘ、ｙ、ｚの多数−決関数を表わしている。In FIG. 4, x, y, and z are human magnetic fluxes similar to those in the embodiment shown in FIG.゛3 is 1: 'A
(Has a winding ratio of D. Two Josephson junctions are used, and each has a magnetic flux φ−x+(y+Z)I2 and φ
2-(y-1z)I2 is applied, and a composite current 1 (=I+ +12) of the currents 11 and I2 flowing through the respective Josephson junctions flows into the load, the load inductance Ll. The truth table for this case is shown in Table 2. As is clear from this table, 1 (also φ) is 3
It represents the majority voting function of human power x, y, z.

ｘ　ｙ　ｚ　φ、　φ２　１．　Ｉ２　Ｉ−１、−１−
１−２−１０−１−１ −１−１＋１　−１　０　−１　０　−１−ｉ　＋ｔ　
−ｔ　−ｔ　ｏ−ｉ（＋　−１−１＋１　＋１　０　＋
１　０　＋１　＋１１川　−１−１０−１０−１，−１＋１　−１　１川　＋１　０　＋１　Ｆ＋　＋１＋１　
＋１　−１　＋１　０　ＩＮ　（）＋１＋１　＋１　＋
１　＋２　＋１　０！−１＋］第３図の実施例ではンヨ
セフソンシートンクションに印加される磁束φはφ−ｘ
＋ｙ−ｌ／であるが、第４図の実施例ではジョセフソン
ジャンクションに印加される磁束φ１　とφ２　とはそ
れぞれφ１−Ｘ＋＋Ａｙ＋＋Ａｚ；φ２　＝’Ａｙ＋’
Ａｙ、である。第３図の実施例の場合には加算の重みは
１．１、■であるが、第４図の実施例の場合には加算の
重みは１、Ｖ２ｚＶ２である。本文ではこれらの場合を
さして磁束を重畳又は加重加算したと称する。x y z φ, φ2 1. I2 I-1, -1-
1-2-10-1-1 -1-1+1 -1 0 -1 0 -1-i +t
-t -t o-i(+ -1-1+1 +1 0 +
1 0 +1 +11 river -1-10-10-1, -1 +1 -1 1 river +1 0 +1 F+ +1+1
+1 -1 +1 0 IN ()+1+1 +1 +
1 +2 +1 0! −1+] In the embodiment shown in FIG.
+y-l/, but in the embodiment of FIG. 4, the magnetic fluxes φ1 and φ2 applied to the Josephson junction are respectively φ1-X++Ay++Az; φ2 = 'Ay+'
Ay. In the case of the embodiment shown in FIG. 3, the addition weight is 1.1, ■, but in the case of the embodiment shown in FIG. 4, the addition weight is 1, V2zV2. In this text, these cases are referred to as superimposed or weighted addition of magnetic fluxes.

更に複雑な論理関数は、複数の超伝導磁束変圧器と４個
の特性のほぼ等しいジョセフソンジャンクションとが４
次元のアダマル行列（要素が＋１又は−１である４行４
列の直交行列）又はその定数倍の磁束伝達特性を具現す
るような接続された回路を使用する本発明の実施例を用
いて実現することができる。この実施例の説明の便宜」
二先ず２次元のアダマル行列について説明する。A more complex logic function is that multiple superconducting flux transformers and four Josephson junctions with approximately equal characteristics are
dimensional Hadamard matrix (4 rows with 4 elements whose elements are +1 or -1)
Embodiments of the invention can be implemented using connected circuits that implement magnetic flux transfer characteristics of an orthogonal matrix of columns) or a constant multiple thereof. "For convenience of explanation of this example"
First, the two-dimensional Hadamard matrix will be explained.

第５図は２次元のアダマル行列（要素が→−又は−１で
ある２行２列の直交行列、−例として回路、通常ハイブ
リット変圧器とし−Ｃ知られているもの５構成を示す。FIG. 5 shows a two-dimensional Hadamard matrix (an orthogonal matrix with two rows and two columns whose elements are →- or -1), for example a circuit, usually known as a hybrid transformer.

この回路で人力磁束信号をφ１．φ２とし、出力磁束信
号をφ３．φ、とし、それぞれが表ず２値論理変数をｘ
、ｙ、ｕ、＼ｌとすると次の関係が成立する。This circuit converts the human magnetic flux signal to φ1. φ2, and the output magnetic flux signal is φ3. φ, and each represents a binary logical variable x
, y, u, \l, the following relationship holds true.

次に４次のアダマル行列（要素が−１１または一４行で
ある４行４列の直交行列、−例としてこの４次のアダマ
ル行列の磁束伝達特性をイｊする回路の入力磁束信号を
φ１．φ２．φ１，７　φ、。Next, a 4th-order Hadamal matrix (a 4-by-4 orthogonal matrix with elements in -11 or 14 rows) is used. .φ2.φ1,7 φ,.

とし、そして出力磁束信号をφ９．φ５１．φ７゜φ６
　とすると人出〕Ｊ侶号は次式により決定される。and the output magnetic flux signal is φ9. φ51. φ7゜φ6
Then, the number of people] J's name is determined by the following formula.

これを実現する回路の４個の出力鮨（子（出力（ｉ４９
東φ５．φ５．φ７．φ。か現れる☆ｉｌｊ子）にそれ
ぞれジョセフソンシャクジョンＪ＋　１．ｌ’２１．１
ｓ　、Ｊ、を結合することによ引１４　Ｉ４論理回路要
素を構成することができる（１１４は４次のアダツル１
１列を、Ｉ４は４個のジョセフソンシャクジョンをそれ
ぞれ表す）。The four outputs of the circuit that realize this (output (i49
East φ5. φ5. φ7. φ. Josephson Shakujon J+ 1. l'21.1
By combining s and J, a 14 I4 logic circuit element can be constructed (114 is a 4th order adatsu
1 column, I4 each representing 4 Josephson blocks).

第６ａ図と第６ｂ図に本発明による１Ｉ４Ｊｌｌ　論理
回路要素の２つの例を示す。３個の磁束ベクトルφ１．
φ２．φ３が加えられる端子を入力端とし、出力磁束ベ
クトルが取出される端子に出力負荷超伝導インダクタン
スＬＬを接続して出力端とする。Figures 6a and 6b show two examples of 1I4Jll logic circuit elements according to the present invention. Three magnetic flux vectors φ1.
φ2. The terminal to which φ3 is applied is the input end, and the output load superconducting inductance LL is connected to the terminal from which the output magnetic flux vector is taken out, and the output end is the terminal.

いま、人力磁束ベクトルが表す２値論理変数をｘｌ、Ｘ
、及びＩ３　とする。出力磁束ベクトルφ４が表す２値
論理変数をＸ、とすると人出ツノの２値論理変数は次式
の関係を満足する３、Ｘ１＝−Ｘ、・Ｉ２　・Ｉ３　（４）真、イＡを表現するのに磁束の極性Ｃ＋、−）によって
も、磁束の有ｊｉｊＥ　（Ｑ　、−１−もしくは−の磁
束）によってもよい。前者によれば式（４）はＸ→　＝
Ｘ、■ｘ２■ｘ３　となり、３ヒツトの排泄的論理和回
路であり、後者によればＸ、＝ｘ、＆Ｘ２　＆Ｘ３　と
なり、３ビツトの論理積回路となる。Now, the binary logical variables represented by the human magnetic flux vector are xl,
, and I3. If the binary logical variable represented by the output magnetic flux vector φ4 is X, the binary logical variable of the turnout satisfies the following relationship.3, X1=-X, ・I2 ・I3 (4) True, i It may be expressed by the polarity of the magnetic flux (C+, -) or by the presence of the magnetic flux (Q, -1- or -magnetic flux). According to the former, equation (4) is X→ =
According to the latter, X, x2, x3, which is a 3-bit exclusive OR circuit, and the latter, X, = x, &X2 &X3, which is a 3-bit AND circuit.

第７図に１個の本発明の実施例の１１４．１４　論理回
路要素Ｈ４Ｊ４　と１個の２次元アダマル回路要素１１
２とから成る２ビット選択回路（ｘ、ｙのいずれがを信
号ＳＯ，Ｓｌに従って選択して出力する回路）の構成を
示し、表３にその回路の真理値表を示ず。FIG. 7 shows one 114.14 logic circuit element H4J4 of the embodiment of the present invention and one two-dimensional Hadamal circuit element 11.
Table 3 shows the configuration of a 2-bit selection circuit (a circuit that selects and outputs either x or y according to signals SO and SI) consisting of 2 and 2, and Table 3 does not show the truth table of the circuit.

Ｓｏ　Ｓｌ　ｘ　ｙ　ｕ　ｖ　ｗ　ｆ −１−１−１−１０川　０　川　（Ｘ）月　刊　−１＋
１　−１　０　−ｉ　−１（ｘ）＝１　刊　＋１　−．
１　ｔｌ　Ｏ４１刊　（ｘ）−１刊　＋１　＋１　０　
＋１　０　−１　（ｘ）−１月　−１−１０−１０−１
（ｙ） −１→］　−１ｔｌ川　０Ｆ１１１（ｙ）−１ｔｌ　４
４　’−１ｔｌ　Ｏ−１川　くｙ）−１＋］　＋］　ト
１　０　＋１　［ＩＩｉ　（ｙ）弓　−１−１−１０川
　０　刊　（ｙ）＋１．　−１　−Ｉ　Ｌｌ　−１０→
ｌ　ト１　（ｙ）→１　−１　→ｌ　刊　ｔｌ　ｆｌ　
−４４（ｙ）＋１　−１　普１　＋１　０　→１　０　
４１　（ｙ）４１　ｔｌ　−１−１０刊　［１−１（Ｘ
）司　４４　−１　＋１　−１　０　刊−１（×）→］
　＋］　、１．１　−１　ｔｌ　Ｏ→ｌ　４１　（Ｘ）
→ｌ　＋］　＋］　司　０　＋１　［１月　（×）表　
２第８図に１個の＋＋、＋、ｉ４論理回路要素１１４．１
４　と１個の２次元アダマル回路要素１−１２　とから
成る３人力多数決回路（ｘ、ｙ、ｚの過半数が真であれ
ば真を、偽であれば偽を出力する回路）の構成を示し、
表４にその回路の真理値表を示す。So Sl x y u v w f -1-1-1-10 River 0 River (X) Monthly -1+
1 -1 0 -i -1(x)=1 publication +1 -.
1 tl O41 publication (x)-1 publication +1 +1 0
+1 0 -1 (x)-January -1-10-10-1
(y) -1→] -1tl river 0F111 (y) -1tl 4
4'-1tl O-1 river kuy)-1+] +] ト1 0 +1 [IIi (y) Bow -1-1-10 river 0 publication (y)+1. -1 -I Ll -10→
l To1 (y)→1 -1 →l Published tl fl
-44(y)+1 -1 Ordinary 1 +1 0 →1 0
41 (y) 41 tl -1-10 edition [1-1(X
) Tsukasa 44 -1 +1 -1 0 publication -1(×)→]
+] , 1.1 -1 tl O→l 41 (X)
→l +] +] Tsukasa 0 +1 [January (×) table
2 One ++, +, i4 logic circuit element 114.1 in Figure 8
4 and one two-dimensional Hadamal circuit element 1-12 (a circuit that outputs true if the majority of x, y, z is true, and outputs false if it is false) is shown. ,
Table 4 shows the truth table of the circuit.

ｘ　ｙ　ＺＩＪ　ＶＷ　ｆ −１’−１−１０−１０−１ −１−１＋１−１０−１月 −１ｔｌ　−１４４０川　川 −１ｔｌ　ｔｌ　Ｑ　ｔｌ　ｔｌ　、４．１←１−１−
１０−１０刊＋１　−１　＋１　４　［１−１＋１ →１　→１　−１　ｔｌ　Ｏ→１−１＋］　−１１＋］　Ｏ→１０川表　４第９図に１個の１１４．１４論理回路要素１１／ｌ　、
Ｉｌｌ　と２１１．１．１の２次元アダマル回路要素１
−１２　とから成る３人カ一致回路（ｘ、ｙ、ｚがいず
れも真又は偽であるときにのみ真を出力し、それ以外の
場合は偽を出力する）の構成を示し、表５にその回路の
真理値表を示す。x y ZIJ VW f -1'-1-10-10-1 -1-1+1-10-January-1tl -1440kawa river-1tl tl Q tl tl , 4.1←1-1-
10-10 publication +1 -1 +1 4 [1-1+1 →1 →1 -1 tl O→1-1 +] -11+] O→10 river table 4 One 114.14 logic circuit element 11 in Figure 9 /l,
Ill and 2D Hadamard circuit element 1 of 211.1.1
-12 The configuration of a three-person matching circuit (outputs true only when x, y, and z are all true or false, and outputs false otherwise) is shown in Table 5. Show the truth table of the circuit.

σ：　↓゛ｌ −１−１−１−１刊　±１」１月　−１→ｌ　−１００Ｊ１暑　ト１　−１　３−１　Ｆｌ　七１ −暑　＋１　司　０　０　［１−１＋４１　川　署　１　’ＯＯ）−１＋ｌ　−１ｔｌ　ｆｌ　ｔｌ　ｔｌ　−！：１＋１　何
−１１，０［］　川用　＋１　川　」ｌ　＋１　±１　ａ“１表　５第５図において、例えばＸ、ｙ、ｚかいずれも−１であ
ると１１４．１４　の２つの入力し、ｖは−１゜−１と
なり、残りの１つの入力に出力の極性を定める信号σ（
−±１　）が加わると１１４ＪＩＩ　の出力は式（３）
に従って±１となり、この出力を（２Ｗ＊＊−σ）の線
形演算回路を介して最終的に出力することとなる。σ: ↓゛l -1-1-1-1 publication ±1'' January -1→l -100J1 Hot 1 -1 3-1 Fl 71 -Hot +1 Tsukasa 0 0 [1-1+ 41 Kawa Station 1 'OO)-1 +l -1tl fl tl tl -! :1+1 What -11,0 [] For river +1 River "l +1 ±1 a"1 Table 5 In Figure 5, for example, if X, y, and z are all -1, the two inputs 114.14 , v becomes -1°-1, and the remaining one input is the signal σ(
-±1), the output of 114JII is expressed by formula (3)
Accordingly, it becomes ±1, and this output is finally outputted via a (2W**-σ) linear arithmetic circuit.

第１０図に２個の１１４．１４　論理回路要素１１４．
１４　を使用した３中１ビット回路（：３人力のうらと
れか１つ真であればそのときに出力は真とｌＳす、それ
以外の場合は出力は偽となる）の構成を示し、表５にそ
の回路の真理値表を示す。In FIG. 10, there are two 114.14 logic circuit elements 114.
14 shows the configuration of a 1 out of 3 bit circuit (: if one of the three is true, then the output is true; otherwise, the output is false), and the table below shows the configuration of a 1 out of 3 bit circuit using Figure 5 shows the truth table of the circuit.

ｘ　ｙ　Ｚ　Ｘ＊　ｙ＊　Ｚ＊　ａ＊　ｌ’　ｆ（＝ｌ
’−２ａ）−１−１−１００００川−１ −１刊　＋１　０　（１１０＝ｉ　→１−１　ｔｌ　−
］　０１００・１司 −１司　＋１　０　１　１　ｔｌ　川　−１４４−１−
１１００（１・１−１＋１　−１　ｔｌ　Ｉ　ＯＩ　Ｏ、−１川→１　ｔｌ　
−１１１ｆｌｌ　ｔｌ刊−］司　＋１　→ｌ　ｌ　］　
ｔｌ　ｌ　＋１　同表　５第１０図において３つの入力信号ｘ、ｙ、ｚ　（例えば
−１，、−１，＋１）　は一方のＨ４Ｊ４へそのまま加
えられ、他方のＨ４Ｊ４へはレベル変換しｘ；Ｉ：、ｙ
＊。x y Z X* y* Z* a* l' f(=l
'-2a) -1-1-10000 river-1 -1 edition +1 0 (110=i →1-1 tl -
] 0100・1 Tsukasa-1 Tsukasa +1 0 1 1 tl River -144-1-
1100 (1・1-1 +1 -1 tl I OI O, -1 river → 1 tl
-111fll tl publication-] Tsukasa +1 → l l ]
tl l +1 Same Table 5 In Fig. 10, three input signals x, y, z (for example, -1,, -1, +1) are applied as they are to one H4J4, and are level-converted to the other H4J4. :,y
*.

Ｚ＊（例えば０，０．１）として加えられ、前記の一方
の１Ｉ４Ｊ４　の出力Ｐ（例えば］−１）と、前記の他
方の１１４Ｊ４　の出力ａ＊（例えばＯ）とは（丁〕−
２ａ＊）の演算を行う回路を通して最終的に［（例えば
、＋１）として出力される。Z* (e.g. 0, 0.1), and the output P (e.g.]-1) of the one 1I4J4 and the output a* (e.g. O) of the other 114J4 are (d)-
2a*) and is finally output as [(for example, +1).

[Brief explanation of drawings]

第１図はショセフソンンヤンクションと超伝導インダク
タンスとの直列回路ループを示し、第２図はその回路の
特性を示す。第３図は３人力の奇偶検査回路に適用した本発明の実施
例を示す。第４図は３人力の多数決回路に適用した不発Ｉυ１の実
施例を示す。第５図は２次元アダマル回路の構成を示す。第６図ａ図と第６　ｂ図とはそれぞれ本発明の実施例で
ある＋＋４　Ｊ４論理回路要素を示す。第７図は＋１４　Ｊ４　論理回路要素を使用した２人力
選択回路を示す。第８図は１１４ｊ４　論理回路要素を使用した３人力多
数決回路を示す。第９図は１１４　Ｊ４論理回路要素を使用した３人カ一
致回路を示す。第１０図は１１４Ｊ４論理回路要素を使用した３中１ビ
ット回路を示す。図中：ｌ１４　Ｊ４　：＋＋４Ｊ４論理回路要素１−１
２：２次元アダマル回路第１図第５図第６８図第６ｂ図Ｉ第７図FIG. 1 shows a series circuit loop of a Shosefson junction and a superconducting inductance, and FIG. 2 shows the characteristics of the circuit. FIG. 3 shows an embodiment of the present invention applied to an odd-even test circuit operated by three people. FIG. 4 shows an embodiment of the unexploded Iυ1 applied to a three-person majority circuit. FIG. 5 shows the configuration of a two-dimensional Hadamard circuit. FIGS. 6a and 6b each illustrate a ++4 J4 logic circuit element according to an embodiment of the present invention. FIG. 7 shows a two-person selection circuit using +14 J4 logic circuit elements. FIG. 8 shows a three-person majority voting circuit using 114j4 logic circuit elements. FIG. 9 shows a three-person matching circuit using 114 J4 logic circuit elements. FIG. 10 shows a 1-of-3 bit circuit using 114J4 logic circuit elements. In the figure: l14 J4: ++4J4 logic circuit element 1-1
2: Two-dimensional Hadamal circuit Figure 1 Figure 5 Figure 68 Figure 6b Figure I Figure 7

Claims

[Claims]

(1) Add the weighted magnetic fluxes representing the logical variables with the fixed Joseph Sonshi\Nkushi317, and add this weighted magnetic flux to the above-mentioned J ball j Sefson Shankho.
an output load superconducting inductance connected to the Josephson junction, and an output means for extracting the magnetic flux generated by the current flowing from the Josephson junction to the superconducting inductance as a logical output. A Josephson junction logic circuit element characterized in that it can generate ff1fi.

(2) A Josephson junction logic circuit element according to claim (1), wherein said weighted addition means comprises a superconducting flux transformer.

(3) The above-mentioned Josephson junction is composed of four Josephson junctions having the same characteristics, and the weighted addition means includes a superconducting flux transformer to which three magnetic fluxes are applied, and a four-dimensional Hadamard matrix or Claim No.
Josephson junction logic circuit element described in item 1).