JPS60191294A - Address updating unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address updating device, and its processing speed is improved.

[Technical background of the invention and its problems]

2. Description of the Related Art In recent years, systems (for example, video game systems) that can display images on a monitor such as a television receiver by key operations have become widespread.

Among these types of systems, there are systems in which image data transfer function is important in systems that can perform image compositing.

As an example, a device equipped with a New Year's card creation function as shown in Figure 1 has been proposed. This system can display a sample display section 12 and a workpiece display section 13 on a display screen 1. In this example, the sample display section 12 has an octopus, a piece, and a tree. A state in which the image of the 'top' has been transferred to the lower left of the workpiece display section 13 is shown.

This state is usually obtained by operating the sample image designation key and the transfer destination designation key on the keyboard. When a sample image designation key and a transfer destination designation key, which are determined in advance according to specifications, are operated, the microprocessor within this image processing device starts image data transfer processing.

According to the conventional technology, this image data transfer process is entirely performed by software.

FIG. 2 shows an image memory 15 corresponding to the display screen 11. The addresses of the image memory 15 are set so that their numbers increase in accordance with the line sequential scanning of the television screen. That is, to explain it on the drawing, the hair address number increases from the upper left to the right, and when it advances by one horizontal line, it moves to the next horizontal line, and so on.

Now transfer the data of sample image area x5A to area 1
Let us consider the case of transferring to 5B.

In this case, the data is obtained by reading the data in the image area 151L and updating the write address to the transfer destination area. FIG. 3 shows an enlarged view of the image area J5A. Assuming that the upper left address of the image area 15A is KXN+j, this becomes the initial value and the address data is counted up. And the address is KxNj+(n-
1) When you reach the right edge of the area,
It is necessary to add N-n+1 to this address KxN+j+(n-1) and move to address (K+1)XN+j. It is necessary to repeat such processing to update the address designation data up to the final address of the image area 15A. Similar address update processing is required when writing read data. When the vertical address start positions are aligned like this, it is relatively easy to calculate the address, but when the vertical address changes as shown in area 15C, it becomes necessary to perform complicated address calculation. .

Conventionally, all such address calculations have been processed by a program, which has caused a problem in that the processing time is extremely slow.

[Purpose of the invention]

This invention was made to deal with the above circumstances, and includes:
m; To provide an address update device that updates addresses at high speed by simple means.

[Summary of the invention]

According to this invention, update address data is generated at high speed by realizing the part 22123124 for calculating update of address data and the parts 30, 28, 29, 27, etc. for outputting addition data for updating by hardware. It has been made possible.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 shows an embodiment of the present invention, in which reference numeral 21 is an address update reference pulse generator that generates a pulse S1 for timing address updates. The pulse S1 generated here is the memory access reference pulse (read/
write) is used, an adder 24, a horizontal counter 2
5 as a clock.

On the other hand, 22 is an initial value setting circuit, which is a circuit for setting initial data of the address of the sample image area (see FIG. 3). The output of this circuit 22 is input to an address memory 23. The output data of this address memory 23 is used as addressing data for the image memory and is also added to an adder 24. This adder 24 adds the data from the address memory 23 and the data from the switch circuit 3θ. Then, the result is inputted into the address memory 23 again, thereby updating the addressing data.

Next, the means for providing addition data to the adder 24 and its driving means will be explained. A count value n is preset in the horizontal direction counter 25, and when this horizontal direction counter 25 counts n pulses S1,
A pulse S2 as a carry is output, which is input to the switching pulse generator 27 and the vertical counter 26. Here, the vertical direction counter 26 is preset with a count value m. A pulse S3 obtained when the vertical counter 26 counts m pulses S2 is used to stop access (read/write) to the image memory. The switching pulse generator 29 generates a pulse S4 every time the pulse S2 is input, and thereby controls the switch circuit 30. The switch circuit 30 inputs the data of the addend memory 29 to the adder 24 once every time the pulse S4 is applied. Other than this time, the switch circuit 30 selects the data in the addend memory 28 and supplies it to the adder 24. Therefore, in the adder 24, the addition process of the data in the addend memory 28 and the data in the address memory 23 is performed n times in synchronization with the pulse S, and n
+1st time, data in addend memory 28 and address memory 2
Addition processing with data No. 3 is performed.

Here, the data in the addend memory 28 is 1 (horizontal address update), and the data in the addend memory 29 is (N-n
+1) (vertical address update). In other words, as in the example of FIG. 3, if the image area 15k has n addresses in the horizontal direction and m lines (addresses) in the vertical direction, the operation timing waveforms are shown in FIGS. 5(a) and 5(b). It becomes like this. Further, the set data of the initial value set circuit 22 in this case is KXN+j.

The above explanation is for updating the data read address of the sample image area as shown in Figure 3, but it can be done in the same way when updating the address of the transfer destination area. Just change the data.

Next, if the vertical lines are not aligned as in the image area 15C in FIG. The contents of the addend memory may also be switched. As described above, according to the present invention, address updating work can be performed almost entirely by hardware, and updated address data can be generated at high speed.

Further, according to the present invention, various functions can be provided by setting various data stored in the addend memories 28 and 29. For example, if the data stored in the addend memory 28 is set to 2 when reading data, and the data stored in the addend memory 28 is set to 1 when writing data, the size of the image in the transfer destination area is set to 172. 0 is also possible, and vice versa, and it is also possible to enlarge and transfer 0
In this way, various images can be transferred with the simple operation of changing the value of the addend memory, so it can be used in many fields such as graphic animation and image compositing.Furthermore, it is possible to transfer images after enlarging or reducing them. As a means to do this, when the output pulse of the address update reference pulse generator 21 is input to the adder 24 or the horizontal force counter 25,
Alternatively, the frequency division ratio may be changed by inputting the signal through a frequency dividing means.

FIG. 6 shows a frequency divider on the output side of the address update reference pulse generator 21. This is an example in which JA is connected. As a result, if the frequency division ratio is switched by the microprocessor between reading and writing, it is possible to freely enlarge or reduce the transferred image.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an address update device that updates addresses at high speed using simple means.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram showing an example of a display screen, Fig. 2 is an explanatory diagram to explain the address of the image memory, Fig. 3 is an explanatory diagram showing a part of Fig. 2, and Fig. 4 is an explanatory diagram showing an example of the display screen. , a configuration explanatory diagram showing one embodiment of this invention, FIG. 5 is a signal waveform diagram of each part of the circuit of FIG. 4, and FIG. 6 is a circuit diagram shown to explain another embodiment of this invention. . 2 No. Address update reference pulse generator, 22...
Initial value set circuit, 23...address memory, 24.
...Adder, 25...Horizontal counter, 26...
Vertical counter, 27°° switching pulse generator, 28.29... Addend memory, 30... Switch circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Drop L

Claims (1)

[Claims] an initial value set circuit into which arbitrary initial address data of the image memory is set; an address memory into which updated address data based on the address data of the initial value set circuit can be input/output; and an output address of the address memory. an adder that adds the data and the addition data of the switch circuit and inputs it to the address memory; an address update reference pulse generator that provides an addition timing pulse to the adder; a horizontal direction counter that counts the number of direction addresses and outputs a line change pulse when the counting is completed; A vertical counter that counts and generates an address update end pulse, a plurality of addend memories each storing additional data to be applied to the adder via the switch circuit, and output pulses of the horizontal counter are input. and a switching pulse generator that generates a switching pulse in response to the pulse so that the switch circuit selects and derives data for line change from one of the addend memories. Characteristic address update device.