JPS6018977A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS6018977A JPS6018977A JP58126047A JP12604783A JPS6018977A JP S6018977 A JPS6018977 A JP S6018977A JP 58126047 A JP58126047 A JP 58126047A JP 12604783 A JP12604783 A JP 12604783A JP S6018977 A JPS6018977 A JP S6018977A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion
- active layer
- layers
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 26
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 239000007791 liquid phase Substances 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 86
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体素子の製造方法、特に発光ダイオード(
発光素子)の製造方法に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, particularly a light emitting diode (
The present invention relates to a method of manufacturing a light emitting device.
通信用近赤外発光ダイオード素子として本出願人は第1
図に示すような構造の発光素子を開発しティる。この発
光素子1はドーム状のG a A−g A s体2の平
坦面上にp −G a AJI A sからなる15〜
20μmの厚さの23層3を有している。このP1層3
はその中央に厚さ0.5μmのp −G a Affl
A sからなる27層(活性層)4+ 1.5μmの厚
さのn −GaA、、eAsからなる8層5.0.7μ
mの厚さのn”−GaAsからなるN+層6を順次積層
した構造となっている。また、前記P6層3の上面には
前記活性層4等を非接触で取り囲むように配設されたP
+層7が形成されている。そして、このP+層7上には
7ノード電極8が設けられ、N+層6上にはカソード電
極9が設けられている。また、電流狭窄欠口る目的で前
記N+層6および8層5の途中深さまでKZnが拡散さ
れてP+の電流狭窄層1oが設けられている。このよう
な発光素子1はアノード電極8およびカソード電極9間
に所定の電圧を印加すると・ドームの略中心となる位置
のPN接合部分で近赤外光11を発光する。The applicant has developed the first near-infrared light emitting diode device for communications.
Develop a light emitting device with the structure shown in the figure. This light emitting element 1 consists of 15~
It has 23 layers 3 with a thickness of 20 μm. This P1 layer 3
has a 0.5 μm thick p-G a Affl in its center.
27 layers (active layer) consisting of As 4+ 8 layers consisting of n-GaA, eAs with a thickness of 1.5 μm, 5.0.7 μm
It has a structure in which N+ layers 6 made of n"-GaAs with a thickness of P
+ layer 7 is formed. A seven-node electrode 8 is provided on the P+ layer 7, and a cathode electrode 9 is provided on the N+ layer 6. Further, for the purpose of current confinement, KZn is diffused halfway into the N+ layers 6 and 8 layers 5 to provide a P+ current confinement layer 1o. When a predetermined voltage is applied between the anode electrode 8 and the cathode electrode 9, such a light emitting element 1 emits near-infrared light 11 at the PN junction at the approximate center of the dome.
しかし、このような発光素子1は前記P+層7の形成の
ために行な5Znの拡散処理(700℃で100分処理
)時の熱で、活性層4内に拡散されているZnがN層5
中に拡散(バツクデ、fフーージョン)し、その後形成
されるP+の電流狭窄層10と導通してしまいショート
不良が発生するという問題点が生ずるということが本発
明者によってAbきらかとされた。However, in such a light-emitting element 1, the Zn diffused into the active layer 4 is absorbed by the heat during the 5Zn diffusion treatment (treatment at 700° C. for 100 minutes) performed to form the P+ layer 7. 5
The inventor of the present invention has found that Ab diffuses into the P+ current confinement layer 10 that is subsequently formed, causing a short-circuit failure.
そこで本発明者はこのパックディフュージョンについて
検討した結果、前記N層5はn導電型決定不純物である
Teの濃度がlXl0 a!I で、活性層4のp導電
型決定不純物であるZnの濃度が5 X: 10171
m−3であり、濃度差が太きすぎることによりバックデ
ィフュージョンが発生し易いこと馨知った。そこで、濃
度差を/」1さくすることによってバックディフュージ
ョンを防止できることに気が付き本発明を成した。Therefore, the present inventor studied this pack diffusion and found that the concentration of Te, which is an n conductivity type determining impurity, in the N layer 5 is lXl0 a! I, the concentration of Zn, which is an impurity determining the p conductivity type of the active layer 4, is 5X: 10171
m-3, and Kaoru learned that back diffusion is likely to occur due to the density difference being too large. Then, they realized that back diffusion could be prevented by reducing the density difference by 1, and developed the present invention.
〔発明の目的〕
本発明の目的は牛導体素子の製造において、熱処理時の
バックディフュージョンを防止することにより、ショー
ト不良の発生を防止することにある。[Object of the Invention] An object of the present invention is to prevent the occurrence of short-circuit defects by preventing back diffusion during heat treatment in the production of conductor elements.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかにな−るで
あろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明はドーム体となるGaAlAs層の主
面に順次p−GaA−#Asからなる27層、p−Q
a A−# A Sからなる22層(活性層)、 n
GaA−#AsからなるN層、n−GaAsからなるN
層層を液相エピタキシャル法によって形成した後、N層
層から21層に達するようKZnを拡散させてP+導電
型となる21層をドーナツ状に形成するとともK、この
ドーナツ状P+層の内周にN層の途中に布達するように
Znを拡散し【ドーナツ状の電流狭窄層を形成し、かつ
電流狭窄層とP+層との界面部分に沼って20層に達す
るようなメサエッチングを行ない、さらに、N+層上に
カソード電極、P+層にアノード電極を形成するととも
に、チップ化。That is, in the present invention, 27 layers made of p-GaA-#As, p-Q
22 layers (active layer) consisting of a A-# A S, n
N layer made of GaA-#As, N layer made of n-GaAs
After forming the layers by liquid phase epitaxial method, KZn is diffused from the N layer to the 21st layer to form the 21st layer of P+ conductivity type in a donut shape. Then, Zn is diffused so as to reach the middle of the N layer [to form a donut-shaped current confinement layer, and mesa etching is performed to reach 20 layers at the interface between the current confinement layer and the P+ layer. , Furthermore, a cathode electrode is formed on the N+ layer, an anode electrode is formed on the P+ layer, and it is made into a chip.
ドーム化してドーム構造の発光素子を製造する方法にお
いて、P+層および電流狭窄層形成時の熱による活性層
からN層へのZnの拡散率を低くし、活性層と電流狭窄
層とのショートを防止するためK、あらかじめN層の不
純物濃度を活性層の不純物濃度に近似させておくことに
よって、活性層と電流狭窄層との導通(ショート)を防
止し、発光素子製造歩留の向上1発光素子の信頼度向上
を達成するものである。In the method of manufacturing a light emitting element with a dome structure, the diffusion rate of Zn from the active layer to the N layer due to heat during formation of the P+ layer and the current confinement layer is reduced, thereby preventing short circuits between the active layer and the current confinement layer. In order to prevent this, conduction (short circuit) between the active layer and the current confinement layer can be prevented by making the impurity concentration of the N layer similar to the impurity concentration of the active layer in advance, thereby improving the manufacturing yield of light emitting devices. This improves the reliability of the device.
第2図ta)〜(b)は本発明の一実施例による近赤外
光を発光するドーム状発光素子(発光ダイオード)の製
造方法を示す断面図である。FIGS. 2(a) to 2(b) are cross-sectional views showing a method of manufacturing a dome-shaped light emitting element (light emitting diode) that emits near-infrared light according to an embodiment of the present invention.
この実施例では、同図(a)に示すように、100μ程
度の厚さのGaAs板12の主面(上面)に300μm
程度の厚さのアンドープのGaA−gAs体2を有する
ウェハ13を用意する。In this embodiment, as shown in FIG. 2(a), a 300 μm thick
A wafer 13 having an undoped GaA-gAs body 2 having a certain thickness is prepared.
つぎに、液相エピタキシャル法によって15〜20pm
の厚さのp −G a AJI A sからなるP8層
3゜0.5μmの厚さのp −GaA−13Asからな
るPt層(活性層)4. 1.5μmの厚さのn−Ga
A、、eAsからなる8層5、 0.7μmの厚さのn
”−GaA沼AsからなるN+層6を順次形成する。こ
の際、n導′WLm決定不純物としてはf’e、 p導
電型決定不純物はZnを使用する。また、後述する活性
層4からのZnのパックディフュージョン率の低減化を
図るために、活性層4のZn濃度をたとえば5に101
7m−3に対して、8層5のTe濃度をたとえば3〜5
X10 011 と近似させて、濃度差を小さくしてお
く。Next, by liquid phase epitaxial method, 15 to 20 pm
P8 layer made of p-GaAJIAs with a thickness of 3°; Pt layer (active layer) made of p-GaA-13As with a thickness of 0.5 μm; 4. 1.5μm thick n-Ga
A, 8 layers of eAs 5, 0.7 μm thick n
An N+ layer 6 made of "-GaA swamp As is sequentially formed. At this time, f'e is used as the n-conductivity WLm determining impurity, and Zn is used as the p-conductivity type determining impurity. In order to reduce the pack diffusion rate of Zn, the Zn concentration of the active layer 4 is increased from 5 to 101, for example.
7m-3, the Te concentration of the 8th layer 5 is, for example, 3 to 5.
The density difference is made small by approximating it to X10 011 .
つぎに、ウェハ13の主面からZn’L拡散させ、21
層3にまで達するドーナツ状のP+層7を常用のホトエ
ツチング技術および拡散技術によって形成する。なお、
このZnの拡散は700℃で100分処理されることに
よって行なわれる。Next, Zn'L is diffused from the main surface of the wafer 13, and
A doughnut-shaped P+ layer 7 extending up to layer 3 is formed by conventional photoetching and diffusion techniques. In addition,
This Zn diffusion is performed by processing at 700° C. for 100 minutes.
つぎに、常用のホトエツチング技術および拡散技術を用
いて、前記P+層7の内周に8層5の途中の深さにまで
達するドーナツ状のp導電型の電流狭窄層10乞形成す
る。この拡散処理では1.5μの薄い8層5の中間深さ
に正確にZnを拡散させるために、前記P+層7を形成
する際の拡散温度700℃に比較して675℃と温度を
低くし、かつ拡散深さも浅いところから処理時間も20
分と短かくする。Next, a donut-shaped p-type current confinement layer 10 is formed on the inner periphery of the P+ layer 7 to a depth halfway through the eight layers 5 using conventional photoetching and diffusion techniques. In this diffusion process, in order to accurately diffuse Zn into the middle depth of the 1.5μ thin 8-layer 5, the temperature was lowered to 675°C compared to the diffusion temperature of 700°C when forming the P+ layer 7. , and the processing time is 20 minutes since the diffusion depth is shallow.
Make it as short as minutes.
この拡散処理において、活性層4内のZnがN層°5中
にパックディフュージョンするが 活性層4と8層5に
おけるそれぞれの不純物濃度は5に1017an−3お
よび3〜5X1017□□□−3と近似し、濃度差が第
1図で示す構造のものと比較して/」・さい。In this diffusion process, Zn in the active layer 4 undergoes pack diffusion into the N layer 5, but the respective impurity concentrations in the active layer 4 and 8 layer 5 are 5 to 1017an-3 and 3 to 5X1017□□□-3. Approximately, the concentration difference is compared with that of the structure shown in Figure 1.
この結果、パックディフュージョン層(図示せず)は8
層5を通過して電流狭窄層10に達することはなく、シ
ョート不良は発生しない。As a result, the pack diffusion layer (not shown) is 8
The current does not pass through the layer 5 and reach the current confinement layer 10, and no short-circuit failure occurs.
つぎに、前記P+層7と電流狭窄層10との界面部分に
沿ってドーナツ状にメサエッチングを行なう。メサエッ
チングは活性層4をも越えて21層30表層部に達する
ように行なう。また、P+層7の表面にはアノード電極
8を、N+層6の表面にはカソード電極9を形成する。Next, donut-shaped mesa etching is performed along the interface between the P+ layer 7 and the current confinement layer 10. Mesa etching is performed so as to extend beyond the active layer 4 and reach the surface layer 21 of the layer 30. Further, an anode electrode 8 is formed on the surface of the P+ layer 7, and a cathode electrode 9 is formed on the surface of the N+ layer 6.
さらに、ウエノ・13を格子状に分断してチップ化する
とともに、G a A−g A s体部分をドーム状に
加工し、同図(d)で示すようなドーム構造の発光素子
1を製造する。Furthermore, the Ueno 13 is divided into lattice shapes and made into chips, and the GaAgAs body portion is processed into a dome shape to produce a light emitting element 1 with a dome structure as shown in the same figure (d). do.
このような発光素子1はアノード電極8とカソード電極
9間に所定の電圧を印加することにより、ドームの略中
心位置にあるPN接合部分から近赤外光11を発光する
。By applying a predetermined voltage between the anode electrode 8 and the cathode electrode 9, such a light-emitting element 1 emits near-infrared light 11 from the PN junction located approximately at the center of the dome.
(1)本発明の発光素子は活性層とこれに隣接する薄い
N層との不純物濃度差が小さいことから、発光素子製造
時に加わる熱処理によっても活性層中の不純物のN層に
対するバンクディフュージョン量(率)は小さい。この
ため、パックディフュージョン層がN層を通過して活性
層と同じ導電型である電流狭窄層に到達することが防止
でき、ショート不良発生防止が可能となり、信頼度の高
い発光素子を提供することができる。(1) Since the light emitting device of the present invention has a small impurity concentration difference between the active layer and the thin N layer adjacent thereto, the amount of bank diffusion of impurities in the active layer to the N layer ( rate) is small. Therefore, it is possible to prevent the pack diffusion layer from passing through the N layer and reaching the current confinement layer, which has the same conductivity type as the active layer, making it possible to prevent the occurrence of short circuit defects, and providing a highly reliable light emitting device. I can do it.
(2)上記(1)より、発光素子製造において、ショー
ト不良発生防止が図れることから、歩留の向上が図れ、
信頼度の高い発光素子を安価に製造することができる効
果を奏する。(2) From (1) above, it is possible to prevent the occurrence of short circuit defects in light emitting device manufacturing, thereby improving yield.
This has the effect that a highly reliable light emitting element can be manufactured at low cost.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。すなわち、Znおよび
Teの濃度値も実施例以外のものでもよい。ただし、T
e濃度はたとえばlXl018m、−3と高くすると結
晶性が悪くなるので注意を要する。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. That is, the concentration values of Zn and Te may also be other than those in the examples. However, T
If the e concentration is increased to, for example, lXl018m, -3, the crystallinity will deteriorate, so care must be taken.
また、熱処理後にパックディフュージョンが進む方向に
パックディフュージョン層と同じ導電型の領域を形成す
る素子構造で、パックディフュージョンでショートが起
るおそれのある場合にも同様に本発明は適用できる。Furthermore, the present invention is similarly applicable to cases where there is a risk of short-circuiting occurring in the pack diffusion in an element structure in which a region of the same conductivity type as the pack diffusion layer is formed in the direction in which the pack diffusion advances after heat treatment.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である発光ダイオード製造
技術に適用した場合について説明したが、それに限定さ
れるものではなく、たとえば、他の半導体装置の製造に
も適用できる。少なくとも、同一導電型領域の間に他の
導電型領域が存在するような構造の半導体装置の製造で
あって、かつその製造時の熱処理で1対の同一導電型領
域がパックディフュージョンで導通するおそれのある半
導体装置の製造方法に適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the light emitting diode manufacturing technology, which is the background field of application, but the invention is not limited thereto. It can also be applied to manufacturing. At least, manufacturing of a semiconductor device having a structure in which a region of another conductivity type exists between regions of the same conductivity type, and there is a risk that a pair of regions of the same conductivity type may become electrically connected due to pack diffusion during heat treatment during manufacturing. It can be applied to certain semiconductor device manufacturing methods.
第1図は本出願人の開発による発光素子の断面図、
第2図(a)〜(d)は本発明の一実施例による発光素
子の製造方法を示す断面図である。
1・・・発光素子、2・・・G a A−g A s体
、3・・・23層、4・・・23層(活性層)、5・・
・N層、6・・・N層層、7・・・P′層、8・・・ア
ノード電極、9・・・カソード電極、10・・・電流狭
窄層、11 ・近赤外光、12・・・G a A s板
、13・・・ウェハ。FIG. 1 is a sectional view of a light emitting device developed by the present applicant, and FIGS. 2(a) to 2(d) are sectional views showing a method for manufacturing a light emitting device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Light emitting element, 2... G a A-g As body, 3... 23 layers, 4... 23 layers (active layer), 5...
・N layer, 6... N layer, 7... P' layer, 8... anode electrode, 9... cathode electrode, 10... current confinement layer, 11 ・Near infrared light, 12 ...G a As plate, 13... Wafer.
Claims (1)
域を同時または別々に形成する工程と、加熱処理する工
程と、を有する半導体素子の製造方法であって、前記加
熱処理時に第2導電型決定不純物が第1導電型領域また
は第1導電型形成予定領域に拡散して両筒2導電型領域
が電気的に導通しないように、一方または両方の前記第
2導電型領域の不純物濃度は第1導電型領域の不純物濃
度に近似させておくことを特徴とする半導体素子の製造
方法。1. A method for manufacturing a semiconductor device, comprising the steps of simultaneously or separately forming a second conductivity type region sandwiching a first conductivity type region, and a heat treatment step, the method comprising the steps of: The impurity concentration in one or both of the second conductivity type regions is set so that the type determining impurity is diffused into the first conductivity type region or the first conductivity type formation region and the two cylinder conductivity type regions are not electrically conductive. A method for manufacturing a semiconductor device, characterized in that the impurity concentration is approximated to that of a first conductivity type region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58126047A JPS6018977A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58126047A JPS6018977A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6018977A true JPS6018977A (en) | 1985-01-31 |
Family
ID=14925330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58126047A Pending JPS6018977A (en) | 1983-07-13 | 1983-07-13 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6018977A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563235A (en) * | 1991-08-29 | 1993-03-12 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor element |
-
1983
- 1983-07-13 JP JP58126047A patent/JPS6018977A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0563235A (en) * | 1991-08-29 | 1993-03-12 | Shin Etsu Handotai Co Ltd | Manufacture of semiconductor element |
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