JPS60186932A - Arithmetic device - Google Patents

Abstract

PURPOSE:To attain an operation of an arithmetic device at a high speed by selecting the outputs of arithmetic circuits having carry inputs 0 and 1 respectively in response to the presence or absence of a carry given from a carry look-ahead circuit. CONSTITUTION:This arithmetic circuit is provided with the 1st and 2nd operand holding registers 1 and 2, arithmetic circuit blocks 3-1-3-4, carry look-ahead circuits 4 and 5 having carry inputs 1 and 0 to be applied to the lowest digit respectively, etc. Each of blocks 3-1-3-4 consists of adders 31 and 32 of carry inputs 1 and 0, selectors 33 and 34 of carry inputs 1 and 0 to be applied to the lowest digit respectively, a selector 35 which is selected by the carry output given from the highest digit, and an arithmetic result holding register 36. In case binary numbers A and B of 16 bits, for example, are calculated, the parallel additions are carried out for every 4 bits with blocks 3-1-3-4 respectively. Then the circuit 4 selects the selector 31 or 32 according to the presence or absence of a carry obtained through the prescribed addition of contents of registers 1 and 2.

Description

[Detailed Description of the Invention] [Technical Field] +Ih fIB kn-mockery ``Kanini-Hatsu-L/rtr Tori mo Ichigo Age Soderei 14; Tachibana, ^Relating to performance equipment.

For example, absolute value operations are often required in the operation of the mantissa part in floating-point operations. In this case, the problem is that from a certain number A (A〉0) to a certain number B (B〉
The problem is to perform the subtraction A-B, and when A>H, the positive sign and the value of its absolute value A-H are given as a result. , and A<B
In this case, a negative sign and its absolute value B-A should be given as a result.

[Prior art]

In conventional devices, this is done, for example, as shown below.

That is, A 0. Letting B>O, when finding the sign of A-H and its absolute value, take the complement of each digit of B and write it as ■, then B,..., F-B...・(1) becomes. However, F is a value with all the digits of interest being 11". Therefore, F+1=carry from the highest digit is 10.

Now, if we make X=A0B+1, then X=A+B+1 (A-B)+(F+1)...
...(2) When A>H, equation (2) becomes (A
B)+Carry from the highest digit.

On the other hand, when A<B, formula C) becomes
Taking the complement of each digit of X-1, X-1=F-(B −
A ) = B - A. To summarize the above, when A is 0 and B is 0, to find AB, first create X = A-1-B-4-1, and then find the highest digit. If a carry occurs from the highest digit, the result will be a positive sign, and the output X that ignores the carry from the highest digit will be the same as I.
A-Bl Totoru.

Also, if there is no carry from the highest digit, the result will be a negative sign, and x-1, which is the complement of each digit of x-1, will be I
In order to implement this in hardware, conventionally, as shown in FIG. 1, the first operand holding register 1 is
The following process is performed using a circuit consisting of a second operand 2', an arithmetic unit 3', a recombination circuit 4', a selector 5', and an arithmetic result holding register 6'.

That is, registers 1' and 2 store people, and register 2 stores people.
' is stored in advance with B obtained by taking the complement of each digit of B. The performer 3' is operated as an adder in which the carry force 1 is added to the lowest digit, and as a result, the output of the reenactor 3' is 3000'.
The above-mentioned X, tsumashi, and X=A-1-B+l occur.

The carry from the highest digit of the arithmetic unit 3' is output from the output 3001', which is used as the sign of the result as described above (if the output is @1'', it is a positive sign, and the output is 10 ”, a negative sign), selector 5'
used as a control signal for .

In other words, the carry output 3001' from the highest digit is 1"
In this case, the selector 5' selects the output 3000' of the arithmetic unit 3'
, and stores it in register 6'.

Further, when the output 3001' is 0'', the output of the recombination circuit 4' is selected and stored in the register 6'.

The combination circuit 6' subtracts 1 from the input X,
This is a circuit that performs an arithmetic operation x-1 that takes the complement of each digit.

From the foregoing explanation, it is clear that the above operation provides the correct sign at the multi-output 3000' and the correct absolute value of IA-Bl at the register 6''.

When the absolute value is an addition, A is stored in register 1' and B is stored in register 2'' as is, and arithmetic unit 3' is used as an adder with a carry input of 0 to the lowest digit. The selector 5' may be operated so that the selector 5' always selects the output 3000' side.

Now, according to the above configuration, in the case of absolute value subtraction, A(B
In this case, the output of the conjoint circuit 4' is selected, but this is the result of addition in the arithmetic circuit 3', and the performance time is longer because the above-mentioned concomitant operation is performed in kllr. It has the disadvantage that it takes a long time.

Particularly, when performing high-speed addition using the carry-overhead method in the arithmetic circuit 3' for the purpose of high-speed arithmetic, almost as much extra time is wasted for the recomplement circuit 4'. It has the disadvantage of being

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic device that eliminates the above-mentioned conventional drawbacks.

[Relatives of invention]

The equipment of the present invention is an arithmetic device that performs absolute value calculations and supports an arithmetic circuit using a carry-ahead, and includes an arithmetic circuit with O carry input, an arithmetic circuit with 1 carry manpower, and a carry head with 0 carry manpower. Lutsukuahead circuit,
Carry truck head circuit with 1 carry force and front 8
11. The present invention includes a circuit for selecting the output of the arithmetic circuit with zero carry input and the output of the arithmetic circuit with one carry input depending on whether or not there is a carry output from the carry lookahead circuit.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention. .

In this embodiment, an arithmetic circuit block 3-1 includes 1 operand holding register 1, 2 second operand holding registers, and 4 arithmetic circuit blocks 3-1.
, 3-2 , 3-3 , 3-4 , a carry-out look-ahead circuit 4 with a carry input of 1 to the lowest digit, and a carry-out look-ahead circuit 5 with a carry input of 0 to the lowest digit.

In addition, each arithmetic circuit block 3-1 to 3-4 includes an adder 31 for carry input 1, an adder 32 for carry input O, a selector 33 for carry human power 1 to the lowest digit, and a carry input 1 to the lowest digit. It includes a selector 34 requiring no human input, a selector 35 selected by the carry output from the highest digit, and an operation result holding register 36.

In this embodiment, for example, operations on a 16-bit binary number A and a 16-bit binary number B are handled, and each arithmetic circuit block 3-1 to 3-4 performs parallel addition of 4 bits each. 4 arithmetic circuit blocks 3-1, 3-2
, 3-3, and 3-4.

The carry address circuit 4 of the carry operator 1 calculates the above 4 when the contents of the first operand holding register 1 and the second operand holding register 2 are added under the condition that there is a carry input 1 to the lowest digit. It has four outputs for calculating and displaying the presence or absence of a carry from the lower order for each of the 4-bit blocks based on the carry overhead.

For example, the output 4001 for the arithmetic circuit block 3-1
-1 is the result of the above operation, and the circuit block 3-1 has a carry input from the lower block (4-bit block corresponding to the multi-circuit block 3-2) ('1#)
This is an output that displays whether the output is true or not (0'').

This output 11 is supplied as a control signal to select the input of the selector 33 of the carry input 1 in the corresponding arithmetic circuit block 3, and when there is a carry input, if this output is @1'', the carry signal is selected. Select the output 3100 side of the warmer 31 with human power 1 and output it to the output 3300. If there is no carry input, and if this output is 10", the output 3200 of the adder 32 with human power 0 is selected. The selected side is controlled to be output to the output 3300.

Similarly, when the carry-output circuit 5 with a carry input of 0 clears the contents of the first operand holding register 1 and the #L2 operand holding register 2 under the condition that the carry input from the lower order is 0, It has four outputs for calculating and displaying the presence or absence of a carry from the lower order for each of the above four 4-bit blocks based on the carry overhead. For example, as a result of the above calculation, the output 5001-1 to the circuit block 3-1 is output to the circuit block 3-1 from the lower block (Tsumashi platform block 3-2).
This is an output that indicates whether there is a carry input (11") from the 4-pitched book corresponding to (1') or not (@(1')).

This output is supplied as a control signal to select the input of the selector 34 of the carry input 0 in the corresponding arithmetic circuit block 3, and if there is a carry input, and if this output is '1#, Output 3 of adder with carry input 1
1004111, and further takes the complement of each digit and outputs it to output 3400, and if there is no carry input, then if this output is @0, it is an adder with 0 carry input. Select the output 3200 side of 32,
Furthermore, the complement of each digit is taken and the result is controlled to be outputted to the output 3400.

Further, the look-ahead circuit 5 with zero carry power outputs an output 500 indicating whether a carry output from the highest digit is generated (1") or not (+") as a result of the performance by the circuit 5 described above.
0, which corresponds to each arithmetic circuit block 3-1 to 3-3.
-4 is supplied as a control signal to select the input of the selector 35 selected by the carry output, and this selector 3
When a carry output of 5 occurs (in the case of @1”),
The output 3300 of the selector 33 for the carry input 1 is selected, and when the carry output does not occur (in the case of 10#), the output 3400 of the selector 34 for the carry input 0 is selected.

Next, for example, the arithmetic circuit block 3-1 has a 4-bit output corresponding to this block of the first operand holding register 1, and a 4-bit output corresponding to this block of the second operand holding register 2. Adder 3 adds , in parallel under the condition that the carry input from the lower order is 1.
1 and an adder 32 that adds the same as above in parallel under the condition that the carry input from the lower is 0, and the output 3100 of the adder 31 and the output 320 of the adder 32.
0 is the selector 33 of carry human power 1, respectively.
and a carry force 0 selector 34, respectively.

With the above configuration, the output 3300 of the selector 33 of each arithmetic circuit block 3 adds the contents of register 1 and register 2 under the condition that there is a carry input 1 to the lowest digit. Similarly, the output 3400 of the selector 34 of each arithmetic circuit block 3 is output from register 1 and register 2.
The result of adding the contents of and under the condition that the carry input to the lowest digit is O, and taking the complement of each digit, is
It is clear that the 4-bit output for the corresponding block is correctly provided.

Based on the above explanation, it can be seen that the calculation result holding register 36 of each calculation circuit block 3 stores downstream values.

Store A (where A>0) in younger brother 1 operand holding register 1, and store B (where B>0) in second operand holding register 2.
0, and B is a value with the complement of each digit of B).

In this way, if A0B outputs a carry from the highest digit, and if the output 5000 is '1', the calculation result holding register 36 of each calculation circuit block 3 will have the following information:
4 bits of the corresponding block are stored for the value of A+B when there is a carry force l to the lowest digit, and the value of A+B+1 ignoring the carry output from the highest digit.

As mentioned above, from B=F-B, A+l3=A+F-B=F+(AB), and a carry is output from the highest digit only when A-B)0. In this case, Since A+B+1=A-B-4- is a carry output from the highest digit, each operation result holding register 36 contains the correct 4 bits of the corresponding block of the value of A B in the case of A)H. It will be stored.

In addition, if A and B do not output a carry from the highest digit, and if the multi-output 5000 is 10'', a carry input to the lowest digit is input to the operation result holding register 36 of each arithmetic circuit block 3. When λ1B is 0, the value obtained by taking the complement of each digit of the value of λ0B, and 4 bits of the corresponding block corresponding to the value of λ1B is stored.

As mentioned above, not outputting a carry from the highest digit is
In the case of A<, B, in this case, it becomes , so in each operation result holding register 36, in the case of -, B, BA
4 bits of the block corresponding to the value will be stored correctly.

According to the above, in the case of jj), A'2Q, Bn0, perform subtraction A-B, and calculate its absolute value IA Bl and its sign S
To find out, each circuit block 3 obtained by storing A in the first operand holding register 1 and storing the value B obtained by taking the complement of each digit of B in the second operand holding register 2. -1 to 3-4 operation result holding register 3
If the outputs of 6 are combined in parallel, IA-Bl is obtained, and the carry output 5000 from the highest digit of the carry scan head circuit 5 at this time gives the sign of this subtraction result. However, 11'' of the carry output 5000 represents a positive sign, and 0'' of the carry output 5000 represents a negative sign. Also, if the result is 00, a negative sign appears.

As described above, according to this embodiment, the calculation is performed when the carry input to the lowest digit is 1, and when the carry input to the lowest digit is 0.
By performing the calculations in the case of A in parallel by providing a carry-out look-ahead circuit for each and an adder for it, and selecting the result of the calculation according to the carry output from the highest digit, jj), A ) The result for H is also
The result in the case of A<:B is also the same as the carry-out look-ahead circuit 5.
This will be obtained at the same time as the output of . As a result, a computation speed approximately twice as fast as that of the conventional method described above can be obtained.

Note that the above has been described in detail for the case of performing subtraction A-B in the case of A>O, B)Q, but in order to be able to perform addition A-1-B as well, it is necessary to The configuration of the selector 34 for human power O and the selector 35 selected by the carry output may be as shown in FIG.

That is, in place of the selector 34 with the carry input 0, one of the outputs 3100 and 3200 is selected as the selector 34-M with the carry input 0 shown in FIG. 3, and each bit of this is inverted. In addition to the above-mentioned output 3400 that outputs (takes the complement of each digit and outputs it), we separately provide an output 3401 that does not invert even if it is selected.
Selector 35-M selected by the carry output shown in the figure.
supply to.

Therefore, the selector 35-M outputs 3300 and 3400.
and the newly installed output 340], making it a three-person selector. In addition to the output 5000 from the same circuit 5 as described above, the control signal for selecting the input for this also supplies a subtraction mode signal 3500, and in the case of absolute value subtraction, this reduction mode signal 3500 is If absolute value addition is to be performed, it is supplied as 10''. Then, the selector 35-M selects one of the three manual forces, as indicated by the circle in FIG. 4, according to the combination of the output 5000 as a control signal and the subtraction mode signal 3500. This is stored in the calculation result holding register 36.
Store in.

As is clear from FIG. 4, in the case of absolute value subtraction (when the subtraction mode signal 3500 is '1'), the selector 34-
Since M and selector 35-M perform operations completely isometric to the aforementioned selector 34 and selector 35, respectively, the operation is exactly the same as the absolute value subtraction described in detail above.

On the other hand, in the case of absolute value addition, etc., the reduction mode signal 3500 is 60''k, and as a result, the selector 35-M outputs a signal like the carry output 5000 from the highest digit of the carry-out look-ahead circuit 5. Regardless of the condition, the non-inverted output 3401 of the selector 34-M is always selected and is supplied to and stored in the operation result holding register 36. Therefore, A is stored in the first open holding register 1, and B is left unchanged. By storing the results in the second operand holding register 2, the results of A-1-H are obtained in the operation result holding register 36 in the column.

Please note that the above is an explanation of one embodiment of the present invention, and the present invention is not limited to this.9 For example, in this embodiment, each arithmetic circuit block 3 performs a four-bit operation. However, this example is not limited to this.

In this embodiment, the selection control signal of the selector 35 which is selected by the carry output from the highest digit is the carry output from the highest digit of the carry forward circuit 5 when the carry output to the lowest digit is 0. I used an output of 5000,
This can also be done by using the carry output from the highest digit of the carry forward circuit 4 of the carry input 1 to the lowest digit.

〔Effect of the invention〕

As described above, according to the present invention, the speed of absolute value subtraction performed using a carry-over head circuit can be increased rapidly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 4 is a diagram for explaining this operation. In the figure, 1, old, first operand holding register,
2...Second operand holding register, 3-1~
3-4... Arithmetic circuit block, 4...
Carry lookahead circuit with 1 carry input to the lowest digit, 5... Carry lookahead circuit with 0 carry input to the lowest digit, 31... Adder with 1 carry input, 32 ...Adder with carry input 0, 33...Selector with carry input l to the lowest digit, 34.34-M...Carry manual power to the lowest digit 0 selector, 35°35-M...Selector selected by carry output from the highest digit, 36...
- Operation result holding register. h l Figure z 4 Figure

Claims (1)

[Claims] In an arithmetic device that performs an absolute calculation and has a performance circuit using a carry-forward operation, there is an arithmetic circuit with a carry input of 0, a carry-out operation circuit with a carry force of 1, a carry-out operation circuit with a carry input of O, and a carry-out circuit with a carry force of 1. Depending on the presence or absence of the carry output from the look-ahead circuit and the previous We carry look-ahead circuit, the output of the arithmetic circuit with the carry manpower of 0 and the carry manpower of 1
3. A performance device comprising: an output of a performance circuit; and a selection circuit.