JPS60185421A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS60185421A
JPS60185421A JP4051884A JP4051884A JPS60185421A JP S60185421 A JPS60185421 A JP S60185421A JP 4051884 A JP4051884 A JP 4051884A JP 4051884 A JP4051884 A JP 4051884A JP S60185421 A JPS60185421 A JP S60185421A
Authority
JP
Japan
Prior art keywords
capacitor
potential
amplifier
circuit
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4051884A
Other languages
Japanese (ja)
Inventor
Mitsuru Kudo
満 工藤
Shigeaki Kanari
金成 重明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Image Information Systems Inc
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Video Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Video Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP4051884A priority Critical patent/JPS60185421A/en
Publication of JPS60185421A publication Critical patent/JPS60185421A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H11/12Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To obtain an integrated active high-pass filter having a desired high- pass filter characteristic by using a junction capacitance for a capacitance of a time constant circuit of an active secondary high pass filter circuit to absorb a characteristic variation of the time constant circuit. CONSTITUTION:Resistors R1, R2 and capacitors C1, C2 are components for a time constant circuit of the secondary high pass filter, the C1, C2 are constituted of junction capacitors, and the resistance value of resistors R2, R3 is identical. Then two input terminal DC voltages of an amplifier 7 is equal to each other independently of an output voltage Va of a variable voltage source V6 and an output terminal DC potential of the amplifier 7 is always a prescribed potential VC. A signal superimposing an output signal vin of a signal source 6 on the DC potential Va is outputted from an output terminal of the signal source 6. Thus, the voltage applied across the capacitor C1 is (Vc-Va). The voltage applied across the capacitor C2 is also (Vc-Va) and the voltage applied across the capacitor is changed by adjusting the potential Va of the variable voltage source V6.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、ICと称される集積回路に関するものであり
、更に詳しくは、高域通過フィルタ(バイパスフィルタ
)として用いるのに好適な集積回路に関するものである
Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to an integrated circuit called an IC, and more particularly to an integrated circuit suitable for use as a high-pass filter (bypass filter). It is something.

〔発明の背景〕[Background of the invention]

電気回路の集積化(モノリシックIC化、以下単にIC
化と略す)が進むにつれ、外付のブロックフィルタのI
C化が、回路の小形化、低コスト化を実現する上で重要
な課題となりつつある。
Integration of electrical circuits (monolithic IC, hereinafter simply IC)
(abbreviated as "I") progresses, the I
C conversion is becoming an important issue in realizing circuit miniaturization and cost reduction.

従来のフィルタは大部分がインダクタンスL1容量C1
抵抗几で構成されているが、インダクタンスLはIC化
が難しいため従来形式のフィルタの集積化は困難である
。このため容量C1抵抗Rと増幅器で構成可能なアクテ
ィブフィルタがIC化には適している。
Most conventional filters have inductance L1 and capacitance C1.
Although it is composed of a resistor, the inductance L is difficult to integrate into an IC, making it difficult to integrate a conventional filter. For this reason, an active filter that can be configured with a capacitor C1 resistor R and an amplifier is suitable for IC implementation.

第1図に、IC化に適したかかる帰還形アクティブフィ
ルタの従来の回路例を示し説明する。同図において、1
は信号入力端、2は信号出力端、3は利得にの増幅器、
抵抗RはR1とR2、容量CはC1とC2から成ってい
る。この時、入力端1の入力信号を■□、出力端2の田
力信号をv2とすると、伝達関数−は次の如く表わせる
O Vl ・・・・・・(1) 共振周波数f。と回路の良さQは次の如く表わせる。
FIG. 1 shows a conventional circuit example of such a feedback type active filter suitable for IC implementation and will be described. In the same figure, 1
is the signal input terminal, 2 is the signal output terminal, 3 is the gain amplifier,
The resistance R consists of R1 and R2, and the capacitance C consists of C1 and C2. At this time, if the input signal at the input end 1 is □ and the signal at the output end 2 is v2, the transfer function - can be expressed as follows: O Vl (1) Resonant frequency f. The quality Q of the circuit can be expressed as follows.

(但し5−j41+) しかし上記構成のアクティブフィルタ(バイパスフィル
タ)をIC化しようとする場合、使用する回路緊子の抵
抗蝕なら抵抗値、容量値なら容量値のバラつきの問題が
生じる。すなわちIC内の容量値、抵抗値は半導体内の
不純物濃度、製造時におけるマスクずれなどによるバラ
つきの影譬を受け、−例として容量Cの絶対値で±20
チ、抵抗Rの絶対値で±15チ、程度の大きな変動があ
る。
(However, 5-j41+) However, when attempting to integrate the active filter (bypass filter) having the above configuration, a problem arises in that the resistance value of the circuit board used varies, and the capacitance value varies. In other words, the capacitance value and resistance value within an IC are subject to variations due to impurity concentration within the semiconductor, mask misalignment during manufacturing, etc.;
There is a large fluctuation of ±15 cm in the absolute value of the resistance R.

したがって第1図に示したフィルタ(詳しくは2次バイ
パスフィルタ)のカットオフ周11& f。
Therefore, the cutoff circumference 11&f of the filter (more specifically, the secondary bypass filter) shown in FIG.

も第2図に見られるように周波数aからbの範囲で変動
し、上記数値列では最悪時カットオフ周波数f。は±3
5チ(±20チと±15tsの和)変動することとなり
、このように特性の変動幅が大きくては実用に供せない
という問題がある。
As shown in FIG. 2, the frequency also fluctuates in the frequency range from a to b, and in the above numerical sequence, the worst-case cutoff frequency is f. is ±3
This results in a fluctuation of 5 ts (the sum of ±20 ts and ±15 ts), and there is a problem that such a large variation range of characteristics cannot be put to practical use.

この対策としては、ICチップ上でレーザトリミングを
実施するなどして抵抗値を変化させ、抵抗値のバラつき
を吸収することも行なわれているが、精度、歩留り、コ
ストの面などでまだ多くの問題点があり、一般民生用I
Cにまで実用化されるには至っていない。
As a countermeasure to this problem, the resistance value is changed by laser trimming on the IC chip to absorb the variation in resistance value, but there are still many problems in terms of accuracy, yield, cost, etc. There are some problems, and it is not suitable for general consumer use.
It has not yet been put to practical use in C.

またアクティブフィルタを構成する容量に接合容量を用
い、接合容量のもつ容量絶対値のバイアス依存性を利用
し容量値を可変して、抵抗値及び容量値の絶対値バラつ
きを吸収する方法もある。
Another method is to use a junction capacitor as the capacitor constituting the active filter, and to vary the capacitance value by utilizing the bias dependence of the absolute capacitance value of the junction capacitor, thereby absorbing variations in the absolute values of the resistance value and the capacitance value.

かかる方法を実施したアクティブ2次ローパスフィルタ
の従来の回路例を第3図に示す。同図において、4は信
号入力端、5は2次ローパスフィルタの出力端、容量C
はC3〜C5、抵抗RはR4〜R12と”21 t R
22N1)ランジスタQはQINQloでNPN)ラン
ジスタ、■1〜I7は定電流源、■3と■4は定電圧源
、v5は可変電圧源、ローパスフィルタの時定数回路は
抵抗R21r FL22と容量(ただし接合容量) C
a e C4から構成されている。
FIG. 3 shows a conventional circuit example of an active secondary low-pass filter implementing such a method. In the figure, 4 is the signal input terminal, 5 is the output terminal of the second-order low-pass filter, and the capacitor C
is C3 to C5, and the resistance R is R4 to R12.
22N1) transistor Q is QINQlo and NPN) transistor, ■1 to I7 are constant current sources, ■3 and ■4 are constant voltage sources, v5 is a variable voltage source, the time constant circuit of the low-pass filter is resistor R21r FL22 and capacitor (however Junction capacitance) C
It is composed of a e C4.

トランジスタQa 、 C7と抵抗比7〜R9と定電流
源I5で利得Klの第1の増幅器を構成している。また
トランジスタQ9 e QIOと抵抗RIO−R1!と
定電流源■7で利得Klの第2の差動増幅器を構成して
いる。
The transistors Qa and C7, the resistance ratios 7 to R9, and the constant current source I5 constitute a first amplifier with a gain of Kl. Also, transistor Q9 e QIO and resistor RIO-R1! A second differential amplifier with a gain of Kl is constructed by the constant current source (7) and the constant current source (7).

抵抗R4とR5はトランジスタQa トQ4のベース電
位直流電位を等しくするためのものである。同様に抵抗
R6はトランジスタQ6とQ9のベース直流電位を等し
くするためのものである。
The resistors R4 and R5 are used to equalize the base potential and DC potential of the transistor Qa and Q4. Similarly, the resistor R6 is used to equalize the base DC potentials of the transistors Q6 and Q9.

かかる構成の集積化回路において第1の差動増幅器のト
ランジスタQ6のベース電位と、第2の差動増幅器のト
ランジスタQ9のベース電位は等5− しくなり、またトランジスタQ7とQloのベースは可
変電圧源V5に共通に接続されているのでトランジスタ
Q7とQIOのコレクタ電位は共通に可変電圧源v6の
電位により変化する。
In an integrated circuit having such a configuration, the base potential of the transistor Q6 of the first differential amplifier and the base potential of the transistor Q9 of the second differential amplifier are equal to each other, and the bases of the transistors Q7 and Qlo are connected to a variable voltage. Since they are commonly connected to the source V5, the collector potentials of the transistors Q7 and QIO are commonly changed by the potential of the variable voltage source v6.

したがって接合容量で構成される容量C3とC4の両端
の印加電圧は等しく変化し、容fleaとC4の絶対値
は可変電圧源v5の直流電圧により等しい割合で変化す
る。これにより時定数回路の抵抗Rgl a R22と
容量cs s C4の値にバラツキがあってもこれを吸
収できる(抵抗値のバラツキも容量値のバラツキに換算
して吸収することが出来る)。
Therefore, the voltages applied across capacitors C3 and C4, which are constituted by junction capacitors, change equally, and the absolute values of capacitors flea and C4 change at an equal rate depending on the DC voltage of variable voltage source v5. Thereby, even if there are variations in the values of the resistor Rgla R22 and the capacitor css C4 of the time constant circuit, this can be absorbed (variations in resistance values can also be absorbed by converting them into variations in capacitance values).

しかしアクティブ2次バイパスフィルタを接合容量を用
いて集積回路で実現する時には、アクティブ2次關−バ
スフィルタの場合と人なり以下の問題がある。
However, when an active secondary bypass filter is implemented using an integrated circuit using a junction capacitance, there are the following problems compared to the case of an active secondary bypass filter.

四−バスフィルタでは13図に示すように増幅器の1方
の入力端にあたるトランジスタQ6のベース直流電位が
抵抗”41 eR22を介して定まる。
In the four-bus filter, as shown in FIG. 13, the base DC potential of the transistor Q6, which corresponds to one input terminal of the amplifier, is determined via the resistor "41eR22."

このため増幅器の他方の入力端直流電圧をVsで可変す
ることにより、増幅器の出力電圧が変わり、6一 接合容量からなる容NC3の印加電圧が変化し容量値を
変化させることができる。また容量C4も同様な方法で
容量値を調整できるわけである。ところがバイパスフィ
ルタでは、入力信号が容量結合で入力される形式となり
、第3図の四−パスフィルタの回路で云うと、時定数回
路を構成するR(几21.几22)とC(Ca p C
4)が丁度入れ換わった形となってアクティブ2次バイ
パスフィルタが構成されることになるので、直流電位が
Cによってカットされて次段へ伝わらず、従ってバイパ
スフィルタとして正常に動作せず、また可変電圧源v5
の電圧を調整しても容量値は変化せず、バラツキが吸収
されないから所望特性は得られない。
Therefore, by varying the DC voltage at the other input end of the amplifier with Vs, the output voltage of the amplifier changes, and the voltage applied to the capacitor NC3 consisting of 6-junction capacitance changes, making it possible to change the capacitance value. Further, the capacitance value of the capacitor C4 can be adjusted in a similar manner. However, in a bypass filter, the input signal is input through capacitive coupling, and in the four-pass filter circuit shown in Figure 3, R (几21.几22) and C (Ca p C
4) is exactly swapped to form an active secondary bypass filter, so the DC potential is cut by C and is not transmitted to the next stage, so it does not function normally as a bypass filter, and variable voltage source v5
Even if the voltage is adjusted, the capacitance value does not change, and the desired characteristics cannot be obtained because variations are not absorbed.

〔発明の目的〕[Purpose of the invention]

本発明は、上述のような従来の技術的問題を解決するた
めになされたものであり、従って本発明の目的は、バイ
パスフィルタを構成した場合でも、直流電位がCによっ
てカットされることなく次段に伝わり、しかも使用して
いる接合容量が可変電圧源による印加電圧の調整を受け
てその容量値が変化し、バラツキの吸収が可能であるよ
うなJa積回路を提供することにある。
The present invention has been made to solve the conventional technical problems as described above, and therefore, an object of the present invention is to prevent the DC potential from being cut by C even when a bypass filter is configured. It is an object of the present invention to provide a Ja product circuit in which the capacitance value is changed by adjusting the applied voltage by a variable voltage source, and in which variations can be absorbed.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明による集積回路は、2
入力端をもつ増幅器の一方の入力端に、可変電圧源によ
って与えられる直流電位に重畳された交流入力信号を、
第1の容量と第2の容量の直列接続を介して入力し、前
記直流電位を第1の抵抗を介して前記増幅器の一方の入
力端に、また第2の抵抗を介して前記増幅器の他方の入
力端に、それぞれ接続し、該増幅器の出力端を第3の抵
抗を介して前記第1の容量と第2の容量の接続点に接続
して成る集積回路において、前記第1および#I2の各
容量を接合容量で構成し、前記直流電位を可変させるこ
とにより前記第1および第2の容量値を一様に同じ割合
で可変させるようにしたことを特徴としている。
In order to achieve the above object, an integrated circuit according to the present invention comprises two
An alternating current input signal superimposed on a direct current potential provided by a variable voltage source is applied to one input terminal of an amplifier having an input terminal.
input via a series connection of a first capacitor and a second capacitor, and the DC potential is input to one input terminal of the amplifier via a first resistor and to the other input terminal of the amplifier via a second resistor. and an output end of the amplifier is connected to a connection point between the first capacitor and the second capacitor via a third resistor. Each of the capacitances is constituted by a junction capacitance, and by varying the DC potential, the first and second capacitance values are uniformly varied at the same rate.

〔発明の実施例〕[Embodiments of the invention]

次に図を参照して本発明の詳細な説明する。 The present invention will now be described in detail with reference to the drawings.

第4図は本発明の一実施例を示す回路図である。FIG. 4 is a circuit diagram showing one embodiment of the present invention.

同図において、6は信号源、7は2人力増幅器、v6は
nr変電圧1、R1〜Rs ハ抵抗R,CI # C2
は容量Cである。
In the same figure, 6 is a signal source, 7 is a two-power amplifier, v6 is nr variable voltage 1, R1 to Rs c resistance R, CI # C2
is the capacitance C.

抵抗几1 e R2と容量C1a C2は2次バイパス
フィルタ(#!4図の回路)の時定数回路で、容量C1
e C2は接合容量で構成されており、抵抗R2とR3
の抵抗値は等しい。この時、増幅器702つの入力端直
流電圧は、可変電圧源■6の出力電圧vaにかかわらず
等しくなり、増幅器7の出力端直流電位は常に一定電位
Vcとなる。
Resistor 几1e R2 and capacitor C1a C2 is the time constant circuit of the secondary bypass filter (#! 4 circuit), and capacitor C1
e C2 is composed of junction capacitance, and resistors R2 and R3
have the same resistance value. At this time, the DC voltages at the input terminals of the two amplifiers 70 are equal regardless of the output voltage va of the variable voltage source 6, and the DC potential at the output terminal of the amplifier 7 is always a constant potential Vc.

また信号源6の出力端では、直流電位Va上に信号源6
の出力信号vinが重畳される波形となって信号が出力
される。したがって容量C1の両端の印加電圧は(Vc
 Va)となる。また容量C2の両端の印加電圧も(V
c Va)となり、容量CI。
Furthermore, at the output end of the signal source 6, the signal source 6 is placed on the DC potential Va.
A signal is output as a waveform on which the output signal vin is superimposed. Therefore, the voltage applied across capacitor C1 is (Vc
Va). The voltage applied across the capacitor C2 is also (V
c Va), and the capacity CI.

C2の両端の印加電圧はともに(Me Va)と等しく
なり、可変電圧源■6の電位■aの調整により容量両端
の印加電圧を変えることができる。
The voltages applied across C2 are both equal to (Me Va), and the voltages applied across the capacitor can be changed by adjusting the potential ■a of the variable voltage source ■6.

かかる構成により時定数回路の抵抗R1、R2と容量C
1,C2の絶対値バラつきを接合容量を用いた容量C1
* czの容量値調整で吸収できる。また直流電位も抵
抗R2s R3、増幅器7を介して次段へ伝わるので、
陪4図に示した如き回路(2次バイパスフィルタ)を多
段に接続して更に高次のバイパスフィルタを構成するこ
とも可能になる。
With this configuration, the resistances R1 and R2 and the capacitance C of the time constant circuit
1, capacitance C1 using junction capacitance to calculate the absolute value variation of C2
* Can be absorbed by adjusting the capacitance value of cz. Also, since the DC potential is also transmitted to the next stage via resistors R2s R3 and amplifier 7,
It is also possible to configure a higher-order bypass filter by connecting circuits (second-order bypass filters) as shown in FIG. 4 in multiple stages.

#I5図は本発明の更に具体的な実施例を示す回路図で
ある。同図において、8は信号入力端、9は出力端、抵
抗”1t”2と容量C1’ + C2は時定数回路、容
量C6は入力信号の容量結合用である。
#I5 is a circuit diagram showing a more specific embodiment of the present invention. In the figure, 8 is a signal input terminal, 9 is an output terminal, a resistor "1t" 2 and a capacitor C1' + C2 are a time constant circuit, and a capacitor C6 is for capacitive coupling of input signals.

トランジスタQはQ11〜Q15がNPN)ランジスタ
s III〜Illは定電流源、■7は定電圧源、抵抗
R111iとトランジスタQta e C14と定電流
源111で増幅器(第4図における増幅器7に相当)を
構成している。v6は可変電圧源で、抵抗R13とR1
4はトランジスタQ11とC120ベースの直流電位を
等しくするためのものである。
Transistor Q (Q11 to Q15 are NPN) transistor s III to Ill are constant current sources, ■7 is a constant voltage source, resistor R111i, transistor Qta e C14, and constant current source 111 form an amplifier (corresponding to amplifier 7 in Fig. 4) It consists of v6 is a variable voltage source, resistors R13 and R1
4 is for making the DC potentials of the bases of the transistors Q11 and C120 equal.

仮ニトランジスタのベース電流によるベース入力抵抗の
電圧降下を無視すると、トランジスタQllとC12の
ベース電位は等しい。さらに定電流源■8とI9の電流
値を等しくするとトランジスタQllとC12のエミッ
タ電位も等しい0また抵抗R2によるトランジスタQ1
3のベース電流の電圧降下も生じないのでトランジスタ
Q13のベース電位もトランジスタQllのエミッタ電
位に等しくなる。
Ignoring the voltage drop across the base input resistance due to the base current of the hypothetical two transistors, the base potentials of the transistors Qll and C12 are equal. Furthermore, when the current values of the constant current sources 8 and I9 are made equal, the emitter potentials of the transistors Qll and C12 are also equal to 0. Also, the transistor Q1 due to the resistor R2
Since no voltage drop occurs in the base current of transistor Q13, the base potential of transistor Q13 also becomes equal to the emitter potential of transistor Qll.

トランジスタQ13とC14のベース電位IIt、い。Base potential IIt of transistors Q13 and C14.

でトランジスタQ14のコレクタ電位は一定となり、容
量Ct e ”2と抵抗R1の接続点も一定となる。
Then, the collector potential of the transistor Q14 becomes constant, and the connection point between the capacitor Cte ''2 and the resistor R1 also becomes constant.

したがって可変電圧源■6の電圧に応じて接合容量から
なる容量C1と02の絶対値を可変できる。
Therefore, the absolute values of the capacitances C1 and 02, which are junction capacitances, can be varied in accordance with the voltage of the variable voltage source 6.

なお接合容量のバイアス電圧依存性は第6図に一例とし
て示したような特性である。
The bias voltage dependence of the junction capacitance is as shown in FIG. 6 as an example.

第6図において、φは拡散電位(bun t 1npo
tential )といい、通常約0.6〜0.7Vで
ある〇したがって第6図より、接合容量に印加する接合
電圧が0.7Vから4.7V程度まで変わりつる時、接
合容量の容量値が±3596程度変化することが認めら
れ、これにより時定数回路の絶対値バラつきを吸収する
ことができる。
In FIG. 6, φ is the diffusion potential (bun t 1npo
(tential) and is usually about 0.6 to 0.7V. Therefore, from Figure 6, when the junction voltage applied to the junction capacitance changes from about 0.7V to about 4.7V, the capacitance value of the junction capacitance changes. It is recognized that the variation varies by about ±3596, and this allows absorption of variations in the absolute value of the time constant circuit.

第5図の実施例で説明すると、定電圧源■7を9V、l
−ランジスタQ15のエミッタ電位を7vとすると、可
変電圧IVsの電圧を約3.7V〜7.7V程度可変す
ることにより容量C1とC2の絶対容量値を±35%程
度可変することができる。
To explain using the example of FIG. 5, constant voltage source 7 is 9V, l
- If the emitter potential of the transistor Q15 is 7V, the absolute capacitance values of the capacitors C1 and C2 can be varied by about ±35% by varying the voltage of the variable voltage IVs from about 3.7V to 7.7V.

なお第5図における実inでは、アクティブ2次バイパ
スフィルタ一段を構成した例を示したが、本発明は一段
の2次形に限定されるものではなく、2大形バイパスフ
ィルタを1段縦続接続し高次のバイパスフィルタを構成
する場合にも適用できるものであることは容易に明らか
であろう。
Although the actual example in FIG. 5 shows an example in which one stage of active secondary bypass filter is configured, the present invention is not limited to a single stage of quadratic type, and two large bypass filters are connected in cascade in one stage. It is readily apparent that the present invention can also be applied to constructing a high-order bypass filter.

また第5図に示した実施例の回路で、低電源電圧化を計
る上で、トランジスタQ15 # Qlt t C12
のNPN)ランジスタをPNP )ランジスタに変えた
り、直流シフト回路を設けたりしても本質的に回路動作
が変わらない事は明白であろう。
In addition, in the circuit of the embodiment shown in FIG. 5, in order to lower the power supply voltage, the transistor Q15 # Qlt t C12
It is obvious that the circuit operation will not essentially change even if the NPN) transistor is replaced by a PNP) transistor or a DC shift circuit is provided.

また本発明による回路を第3図に示したようなアクティ
ブ2次ローパスフィルタ等と組合せてバンドパスフィル
タ回路を構成することも可能であり、このようにアクテ
ィブバンドパスフィルタ回路においても本発明を利用す
ることもできる。
It is also possible to configure a bandpass filter circuit by combining the circuit according to the present invention with an active secondary low-pass filter as shown in FIG. You can also.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば抵抗と容量と増幅
器からなるアクティブ2次ノ1イノ々スフィルタ回路等
でその時定数回路の特性バラつきを、該時定数回路の容
量に接合容量を用いることにより吸収でき、所望のバイ
パスフィルタ特性を持つ集積化アクティブバイパスフィ
ルタ回路が得られ、従来外付部品であったブロックフィ
ルタを集積化でき、回路の小形化、低コスト化を図る上
で有効であるという利点がある。
As explained above, according to the present invention, variations in characteristics of a time constant circuit in an active second-order innovation filter circuit or the like consisting of a resistor, a capacitor, and an amplifier can be suppressed by using a junction capacitor as the capacitor of the time constant circuit. It is possible to obtain an integrated active bypass filter circuit with the desired bypass filter characteristics, and it is possible to integrate block filters that were conventionally external components, which is effective in reducing the size and cost of the circuit. There is an advantage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は帰還形アクティブフィルタの従来例を示す回路
図、第2図は第1図に示したフィルタの特性を示すグラ
フ、#!3図はアクティブ2次ローパスフィルタの従来
例を示す回路図、第4図は本発明の一実施例を示す回路
図、第5図は本発明の更に翼体的な実施例を示す回路図
、第6図は接合容量のバイアス電圧依存性を示すグラフ
、である。 符号説明 R1を几2 t C1p C2・・・・・・時定数回路
、7・・・・・・増幅器、■6・・・・・・可変電圧源 第1図 第2図 第 4 図 115図 第6 図 !・蛋 I8を圧(労りん)〔■〕
Fig. 1 is a circuit diagram showing a conventional example of a feedback type active filter, Fig. 2 is a graph showing the characteristics of the filter shown in Fig. 1, and #! 3 is a circuit diagram showing a conventional example of an active secondary low-pass filter, FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a circuit diagram showing a further wing-like embodiment of the present invention. FIG. 6 is a graph showing the bias voltage dependence of junction capacitance. Symbol explanation R1 2 t C1p C2...Time constant circuit, 7...Amplifier, ■6...Variable voltage source Fig. 1 Fig. 2 Fig. 4 Fig. 115 Figure 6!・Press the egg I8 (Rin) [■]

Claims (1)

【特許請求の範囲】[Claims] 1)2入力端をもつ増幅器の一方の入力端に、可変電圧
源によって与えられる直流電位に重畳された交流入力信
号を、第1の容量と第2の容量の直列接続を介して入力
し、前記直流電位を第1の抵抗を介して前記増幅器の一
方の入力端に、また第2の抵抗を介して前記増幅器の他
方の入力端に、それぞれ接続し、該増幅器の出力端を第
3の抵抗を介して前記第1の容量と第2の容量の接続点
に接続して成る集積回路において、前記第1および第2
の各容量を接合容量で構成し、前記直流電位を可変させ
ることKより前記第1および第2の容量値を一様に同じ
割合で可変させるようにしたことを特徴とする集積回路
1) inputting an AC input signal superimposed on a DC potential provided by a variable voltage source to one input terminal of an amplifier having two input terminals via a series connection of a first capacitor and a second capacitor; The DC potential is connected to one input terminal of the amplifier via a first resistor and to the other input terminal of the amplifier via a second resistor, and the output terminal of the amplifier is connected to a third input terminal. In the integrated circuit, the first and second capacitors are connected to a connection point between the first capacitor and the second capacitor via a resistor.
An integrated circuit characterized in that each of the capacitances is constituted by a junction capacitance, and by varying the DC potential, the first and second capacitance values are uniformly varied at the same rate.
JP4051884A 1984-03-05 1984-03-05 Integrated circuit Pending JPS60185421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4051884A JPS60185421A (en) 1984-03-05 1984-03-05 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4051884A JPS60185421A (en) 1984-03-05 1984-03-05 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS60185421A true JPS60185421A (en) 1985-09-20

Family

ID=12582732

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4051884A Pending JPS60185421A (en) 1984-03-05 1984-03-05 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS60185421A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01279616A (en) * 1988-05-06 1989-11-09 Hitachi Ltd Semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01279616A (en) * 1988-05-06 1989-11-09 Hitachi Ltd Semiconductor integrated circuit

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