JPS601845A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area of a chip by forming the occupying area of a circuit pattern having gathered functions in one chip in superposed shape by symmetrical conversion, thereby improving the wiring efficiency, raising the signal transmitting speed by the reduction of the wiring length and reducing necessary wiring area. CONSTITUTION:The shape that a block profile 1A and X-axis symmetrical shape 2A are superposed is provided. The symmetrical shape is not limited to axial symmetry. If such a shape is provided, the position of a terminal can be altered without substantially altering the block pattern without varying the block position and the occupying region shape even after the disposition of the block is decided. In this manner, the position of the terminal is selected in response to the interblock wiring pattern, thereby alleviating the wasteful creepage of the wirings between the blocks.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device (hereinafter referred to as an IC), and particularly to an improvement in a design method using a block method.

When designing a pattern for an IC, the IC is usually divided into sections having a set of functions, and the mutual layout of these sections and the detailed pattern design are carried out in different dimensions. Building a more standardized version of this,
There is a block method.

Elements with unit functions, or blocks that combine them, are designed and registered in advance, and when the entire design is actually designed, only the layout of the blocks and the wiring between the blocks are done to improve work efficiency. In particular, in the master slicing method used in gate arrays, etc., a common base pattern is prepared for a wide variety of products.
Additionally, the design is carried out using the building block method, which is limited to the wiring system only.

However, by separating the pattern design into the inter-block level and the block-internal level, some disadvantages have arisen. When wiring between blocks, actually the terminals set for each block are connected. Although the position of this block terminal has a great influence on the wiring pattern between blocks, it is hardly considered at the stage of designing the inside of the block. This occurs because before block placement, it is uncertain which direction the wiring will be connected to.

Inappropriate terminal positions cause unnecessary wiring and an increase in the number of crossovers between multilayer wiring, and local overcrowding of wiring leads to a shortage of wiring area. Such an example is shown in FIG. Between block A and block group B, terminal a1. a2... and the corresponding terminal b1. b2
Although the wires are connected between ..., there are many wires that go around block A.

As a countermeasure, the installation of 14th terminals is currently being implemented. As shown in Fig. 2 (6), common terminals have the same potential terminals on opposite sides of the block frame 4, and equipotential terminals (11, 12) depending on the wiring direction from other blocks. You can select one each from and (21, 22). An example of this is shown in FIG. 2 (b). Blocks C and D are arranged as shown in the figure. Gin potential terminal (CII C2) and (dl, d
When considering the connection only between 2), route m is shorter than route t, and it is more advantageous to wire it with cl-d2. However, wiring between equipotential terminals within a block always adds some amount of each award to the inter-block arrangement, deteriorating the signal transmission speed between blocks. Moreover, the wiring pattern 3 shown in FIG. 2(5) is intended to be an equipotential terminal, and does not cross the inside of the block, thus becoming a hindrance to other internal wiring. In fact, as the intra-block wiring pattern becomes more complex, it becomes more difficult to set equipotential terminals.

If you change the block position according to the wiring congestion, the above method is unnecessary, but if you move some blocks of the block group whose placement has been determined, it may change the relative relationship with other blocks, etc. More extensive block rearrangement becomes necessary.

The present invention is characterized in that the shapes of the areas occupied by these blocks form a pattern M in which the symmetrical transformation wave and the symmetrical transformation wave overlap before the symmetrical transformation.

This makes it possible to obtain the same effect as providing multiple equipotential terminals.

An example is given below and explained. First, when designing a block pattern, as shown in FIG. 3, a shape is provided so that the block outer shape IA and its X-axis symmetrical shape overlap. Symmetry is not limited to axial symmetry.

If such a shape is provided, it becomes possible to change the terminal position without changing the block position or occupied area shape even after the block arrangement is determined, and without changing the block pattern substantially. This makes it possible to select terminal positions according to the inter-block wiring pattern and reduce unnecessary routing of inter-block wiring. When the present invention is applied to block A in FIG. 1, unnecessary wiring can be reduced as shown in FIG. 4. In this case (a square turned 45 degrees ◇), the block terminals marked ◇ should not affect the block occupation shape.

The present invention also exhibits great effects in the master slice method. By providing symmetry in advance to the pattern that serves as the base, it is possible to select the position of the inter-block connection terminal included in the wiring (by making the turns freely changeable) and the wiring overlaid thereon.

An embodiment of the present invention will be shown below regarding a gate array that can be assembled into one product of the master slice. In a gate array, cells forming the base of blocks are arranged regularly, and a functional block can be placed anywhere in this cell area. There are an infinite number of combinations of toothbrush block arrangements, and of course the block terminals can be connected from all directions. Figure 5 shows the outer frame 4 of the three blocks A, TR, and K and the terminal positions on the frame. The F mark at the corner of the block outer frame indicates the block coordinate origin and the direction of the block pattern. FIG. 6(4) shows the symmetrical form of the cell.

This cell pattern 5 has symmetry axes in the X and Y directions, and when a block diagram is superimposed on it, four directions can be selected: f'l, F2, II'3, and F4, as shown in Figure 6 (13+). This is equivalent to having four positions for one terminal.The same goes for other blocks l and j.

As shown in FIG. 7, the wiring area 1 and the area 2 in which the cells are arranged are arranged adjacent to each other, and the block shown in FIG. Figure 7 (
6)) and the actual situation in Figure 7 (c)). The wiring consists of two nodes, and the wiring in the X direction and within the block is limited to the first node, and the Y direction is limited to the second node. Compared to FIG. 7(5), the wiring length between terminals in FIG. 7(b) is shorter, and the number of wiring channels used in the X direction in the wiring area is one less. If the required cover for the wiring channel is reduced, the wiring area can be reduced, and the wiring length can also be further shortened. It is also possible to reduce the chip area of the IC.

In the case of gate arrays, once the overall block arrangement has been determined, it is extremely difficult to change the position of some blocks. Furthermore, it is impossible to move blocks with ordinary master slice varieties in which the same underlying pattern is not arranged in a reverse pattern. Even in such a case, if the present invention is implemented, the terminal position can be changed without changing the occupied position of the block, and unnecessary wiring can be reduced.

As explained above, by implementing the present invention, it is possible to improve the wiring efficiency in an integrated circuit, reduce the signal transmission speed by reducing the wiring length, reduce the required wiring area, and reduce the chip area. be able to. Therefore, the present invention can contribute to improving the functionality of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a pattern diagram showing normal inter-block wiring. al
, a2. a3. a4. a5 is the terminal to the block, bl,
b2. b3. b4. b5 is al, a in block group B
2. a3. A terminal connected to aCa5 is shown. Figure 2 (
(f) is a pattern diagram showing an example of setting equipotential terminals within one block. FIG. 2(c) is a pattern diagram showing a wiring route between equipotentials spanning two blocks. 11 and 21.21 and 2
2. CI and c2. dl and d2 are a pair of equipotential terminals, 3 is wiring within the block between the equipotential terminals, and 4 is an outer frame of the block. t and m indicate two wiring routes between blocks C and D. Figure 3 #'i Block shapes IA and 2 for the X axis
Showing symmetrical relationships between people. FIG. 4 is a pattern diagram showing the result of implementing the present invention on the pattern of FIG. 1. Each terminal name is
Same as figure. Figure 5 shows 1. J. A pattern diagram showing the terminal positions of K3 types of blocks. 1
1. I2. I3 is the block terminal, JIJ2. I3 indicates a terminal of block J, Kl, and 2 indicate a terminal of block. FIG. 6(5) is a pattern diagram of the symmetry axes X and Y of the cell shape 5 and the outer frame 4 of the block overlapping the cell. Figure 6 (
c) The four symmetric forms Fl, F'2. F3
．． A pattern diagram showing F4. Figure 7 (5) is block I
, J, on the gate array and wiring pattern diagram. FIG. 7(b) is a pattern diagram showing the improved results obtained by implementing the present invention on FIG. 7(5). Reference numeral 6 indicates a wiring area, and 7 indicates a cell array area. The 0 mark indicates the 1-2 interlayer ■ia hole. In FIGS. 5, 6, and 7, a seal at the corner of the block outer frame 4 indicates the block coordinate origin and the direction of the block pattern. Fig. l Fig. 2A Mature 3 Close Fig. 4 J Fig. S Fig. A'/ ni 2 K Fig. 6 (A) Fig. 6 (B) Closing Fig. 7 (A)

Claims (1)

[Claims] What is claimed is: 1. An integrated circuit device characterized in that, on a single chip, occupied areas of circuit patterns having a set of functions overlap each other through symmetrical transformation.