JPS60183918A - Power source malfunction detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a power supply abnormality detection device.

If the AC input supplied to the load is temporarily reduced or cut off, or if an overvoltage occurs, there is a high possibility that the load (various electrical equipment) will malfunction. There is a power supply abnormality detection device as part of the device for preventing such malfunctions.

A simple conventional example of a power supply abnormality detection device is shown in FIG. This detects the presence or absence of AC input using an AC relay Y-in-Y, and although it has a simple configuration, it has the disadvantage that the detection time is long, 20 to 30 m5ec.

Another conventional example is the bozumono shown in FIG. Tr is an isolation transformer, D is a rectifier, R,, R2 are resistors, and C is a flat
W is a capacitor, OP is an operational amplifier, and E is a reference voltage. This is an operational amplifier 01l that rectifies and smoothes the AC input.
(Instead of this, a transistor and Zenada (;t -F-
(There are also combinations of Of course, when the rectified voltage due to AC input becomes lower than the reference voltage (, (, output °C -
Output. However, there is a drawback that a time delay occurs due to the time constant 12Xc determined by the resistor R2 and the capacitor C, and the detection time is normally 10 to 20 rns+.

An object of the present invention is to provide a power field lightning detection device with low responsiveness that can eliminate the above-mentioned conventional drawbacks and detect drop or cutoff of AC input, overvoltage, or overcurrent in a very short time. be.

The configuration of this invention will be explained based on FIG. 1 is an A/D converter coupled to AC input, 2 is a central processing unit (microprocessor: CP) in a microcomputer.
U), which includes means 3 for transmitting sampling signals at predetermined time intervals, and reference values VSI, Vs2, etc. corresponding to individual times determined at said predetermined time intervals.
A/
A means 5 for reading a data signal from the D converter 1 and a reference value νs1.
The means 6 for reading Vs2... compares the value Vll of the read data signal with the reference value VSI (J is an integer) and when V+ y SVs J (when overvoltage is detected) VsJ<VlJ.) Means 7 for outputting an input drop detection signal (this also includes cutoff detection signal)
It is equipped with

NF is a noise filter that removes external surges and high-frequency noise, and Tr is an isolation transformer connected to the output end of the noise filter NF, thereby insulating the input power source and the detection circuit. D and D are rectifiers (diodes) connected to the secondary winding of the transformer Tr, thereby performing full-wave rectification. PC is a photocoupler consisting of a light emitting diode I)D and a phototransistor PT. The output (input drop detection signal) from the photocoupler PC is transmitted to the load body. A transistor or other suitable transmission means may be used instead of the photocoupler PC. '1
゛ is an interval timer, which inputs an interrupt to the CPU 2 at every -= fixed period La.

CPU2 and Δ/D converter 1 and start signal line 8,
It is connected by an address bus 9 and a data bus 10.
A start signal and an address signal are output from the PU 2 to the A/D converter 1, and a data signal is output from the A/'D right converter 1 to the CPU 2.

FIG. 5 is an explanatory diagram of voltage comparison, and the comparison means 7 compares the digital value VIJ of the data signal and the reference value Vs.
J (J = 1.2...), and the sampling period tQ is approximately 0.5 to 1. m3(B(.

When the power supply frequency is 5011Z and L O = l m5ec, the range of phase angles from 0 to 180° is divided into 10 equal parts. A flowchart for the CPU 2 in this case is shown in FIG.

In this flowchart, the input drop detection operation is performed when Vl+≦■SJ occurs three times in a row. C every sampling period 1o by interval timer T
An interrupt is generated in PU2, which starts the program.

Send the star 1 signal to A/D converter 1 in step ①. Waiting for the completion of the conversion in step (2), the data signal is read from the /D converter 1 in step (2), and the sampling counter is incremented by 1 in step (2). Base on step ■! (ζ value ■o and data Shingetsu value V.

Compare with.

If v,<Vo, the process moves to step (2), and the sampling counter is 1.Vo. Determine whether ≧10. vl<vo
When 1≧10, it is assumed that the phase of the sine wave is 0° or 18°, and the sampling counter is set to t, =0 in step (3).

Even if the sampling counter is tl≧lo, Vl
If <Vo continues, wait until vl<vo and set the scene pulling counter to L]-Q. Until then, it will be undetectable. The counter rarely becomes LI≧10, but if it changes due to waveform disturbance etc.
Avoid this method.

If the counter does not reach tl=10 and becomes V[<Vo, as shown in the right half of FIG. 5, it is assumed that a normal voltage is not being output, and the sampling counter is left as is.

Now, if V<Vo is NO, then Vl<Vo is Y
If ES and t1≧io is No, the process moves to step (2).

In step (2), the reference value Vs of the corresponding time is read, and in step (2), both are compared as V,>V. Y
If ES, move to step [phase], where Vl>VS
It is determined whether or not this occurs three times in a row. If NO, the process ends and restarts. If YIES, the low voltage detection output is turned off in step O.

Also, if step ■ is No, move to step @V,
Check whether ≦Vs occurs three times in a row.

If NO, it will end and restart, but if YES
If so, turn off the low voltage detection output in step (■).

Further, if the result in step (2) is No, the process moves to the su-knob σ contest (2) and it is determined whether 1≦Vs occurs three times in a row. NO
If so, the process ends and restarts, but if YES, the process moves to step O and turns on the low voltage detection output.

When the power supply frequency is 5011y, the sampling period t
o is to = 1 +50-+ 2÷10=0.00
1 (sec)=1 (msec), and three NOs are detected in 2XtO=2 (msec).

If the sampling period to is made even smaller, the detection time becomes even shorter. Note that it is not necessary to limit the number of consecutive judgments in Step [Phase] 2@ to three times.

In the case of this embodiment, in addition to being able to detect an input drop or cutoff extremely quickly, the noise filter N
The presence of F can actually prevent false positive detection, and
It can be used in a wide variety of ways by changing the 1 gram input depending on the quality and frequency of the power source. In addition, by changing the program and adding a separate power supply to the output circuit of the CPU 2, it is also possible to detect overvoltage and undervoltage.

Although the embodiments have been described above, the power field lightning detection device of the present invention includes: an A/D-1 converter coupled to an AC input; means for transmitting a sampling signal at predetermined time intervals;
a table storing base IB values corresponding to individual times determined at the predetermined time intervals; means for reading data signals from the A/I converter according to the sampling gain No. 1; means for reading a reference value from the table using a sampling signal; comparing the value of the read data signal with the reference value and outputting an input abnormality detection signal when the value of the data signal is below or above the reference value; Because of this configuration, the present invention is capable of preventing input drop or overvoltage, including manual cutoff.

It is effective in being able to detect input abnormalities such as overcurrent in an extremely short time and dramatically improving responsiveness.

[Brief explanation of the drawing]

Fig. 1 is an electric circuit diagram of a conventional example, Fig. 2 is an electric circuit diagram of another conventional example, Fig. 3 is a configuration diagram of the present invention, Fig. 4 is a specific electric circuit diagram thereof, and Fig. 5 is a voltage An explanatory diagram of the comparison, FIG. 6 is a flowchart. l...A/f) converter, 3... sampling signal transmitting means, 4... table, 5... data signal reading means, 6... reference value reading means, 7... comparing means Figure 1 Figure 2 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] a Δ/D converter coupled to an AC input; means for transmitting a sampling signal at predetermined time intervals; a table storing base 71ζ values corresponding to individual times determined by the predetermined intercostal intervals; Said A/
means for inputting >k data signals from the D converter; means for reading base 41 values from the table using the sampling signals; means for outputting a manual abnormality detection signal when the signal value is below or above the reference value;
Alofe power supply abnormality detection device.