JPS61260169A - Ac signal detecting circuit - Google Patents

Ac signal detecting circuit

Info

Publication number
JPS61260169A
JPS61260169A JP10358385A JP10358385A JPS61260169A JP S61260169 A JPS61260169 A JP S61260169A JP 10358385 A JP10358385 A JP 10358385A JP 10358385 A JP10358385 A JP 10358385A JP S61260169 A JPS61260169 A JP S61260169A
Authority
JP
Japan
Prior art keywords
signal
circuit
converter
voltage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10358385A
Other languages
Japanese (ja)
Inventor
Atsuyuki Hirao
平尾 敬幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Electric Industry Co Ltd
Original Assignee
Nippon Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Industry Co Ltd filed Critical Nippon Electric Industry Co Ltd
Priority to JP10358385A priority Critical patent/JPS61260169A/en
Publication of JPS61260169A publication Critical patent/JPS61260169A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To obtain an errorless detection signal by using a single low-voltage power source as the power source and performing the operation after raising an input signal to the + side in DC. CONSTITUTION:The AC input signal issued to an input terminal 1 is inputted to a primary-side winding 4 of a transformer T through a noise eliminating filter 2 and a level setter 3, and the step-down AC signal obtained in a secondary-side winding 5 is raised to the + side by a DC voltage Vref from a reference voltage generating circuit 6 to generate a signal Vdet to be detected. The signal Vdet is sampled by the fist A/D converter 8 and is converted to a digital signal V'det, and the level of the voltage Vref is converted to a digital signal V'ref by the second A/D converter 9. Signals V'det and the signal V'ref are inputted to an operating circuit 10, and the circuit 10 operates V'det-V'ref to output the output signal to a terminal 11. Thus,the errorless accurate detection signal is obtained for the AC input signal waveform.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は主として交流出力装置(例えば定電圧電2!j
!装置)のフィードバックw4mや各種交流波形の計1
!II!i等に使用する交流信号検出回路に関するもの
である。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is mainly applicable to AC output devices (for example, constant voltage electric
! (equipment) feedback w4m and various AC waveforms total 1
! II! The present invention relates to an AC signal detection circuit used in i, etc.

(従来の技術) 従来、例えばコンビコーク。放送装備0通信装置等のN
Nはat精度と信頼性を必要とするため、一般にインバ
ータを用いた定周波定電圧WI源装置が用いられている
が、この出力を安定に維持するためには交流信号検出回
路で出力電圧を検出し、設定電圧値に近づけるようフィ
ードバック制御が行なわれている。このフィードバック
制御を行なう信号は、取出された交流出力電圧を整流回
路と平滑回路によって直流電圧に変換したものと、設定
電圧値とを比較して作っている。
(Prior art) Conventionally, for example, Combicoke. Broadcasting equipment 0 Communication equipment, etc. N
Since N requires AT precision and reliability, a constant frequency constant voltage WI source device using an inverter is generally used, but in order to maintain this output stably, the output voltage must be controlled by an AC signal detection circuit. Feedback control is performed to detect and bring the voltage close to the set voltage value. The signal for performing this feedback control is generated by comparing the extracted AC output voltage converted into a DC voltage by a rectifying circuit and a smoothing circuit with a set voltage value.

このようなところで使われる整流回路は、通常第3図に
示すようなダイオードQa−[)dを構成要素とするブ
リッジ式全波整流回路が用いられている。
The rectifier circuit used in such a place is usually a bridge type full-wave rectifier circuit including diodes Qa-[)d as shown in FIG.

ところで、整流回路出力を平滑回路に通すと時間の遅れ
が生じ、フィ−ドバックIIJ allの応答が遅れる
という問題がある。そのため、高速応答を必要とするフ
ィードバック系では、平滑回路を使わず、整流回路の出
力波形をA/Dコンバータでサンプリングし各サンプル
値をディジタル信号に変換してフィードベック情報を轡
るようにしたものが使われている。整流回路の出力をこ
のように処理する用台には、整流された出力波形そのも
のが重要な意味をもって来るので、正確な波形を出力す
る整流回路が必要である。
By the way, when the output of the rectifier circuit is passed through the smoothing circuit, a time delay occurs, and there is a problem that the response of the feedback IIJ all is delayed. Therefore, in feedback systems that require high-speed response, instead of using a smoothing circuit, the output waveform of the rectifier circuit is sampled with an A/D converter and each sample value is converted to a digital signal to read the feedback information. something is being used. For processing the output of a rectifier circuit in this way, the rectified output waveform itself has an important meaning, so a rectifier circuit that outputs an accurate waveform is required.

〔解決しようとする問題点〕[Problem to be solved]

第3図に示した整流回路においては、整流出力電圧VQ
は、ダイオード順方向降下電圧を■f。
In the rectifier circuit shown in Figure 3, the rectifier output voltage VQ
is the forward voltage drop of the diode f.

入力IFBEをvlとすルト、Vo −Vi −2Vf
 となり、ダイオード順方向降下電圧Vfが誤差となっ
て、第4図(a )に示した入力電圧v1の波形に対し
て正確な整流出力波形を得ることができず、第4図(b
)のようになってしまっていた。
If the input IFBE is vl, then Vo -Vi -2Vf
As a result, the diode forward drop voltage Vf becomes an error, making it impossible to obtain an accurate rectified output waveform for the waveform of the input voltage v1 shown in Figure 4(a).
).

ところで、制御系を構成するマイクロコンピュータやデ
ィジタル演算回路等では、通常低電圧(例えば+5V)
の皐−電源(0と+)を使用しており、交流信号検出回
路にも低電圧の単−lI源を用いた場合には、そこに含
まれる整流回路のダイオード順方向降下電圧Vr  (
例えば0.7V)によって大きな検出誤差を生じ、この
誤差の影響を無視できなくなるという問題がある。
By the way, microcomputers and digital arithmetic circuits that make up the control system usually operate at low voltages (for example, +5V).
If a low-voltage single-I power source (0 and +) is used for the AC signal detection circuit, the diode forward drop voltage Vr (
For example, 0.7 V) causes a large detection error, and there is a problem that the influence of this error cannot be ignored.

本発明は上記の問題引を解消するためになされたもので
、低電圧の単一?1!源を用いた場合に誤差のない検出
信号を得ることができる交流信号検出回路を提供するこ
とを目的とするものである。
The present invention has been made to solve the above problems. 1! It is an object of the present invention to provide an alternating current signal detection circuit that can obtain error-free detection signals when a source is used.

〔問題点を解決するための手段〕[Means for solving problems]

上記の目的を達成するために、本発明の交流信号検出回
路は、整流回路の使用を止め、第2図(a)に示した検
出する交流信号(被検出交流信号)を変圧器の一次鋼に
入力し、その二次側にステップダウンして得られた交流
信号を基準電圧生成回路からの直流電rfVr+Jで+
側に持ち上げて第2図(tl)に示すように凌検出信号
V detを作り、それをサンプリングして、A 、/
 D変換する第1のA/D変t9!器と、上記加えた直
流電圧VrefのレベルをA 、/ D変換器る第2の
A、/D変換器と、上記第1の、A/D変換器の出力信
@ V det−と上記第2のA/D変換器の出力信号
Vref−とを入力してVdet −−Vref −の
演算を行なう演算回路を用いて検出信号(交流信号レベ
ル)を得るようにした。
In order to achieve the above object, the AC signal detection circuit of the present invention stops the use of a rectifier circuit and transfers the AC signal to be detected (AC signal to be detected) shown in FIG. The AC signal obtained by stepping down to the secondary side is input to the DC current rfVr+J from the reference voltage generation circuit.
Lift it to the side to create a detection signal V det as shown in Figure 2 (tl), sample it, and obtain A , /
First A/D change t9 for D conversion! a second A/D converter that converts the level of the applied DC voltage Vref into an A/D converter; a second A/D converter that converts the level of the applied DC voltage Vref; A detection signal (alternating current signal level) is obtained using an arithmetic circuit which inputs the output signal Vref- of the A/D converter No. 2 and calculates Vdet--Vref-.

(作用) 上述したように、本発明の交流信号検出回路は、′R′
fIAとして低電圧の単−m源を用いたもので、しかも
整流回路を使用していないので、検出するために入力し
た交流信号をそのまま使うわけにはゆかず、直流的に+
側に持ち上げ(バイアスをかける)でから演算処理する
ことにより、w4差のない検出信号を得るようにしてい
る。
(Function) As described above, the AC signal detection circuit of the present invention has 'R'
Since the fIA uses a low-voltage single-m source and does not use a rectifier circuit, it is not possible to use the input AC signal as is for detection, and the DC signal is
By lifting (biasing) to the side and then performing arithmetic processing, a detection signal with no w4 difference is obtained.

〔実施例〕〔Example〕

次に本発明の*施例について図面を4!照して説明する
Next, there are 4 drawings regarding *embodiments of the present invention! I will refer to and explain.

第1図は本発明の交流信号検出回路の一実施例を示す回
路図である。図において、1は交流入力信号(被検出交
流信号)が与えられる入力端子、2は雑音除去用のフィ
ルタ、3は入力信号のレベル設定回路、4ば変圧器(T
)の−次轡榛、5は同じく二次M!線、6は変圧器(T
)の二次側に直流電圧V refを加えるための基準電
圧生成回路、7は所定の信号レベルを取り出すためのレ
ベル設定回路である。8は第1のA 、/ D変換器で
、変圧器の二次側における直流電圧vrefの重畳され
た被検出信号yaetをサンプリングしてディジタル信
号11′に変換する。9は第2のA 、/ D変換器で
、変圧器の二次側に加えた直流電圧V refのレベル
をディジタル信@yrer′に変換する。10は演算回
路で、第1のA 、/ D変換器の出力信号■det−
と第2のA 、/ D変換器の出力信号V ref’と
を入力してVdet = −Vref −の演算を行な
い検出信号を出力する。11は検出信号(演算結果のデ
ィジタル信@)を出力する出力端子である。
FIG. 1 is a circuit diagram showing an embodiment of the AC signal detection circuit of the present invention. In the figure, 1 is an input terminal to which an AC input signal (AC signal to be detected) is applied, 2 is a noise removal filter, 3 is an input signal level setting circuit, and 4 is a transformer (T
)'s - next 轡榛, 5 is also the second M! line, 6 is the transformer (T
), and 7 is a level setting circuit for extracting a predetermined signal level. 8 is a first A/D converter which samples the detected signal yaet on which the DC voltage vref on the secondary side of the transformer is superimposed and converts it into a digital signal 11'. 9 is a second A/D converter which converts the level of the DC voltage V ref applied to the secondary side of the transformer into a digital signal @yrer'. 10 is an arithmetic circuit which receives the output signal of the first A/D converter ■det-
and the output signal V ref' of the second A,/D converter are input, the calculation of Vdet = -Vref - is performed, and a detection signal is output. Reference numeral 11 denotes an output terminal that outputs a detection signal (digital signal of the calculation result).

ダイオードD1.D2は入力信号電圧・に異常が発生し
た時にA、/D変換器や演算回路を保護するために挿入
したちのである。なお、レベル゛設定回路3及び7は必
須のものではない。
Diode D1. D2 is inserted to protect the A/D converter and arithmetic circuit when an abnormality occurs in the input signal voltage. Note that the level setting circuits 3 and 7 are not essential.

〔効果〕〔effect〕

以上説明したように、本発明の交流信号検出回路は、整
流回路を用いていないので、交流入力信号(被検出交流
信号)波形に対して誤差のない正確な検出信号が得られ
る。
As explained above, since the AC signal detection circuit of the present invention does not use a rectifier circuit, it is possible to obtain an accurate detection signal with no error in the waveform of the AC input signal (AC signal to be detected).

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の交流信号検出回路の回路図である。第
2図(a)、(b)は本発明の回路の動作説明図で、(
a)は被検出交流信号、(Mは被検出信号と検出信号の
関係を示している。第3図は従来の整流回路の回路図、
第4図は従来の整流回路の波形図で(a)は入力波形、
(b)は整流出力である。 T・・・・・・変圧器、 4・・・・・・変圧器の一次g!線。 5・・・・・・変圧器の二次IJ線、 6・・・・・・基準電圧生成回路、 8・・・・・・第1のA/D変換器、 9・・・・・・第2のA 、、/ D変換器、10・・
・・・・演算回路。
FIG. 1 is a circuit diagram of an AC signal detection circuit according to the present invention. FIGS. 2(a) and 2(b) are explanatory diagrams of the operation of the circuit of the present invention.
a) shows the AC signal to be detected, (M shows the relationship between the signal to be detected and the detection signal. Fig. 3 is a circuit diagram of a conventional rectifier circuit,
Figure 4 is a waveform diagram of a conventional rectifier circuit; (a) is the input waveform;
(b) is the rectified output. T...Transformer, 4...Primary g of transformer! line. 5... Secondary IJ line of transformer, 6... Reference voltage generation circuit, 8... First A/D converter, 9... Second A/D converter, 10...
...Arithmetic circuit.

Claims (1)

【特許請求の範囲】[Claims] 1、被検出交流信号が入力される変圧器と、該変圧器の
二次側に所定の直流電圧Vrefを加える基準電圧生成
回路と、上記直流電圧Vrefを重畳して変圧器の二次
側に得られた被検出信号VdetをサンプリングしてA
/D変換する第1のA/D変換器と、上記加えた直流電
圧VrefのレベルをA/D変換する第2のA/D変換
器と、上記第1のA/D変換器の出力信号Vdet′と
上記第2のA/D変換器の出力信号Vref′とを入力
してVdet′−Vref′の演算を行ない検出信号を
出力する演算回路を備えて構成した交流信号検出回路。
1. A transformer to which the AC signal to be detected is input, a reference voltage generation circuit that applies a predetermined DC voltage Vref to the secondary side of the transformer, and a reference voltage generation circuit that applies the DC voltage Vref to the secondary side of the transformer. The obtained detected signal Vdet is sampled and A
a first A/D converter that performs /D conversion, a second A/D converter that performs A/D conversion of the level of the applied DC voltage Vref, and an output signal of the first A/D converter. An AC signal detection circuit comprising an arithmetic circuit that inputs Vdet' and the output signal Vref' of the second A/D converter, calculates Vdet'-Vref', and outputs a detection signal.
JP10358385A 1985-05-15 1985-05-15 Ac signal detecting circuit Pending JPS61260169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10358385A JPS61260169A (en) 1985-05-15 1985-05-15 Ac signal detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10358385A JPS61260169A (en) 1985-05-15 1985-05-15 Ac signal detecting circuit

Publications (1)

Publication Number Publication Date
JPS61260169A true JPS61260169A (en) 1986-11-18

Family

ID=14357798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10358385A Pending JPS61260169A (en) 1985-05-15 1985-05-15 Ac signal detecting circuit

Country Status (1)

Country Link
JP (1) JPS61260169A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09311145A (en) * 1996-05-24 1997-12-02 Hitachi Ltd Current detector
JP2018179913A (en) * 2017-04-20 2018-11-15 パナソニックIpマネジメント株式会社 Computation system and measurement system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09311145A (en) * 1996-05-24 1997-12-02 Hitachi Ltd Current detector
JP2018179913A (en) * 2017-04-20 2018-11-15 パナソニックIpマネジメント株式会社 Computation system and measurement system

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