JPS60182859A - Original reader - Google Patents

Abstract

PURPOSE:To execute sure reading especially in reading of a picture applied variable power by arranging plural line sensors while making the read position different and giving a delay to an output of a line sensor subject to preceding scanning in response to magnification. CONSTITUTION:Line sensor chips 1-4 are scanned in the direction of arrow MS, and an analog signal in response to the luminous intensity received in synchronizing with a prescribed clock pulse is outputted at an output OUT at each picture line. Since the line sensor chips 1, 3 read and scan the original in preceding over the chips 2, 4 by a prescribed line (e.g., 4 lines), the output of the line sensor chips 1, 3 is delayed over a time corresponding to the shift of read position (interval l=4 lines) and the variable power rate. Thus, the chips 1, 3 are provided with a vertical CCD register 15 for a prescribed line's share and the shift in the reading signal due to the shift between the line sensors is eliminated in case of reading of the picture applied with variable power by the delay.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an original reading device that photoelectrically reads an original image and forms an image signal.

[Prior art]

In order to photoelectrically read the shading of a document image, a 2-in-7 sensor is known in which a plurality of light-receiving elements made of amorphous silicon strips are arranged in a line across the width of the document to be read.

Now, the sky is MU4 size! 16 pixels/jl in the edge direction of the original (approximately 210mm)! I
If the same resolution is used, one line sensor with about 3SoO light receiving elements on about 500 substrates is required. However, it is difficult to form such a large number of light-receiving elements on the same substrate without missing parts and with approximately uniform sensitivity, and therefore, unless improvements are made in yield etc. is also not practical.

Therefore, it is conceivable to arrange a plurality of line sensors each consisting of about 1,000 light receiving elements in the scanning direction and read one line of image by dividing it into two-in-sensors each. When K is set in this way, the number of light receiving elements to be formed on the same substrate is not large, so the yield can be improved and the consistency that causes the above-mentioned cost problem can be solved.

However, there are invalid bits at both ends of the line sensor that cannot be used for image reading.
An unreadable area occurs only when a plurality of line sensors are arranged on one line. Therefore, it is conceivable to arrange a plurality of line sensors in a staggered manner, for example, so that the reading lines of adjacent line sensors are different.

When multiple line sensors are arranged in a staggered manner, the nine adjacent line sensors scan different document surfaces by moving relative to each other in the direction perpendicular to the scanning direction, so that when reading the document surface, the nine line sensors read the document in advance. There is a time lag between the signal from the first example line sensor that scans and the subsequent signal from the second line sensor, which corresponds to the positional deviation between adjacent line sensors. In a copying apparatus or the like that requires a high resolution such as this deviation Vi1 of 16 pixels per dragon, it is undesirable for the effect of the deviation in the gun holder to appear on the copied image. Also,
In power 2--image reading, this deviation also affected the color balance.

Also, if you want to enlarge or reduce the original image and play it back,
It is known that the relative speed between a document and a 2-in sensor involved in reading the document is changed in accordance with the magnification ratio. When reading an image at variable magnification in this way, in the configuration in which a plurality of line sensors are arranged in a staggered manner as described above, the line sensor that reads the image first reads the gun-retrieving good image line. The time it takes for the line sensor to read varies depending on the magnification ratio.

Therefore, the above-mentioned problem caused by the misalignment of the line senna becomes even more pronounced.

〔the purpose〕

The present invention has been made in view of the above points, and provides a document reading device that solves the above-mentioned problem caused by misalignment between sensors when a document is read by multiple line sensors, and achieves good image reading. The purpose is to provide, in particular,
It is an object of the present invention to provide a document reading device that performs a reliable reading operation even when reading an image at variable magnification.

〔Example〕

Embodiments to which the present invention is applied will be described in detail below with reference to the drawings.

In this embodiment, when line-scanning a document, a plurality of line sensors are arranged in a staggered manner so that the reading positions of adjacent line sensors are different, and the document is divided and read. .

Therefore, as mentioned above, KM between the line Senna! This will cause the position to be misaligned. Therefore, in order to obtain a 1-)in continuous signal from image signals divided and read by a plurality of line sensors, at least the signal output from the first row of line sensors that scans the document in advance is stored, It is read in synchronization with the (iV output) from the line output sensor in the second row following it.

FIG. 1(a) shows a nine multi-chip OOD sensor in which a plurality of line sensor chips 4 each made of amorphous silicon, etc., each having a plurality of light receiving elements lined up in a row are arranged in a staggered manner on a substrate 5. FIG. In the figure, each line sensor chip 4 scans in the direction of arrow M8 and outputs O.
An analog signal corresponding to the intensity of the received light is output to the UT for each pixel in synchronization with a predetermined clock pulse.

The line sensor chips 4 each include 1056 light receiving elements, of which 1024 are used as effective light receiving elements for reading. Therefore, the total is 1024X4=4096
A number of light-receiving elements are used for image reading, and this makes it possible to read an image of A4 size (210 mi+, x 297 mm), for example, with a resolution of 16 pixels per line in the transverse direction.

Furthermore, when actually reading a document image, this multi-chip COD sensor moves relative to the document in a direction perpendicular to the main scanning direction of the line sensor (in the direction of arrow SS).

Therefore, line sensor chips 1 and 3 are connected to a predetermined line (4 lines in this embodiment) than line sensor chips 2 and 4.
The original is read and scanned in advance.

Figure 1(b) shows adjacent line sensor chips 2 and 5.
FIG. 6 and 7 are light receiving element arrays formed on the line sensor chips 2 and 5, respectively. The shaded areas indicate invalid light receiving elements that output dummy bits that are not used for reading and are present in a predetermined number (six in this example) at both ends of the light receiving element array. The line sensor chip is designed to align the border between the ineffective light receiving element and the effective light receiving element for this reading, and at a predetermined line interval! (4 lines in this embodiment).

8 and 9V! This is a shift gate that transfers and outputs charges accumulated in each light receiving element of the light receiving element arrays 6 and 7 in parallel according to incident light. This is a Mizuko CD register that transfers charges (analog signals) outputted in parallel from the 11th and 12th light-receiving element arrays 6 and 7, respectively, in the main scanning direction and serially according to the lock. The charges transferred by the Mizuko0D register 11 are converted into voltage signals at the output section 15 and output for each pixel.

Reference numeral 14 denotes a reset gate 4 for erasing the charge converted into a voltage signal in the output section 13, which performs an erasing operation at the rear end of the transfer lock for each pixel. In addition, horizontal 00
One end (not shown) of the D register 2 is also provided with the above-mentioned output section and reset gate.

Between the 77 gate 8 of the line sensor chip 3 and the horizontal 00D register 1, there is a vertical GOD register 5 having multiple stages of OOD registers for transferring the charges output in parallel from the shift gate 8 in parallel, and a vertical 1K
77 gate 1 for transferring the charge transferred in OOD register 5 to horizontal 00D register 1 in parallel
0 is set. Also, one horizontal 00D register is directly connected to the shift gate 9 of the line sensor chip 2.

That is, the line sensor chip 5 reads the document in advance of the line sensor chip 2, and corresponds to the deviation of the reading position (interval/=4 lines) and the variable magnification, and the line sensor chip 5 reads the document for a required time. A vertical COD register 15 for a predetermined line is provided to delay the output of the chip 5.
Ru.

Note that the line sensor chip 1 shown in FIG. 1 (-) has the same structure as the line sensor chip 3, and the line centimeter chip 4 has the same structure as the line sensor chip 2, and are arranged in the same manner as in FIG.

FIG. 2 is a configuration diagram of a copying apparatus to which the multi-chip OOD sensor shown in FIG. 1 is applied. 100 is a digital image signal VIDj! (photoelectrically reading the original image). t.

This is a printer unit that records an image based on a digital image signal VIDffO indicating white/black output from the reader unit 100.

In the reader unit 100, 21 is a document;
2: A transparent document table glass that supports it, 23, a document table cover, 24, an illumination rung that exposes the document, 25: a reflector to efficiently apply the amount of light that illuminates the document, 26, a mirror that illuminates the document from the document. a short-focus imaging lens for introducing the light of
It's Senna. Reference numeral 28 denotes a reciprocating sensor fixing table on which a lighting 2 lamp 241, a reflecting mirror 25, a lens 26 and a multi-chip OOD sensor 27 are fixedly mounted, and 29 a sensor fixing table 2.
8), a fixed base that supports the 30-wire shaft, a wire that transmits the force for reciprocating the 31Fi sensor fixed base, a roller 32 that transmits the drive of the wire 51, and a fixed base that supports the 55-wire shaft 31. A drive roller connected to the rotation drive source, a drive wire connecting the 54 #i drive source and the drive roller 35, a 55 motor as a drive source, a 36 multi-chip O
This is a cable that guides the output from the OD sensor 27. 37
is a control processing unit that controls the output of the multi-chip OOD sensor 27 and the operation of the lighting 2 lamp 24 and motor 35. The forward limit 8w is operated by the Sad sensor fixing base 28K. 39 is a home position sensor of the sensor fixing base 28. This is an operation panel for 40 operators to issue copy commands, etc.

The operation of the reader unit will be explained. First, the operation panel 40
When a copy command is input from the control processing unit 57, a signal instructing to turn on the illumination lamp 24 is sent, and only the illumination lamp 24 is turned on. Next, the motor 25 is rotated forward. As a result, the sensor fixing base 28 starts moving in the direction of the arrow. Accordingly, the original 21 is read and scanned line by line by the multi-chip COD sensor 27, which is moved in the sub-scanning direction, thereby converting it into an m-signal. When the fixed base 28 has reached the end point of forward movement, the forward limiter (fiW38) is operated, thereby the motor 35 is reversed and the fixed base 28 starts to move forward. When the home position station 29 is operated, the motors 55 and 8 are stopped, and the senna fixing base 2# is stopped at the home position.

Further, when variable-magnification reading is performed, the reading cycle for every 12 images is kept constant, and the moving speed of the senna fixing table 2B in the sub-scanning direction (true direction) is changed in accordance with the variable magnification. For example, when the magnification ratio is 0.5 times, the sub-scanning speed is set to twice the normal magnification, and when the magnification ratio is 2x, the sub-scanning speed is set to H when the magnification is the same. This change in moving speed can be achieved by changing the rotational speed of the motor 55, or by keeping the rotational speed of the motor 55 constant and providing a variable speed gear.

When the multi-chip OOD sensor 27 moves forward in the #SiA direction, that is, in the sub-scanning direction, the line sensor chip 1
Chips 2 and 3 are also reading the image of the preceding main scanning line of the document. This is shown in the timing chart in Figure 3 and the multi-chip OO in Figure IS4.
This is explained using the configuration diagram of the D sensor.

In FIG. 4, parts with the same numbers as those in FIG. 1 (1)) have the same functions. 41 is an analog switch for selecting the outputs of the four line sensor chips 4 according to data select signals DBj to DB4 and outputting them as output signals OBT, and horizontal 00D registers 11.41 for each of the four line sensor chips 4 from φH1 to 4. 12 horizontal transfer lock for transfer operation, φV11 to 17. φv'51～
φ757 #i Vertical transfer lock for transferring vertical 00D registers 15 of line centimeter chips 1 and 3, R81 to 4, reset signal of reset gate 14 of each line sensor chip, 111Hj, f3HI
B, BH2, BH5A.

8I (3B and 8H) is a shift signal for shifting gates 8, 9, and 10 of each of the 4 line sensor chips; 081 to os is an output signal from each of the 4 line sensor chips.

As shown in the figure, line sensor chips 1 and 5, that is, line sensor chips that read originals in advance, each have a vertical COD register 15 for 7 lines between shift gates 8 and 10.
is provided.

The pulse signals in FIG. 5 are shift pulses SHI A and 8HI B that drive the shift gates 8 and 10 in the line sensor chip 1 and output parallel images.
and the relationship between the four vertical transfer wheels φV11 to φV17.

Now, in the multi-chip OOD sensor used in this embodiment, as shown in A, in which a plurality of line sensor chips are arranged in a staggered manner with a spatial distance of four lines, a leading line sensor chip and a trailing line sensor chip are used. Output signals of images of the same line read at different times must be output serially. For this purpose, in order to delay the output of the reading signal of the preceding line sensor chip by a predetermined amount,
Provide a D register. Here, in order to enable variable magnification reading of the image, it is necessary to set the number of 00D registration stages (line a) constituting the vertical 00D register 15 in consideration of the variable magnification. For example, in the case of magnification with a variable magnification of 1.5 times, the sub-scanning speed of the reading section (sensor fixing table 28) is increased by %. Therefore, a scanning time difference of seven lines occurs before the line sensor chip 2 scans the first line scanned by the line sensor chip 1. Therefore, in order to enable enlarged reading with a maximum magnification ratio of 1.5 times, a seven-line vertical 00D register is required. That is, the number of stages of vertical oon registers must be at least the number expressed by the first-order equation. (Required magnification ratio) ÷ (1/(difference between line sensors 11)) line.

Therefore, in this example, the necessary magnification ratio is 1.5 times, and the amount of deviation between the line sensors is 4 lines, so it is 1.5% (3A)"7
Therefore, at least seven stages of vertical 00D registers are required. Next, considering a magnification ratio of 1.25x, in this case, the scanning speed of the reading section is multiplied by %, and line sensor chips 2 and 1 read the same line with a difference in scanning time of 6 lines. . For this purpose, the vertical shift clock signal φV
11 to 17 are controlled independently as shown in FIG. 3(1)), and the read signal of the first line is transferred to the vertical 00D register of the seventh line before the scanning of the sixth line is started. Then, the ytt signal of the first line is transferred to the horizontal OGD register 11 by the second 77t signal 811B of the line sensor 1 synchronized with the shift signal 5I (2) to the line sensor chip 2. output O
At the same timing as 82, it is possible to obtain the output 081 of the line sensor chip 2 with a scanning time difference of 6 lines. I can do that.

Similarly, when the magnification ratio is 1x or 0.75x, the vertical shift clock signals φV11 to φV17 can be controlled independently to shift the shift registers configuring the vertical 00D register 15. , by delaying the output of the line sensor chip 2 by the scanning time shift, the output signals O8I, Of of the line sensor chips 1 and 2 are
? 2 are synchronized and output as a read signal of the same line.

Note that the output signal 081 of the line sensor chip 1 is within the K interval of one line scanning interval (SH interval) (however, in the case of a contact type line sensor with 4 chips, in the case of n chips, the 1/n interval). The horizontal transfer lock φH1 is controlled so that all pixels are transferred from the Mizuko CD register 11. , Also, after the output of line sensor chip 1 is completed, line sensor chips 2 to 4 are similarly horizontally transferred and locked φH2 to φH4.
This causes the v blowing output to operate. Then, the read signals of all the chips 4 are sequentially transferred with their phases changed within one line scanning section. Specifically, when the transfer of chip 1 is completed, the analog switch 41 is operated sequentially to turn off the switch for that line and turn on the switch to select the transfer output of the first chip 2. The QBTK is configured to output a signal for one line of 91 lines. Switching of the analog switch 41 is performed according to data select signals DB1 to DB4, which will be described later.

On the other hand, the printer 200 is an electrophotographic laser beam printer that uses laser light to record an image based on the digital image signal VIDEO from the reader 100.

In the printer 200, the radar unit receives the go from the signal V from the 51-digit reader 100 and outputs a modulated laser beam. 52 A scanner unit for scanning the radar light, 551-4 A BD (551-4) that receives the laser light and outputs a BD double signal for horizontal synchronization of image recording etc.
54 is a photoconductor drum rotated at a constant speed in the direction of the arrow; 55 is a charger that charges the photoconductor drum; 56 is a high-voltage unit that supplies voltage to the charger 55, etc.; 57 is a cassette; Copy paper stored in 5
8 is a paper feed roller that rotates to feed the copy paper; 59 is a registration roller that synchronizes the leading edge of the copy paper with the leading edge of the latent image formed on the photoreceptor drum by irradiation with laser light; 60 is a developing device that converts the latent image into a visible image by attaching toner to it; 61 is a transfer device that transfers the visible image onto a copy paper sent to a predetermined tying ring by a registration roller;
These are a fixing device that fuses the toner on the 62-page copy paper, a cleaner that removes unnecessary toner on the photoreceptor drum 54 after the 65-page transfer is completed, and a static elimination lamp that removes the potential on the surface of the 64-page photoreceptor drum.

Let me explain the operation The photoreceptor 54 is charged with a uniform surface potential using a charge a55.

JfO is output from the signal V from the reader section 100 to the radar unit 51 as a modulation signal of laser light. The radar unit 51 emits a laser beam modulated from this V according to the ff1O signal, and this radar beam is deflected and scanned by the scanner unit 52 perpendicular to the drum rotation direction. The latent image thus formed on the photosensitive drum is visualized by the developing device 60. On the other hand, the toner on the drum is transferred by the action of the transfer device 61 to the copy paper that is synchronously conveyed by the transfer row 259, and the toner image is then fixed to the transfer paper by the fixing device 62, and the toner image is fixed to the copy paper by the fixing device 62. is discharged.

Here, a concrete block diagram is shown in FIG.

Further, the output image timing is shown in FIG.

70a and 701) in Figure 5 are analog switches for switching the output OS1 of chip 1, 70c and 70dQ are analog switches for switching the output OS2 of chip 2, 70e and 7of are chip 3, and 70g and 70h.
indicates each analog switch of chip 4. (The part surrounded by the dotted line corresponds to the analog switch 41 in FIG. 4.) 71 is a sample halt circuit for making the output time of the output signal constant.

72 is an amplifier for increasing the signal; a ψ converter for converting the 75-digit analog signal into a digital signal of predetermined bits; and 2, which compares the 74-digit digital signal with a threshold value and indicates white/black.
A comparator for forming a value signal, 75 is a dither ROM that outputs digital data stored in advance to the comparator 74 as a threshold value according to an address, 76 is a dither ROM
Dither counters 77 and 7 that determine the output address of
8 is a RAM for alternately storing the bit data obtained by comparing the image data with the number 11fi of the dither ROM in the comparator 74, and a RAM for storing the output of the 91Fi comparator 74
When writing to 77 and Vi7B, the clock V10 is synchronized with the address signal applied to RAh177.7B.
A latch circuit for transmitting the output of the comparator 74 to RAM 77 or 78 according to LK, 79 a selector that supplies read and write addresses to RAM 77, and 80 a read and write address to RAM 3B. The synchronous control circuit 8 synchronizes with the BD double signal, which is a synchronizing signal for each line coming from the selector and the 81-digit printer 200.
5 to 2BD section, an inverter that inverts the signal that is output alternately every section, 82 an oscillator for matching the signal output to the characteristics (recording speed) of the printer 200, 85 an oscillation clock φP from the printer oscillator 82 A read counter 92 counts n-0LK from the controller 90 (in this example, the frequency of the clock n-OLK is twice the operating frequency φ of the binary circuit in the previous stage), and this clock signal n -OLK as variable magnification signal 5j
In this embodiment, the frequency changing circuit outputs a clock signal WOLK having a changed frequency. 84 write counters that receive and count the clock VIOLE input from the frequency change circuit 92; 85 is a RAM 57;
．． This is a synchronous control circuit for controlling read/write of 38.

87 Ritter oscillator that outputs a clock pulse φ that determines the transfer of the read output of the 86-digit multichip COD sensor;
A BD synchronization circuit synchronizes the BD double signal from the oscillator 86 for the reader and the printer 200 and generates a BH pulse to the multi-chip CCD sensor, the odd-numbered T-tube of 88FioOD, that is, the line sensor chip 1 which performs a reading operation in advance, and Vertical transfer locks φV11 to 17.3 for shifting vertical 00D registers 15. This is a φV generator that generates φv51 to φv37 as shown in FIG. 3 in accordance with the variable magnification signal sg.

Figure 7 shows vertical transfer of 2-inch sensor chip 1 with four φ7
11 to φV17 are shown. Further, FIG. 8 shows an operation timing chart of the φV generator 88. Note that the vertical transfer ledges φVll to φVS7 for the line sensor chip 3 are also formed in the same manner.

The φV generator 88 receives the clock φ from the reader oscillator 86.
a 12-bit counter 121 for counting, an AND-OR logic circuit 122, and four circuits.

A 5-stage bus buffer circuit consisting of 123 to 126 colors. The 12-bit power counter 121 outputs the next 8M from the output of the '9BH pulse by the AND/OR logic circuit 122.
As shown in FIG. 8, pulses Q, 1. Output Q2. In this embodiment, the pulse Q1 is 1H at 3800 clocks for 1H time.
At the 250th clock, the pulse Q is outputted at the 2nd 2500th clock, so the AND-OR logic circuit 1 is
22d1 The address (count output) of the 12-bit counter 121 is decoded and the pulse Q1. It outputs Q2.

In this way, the output pulses Ql, Q2 and the signal S
H is four 3-state buffers 12'5 as shown in Figure 7.
~126 is input. 6 state buffer 125~1
It is selected by the signal si input to the output control G corresponding to the magnification ratio set by the operator, that is, when the magnification ratio is 1.5 times, the signal S jl is selected.
t (X 1.5 ) becomes low level and 125 5-step buffers are selected. Also, 1.25 times the time 3
The state buffer 124, the Fi5 state buffer 125 at 1x, and the 3-state buffer 126 at 0.75x are selected, respectively. For example, the magnification ratio is 1.25
If double is selected, 3-state buffer 124 is selected. 3-state buffer 124Vi, vertical transfer lock φv11. φv12. φv15. The 8H pulse input as φV14 and φV16 is output. Also.

The vertical transfer locks φV15 and φV17 output the input pulse Q1. This forms a vertical transfer lock φV11→V17 as shown in FIG. 3(b).

89 is a counter that counts according to the oscillation signal φ and 8H pulse of the reader Gekko 4-axis unit 86; 90 is a counter that counts 8H according to the count value of the counter 89 according to the reader oscillator 86;
During the signal period, the horizontal transfer locks φH1 to φH4 for causing all line sensor chips to perform transfer operations, the clock OLK synchronized with this clock φH1→H4, the aforementioned clock n-0LK, and the off 4% of the analog switch 41 (
This is a rounding controller that generates lDI31 to DS4.

To explain the operation of FIG. 5, the oscillation signal φ from the league oscillator 86 and the BD double signal from the printer 200 are synchronized by the BD synchronization circuit 47, and the waveform-shaped BD double signal SH pulse is output to the BE terminal of each chip. Enter. In this way, the stain is transferred in parallel to the light receiving elements of each of the two-in sensor chips 1 to 4, and in the line sensor chips 1 and 3, charge is transferred from the final stage of the vertical 00D register 15 to the horizontal COD register 11. It will be done.

Here, in the odd-numbered chips, that is, the line sensor chips 1 and 3 that read the document in advance, the charges transferred from the light receiving array 6 are transferred in the vertical 00D register 15 by vertical transfer locks φVN~17 and φv51~37. . As mentioned above, when the delay is determined by the positional deviation of the adjacent line senna openings due to the staggered arrangement and the magnification ratio, the delay for the spatially different pixels of the first row is performed using the 00D register 15, and then the adjacent It is output in synchronization with the line output of even-numbered chips and in synchronization with the -BD signal. At this time, the charges stored in the horizontal 00D register 10 of the chip 1 are transferred during K of the Bli interval (1 line scanning interval) by the horizontal transfer pulse φH1 controlled by the controller 90 as shown in the timing chart of FIG. All pixels are transferred. Furthermore, it can be seen that the horizontal transfer pulse φH2 is outputted to the adjacent chip 2 after the above-described horizontal transfer pulse φH1 ends. Horizontal transfer pulses φH3 and φH4 are similarly given to chips 3 and 4, and in this way, the pixels of all chips of the multi-chip OOD sensor sequentially transfer output for one line to the analog switch 41 within the 8H interval. I know it will happen.

By the way, if the analog switch 41 is used to switch the outputs of a plurality of line sensor chips in this way, a delay in switching time will occur.

However, as mentioned above, since there is one stroke other than the effective pixel before and after the output of each line sensor step, it is possible to configure the analog switch 41 to respond at this time. Able to deal with response delays. or,
This dummy pixel is removed using the method explained later)
except. In addition, it is okay to use a switch that can operate at high speed.F! Needless to say.

Now, if you do this, the output 08 of the analog switch 41
Pixel data is output at an analog level with a waveform similar to the timing chart shown in the figure.The sample and hold circuit 71 samples and holds this data, and the amplifier 72 converts it to the standard of the A/D converter 75. After correcting the signal value to match the value, convert the analog value to a predetermined bit (
For example, a 6-bit 64th floor g1) digital signal is used.

A read address is output from the dither counter 76 to the dither ROM 75 to perform dither processing in order to convert this into dot data representing black and white with halftones taken into consideration and output to the printer 200.

At this time, the controller 90 removes the transfer lock for one dummy pixel and outputs the running clock OL to the dither counter 76.
K is applied. Therefore, dither RO in the dummy pixel area
The address of M is interrupted L, and the address is restarted when the next valid pixel is input, so line sensor chips 1, 2, 2, 3, and 5
Since the dither matrix is discontinuous at the joint between and 4, defective images such as streaks do not appear in the reproduced image.

The dot data obtained by comparing the output value of the dither ROM 75 with the image signal is synchronized by the latch circuit 91 and stored in one of the line memory RAMs 77 and 78. At this time, first the line memory RAM 77
is selected to be in a writable state when the wg terminal of the synchronization control circuit 85 becomes low. At that time selector 79
The write address bus from shift counter B4 is selected. For this reason, the output of the write counter 84 is R.
It will be input to the address line of AM77. When the write counter 84 and the aforementioned dither counter 7
6, the dummy picture cumulative transfer lock from the controller 90 is removed and nine and four passes are counted, so the dial
- + Address corresponding to i search is not output and RAM
Bit data of one pixel is not stored in 77.

Also, when the synchronous control circuit 85 makes the wi terminal high, the RAM
Since the write terminal wg of 77 goes low and the chip select aS goes low, flAM 77 is selected to be readable. At this time, the selector 79 selects the read address bus from the read counter 83. As a result, the data of the previous line stored in the fi RAM 77 is read out, one dummy pixel is removed, and the data is output to the printer 200 as a continuous pixel signal Vff1o.

At the same time, a low signal is applied to the RAM 78 via the inverter 81, and the write terminal wm of the RAM 77 is set to high, so that the RAM 78 is selected to be in the 11-readable state. Therefore,
The dot data of one pixel less than the current output from the comparator 74 is stored in the RAM 7B. In this way, the RAMs 77 and 78 alternately perform writing and reading from the memories, and synchronize and output jliO from the image signal V for each line to the printer.

Next, a method of changing magnification in the main scanning direction will be described below. From the controller 90, as described above.

Clock signal φ that binarizes the optical 111-converted image signal
A clock OLK that is synchronized with the dummy pixel and eliminates the transfer stress of one dummy pixel, and a clock signal n-OLK to the frequency changing circuit 92 that is synchronized with this clock OLK.
is being output.

By converting both signals from the original into a binary image signal V, the image magnification ratio, that is, copying, is determined by the ratio of the frequency fφ of the four-way signal φ and the frequency fw of the clock signal WOIJ output from the frequency changing circuit 92. The magnification is determined. Figure wc9 shows a time chart when the magnification ratio is 1.5 times in the magnification change processing operation.

FIG. 10 is a circuit diagram showing a frequency changing circuit 92 configured using a decimal quantator. In the figure, 100 is a clock rate setting S (hereinafter referred to as DRM), and clock n −
It is composed of a decimal unit 100a for counting OLK and an AND gate circuit 100b for setting. FIG. 11 is a time chart showing the operation.

The AND gate circuit 100b has a high level signal (H).
, or a low level signal (L) is input to the respective AND gates as gate signals M, B, and 0 from the decoder 104. Decoder 104KFi magnification setting signal 8
JC is manually operated, and outputs obtained by decoding each setting signal are obtained. The combination of gate signals M, B, O, and D and the decoded output terminals QAv of the 10J counter 100a are mutually A, QB, and B.

υ clock permission signals A', B' by the signal from cla
, O' is obtained. Clock enable signals A', B',
Inverter 10 via O', D' OR circuit 101
The signal is inverted at 3 and applied to an AND circuit 1021C which performs a four-way n-OLK output gate.

Signalmen', B', and O' are the gate signals A and B, respectively.
, O are H as shown by the dotted line, and the clock rate is set by these gate signals A, B, and O. For example, if signals A and B are H and 0 is L, 0AS
An output signal (OLOOK 0UT) like ff1 is obtained, and in this case, a signal of 3 clocks is output with 8 clock counts, so the frequency t& of the output signal from the frequency change circuit 92 is the same as the original input signal. clock signal n −O
% of the frequency of LK.

Similarly, when only the signal R is H, the frequency of the output signal is 4/8-% of the clock signal frequency.When the signals B and C are H, the frequency of the output signal is 4/8-% of the clock signal frequency. Output signals of respective frequencies are taken out. That is, the gate signal A output from the decoder 104 according to the scaling factor,
Depending on the combination of B and O, it is possible to extract the frequency of the output signal according to the magnification ratio.

That is, when the magnification ratio is 1.5 times, the gate signals B and O are
% When the time is 1.25 times, gate signals A and O are set to H. When the time is equal to 1.25 times, the gate signal O is set to H, and when the time is 0.75 times, the gate signal A is set to H.
, B and H using the decoder 104, it is possible to obtain a clock output with a frequency corresponding to each magnification.

By the way, when the frequency changing circuit shown in FIG. 10 is configured as shown in FIG. 12, the input clock n is
-'A from 'Z 0 times to Vt a times' for QLK
It is possible to extract a clock whose frequency is multiplied by o. And that's four times magnification)i'AnX(5H+20+F
+4).

Here, the decimal count shown in FIG. 12 is used for continuation. The frequency changing circuit 92 is constructed by connecting decimal counters 100a, which are 4-bit counters, in multiple stages and is capable of counting from 0 to R.
If the clock signal input to G is nφ, the clock rate setting value 8 (8
≦R) is determined by the following equation.

(R+1) 8 := M (a) 00 n Here, since the setting uis#'i is an integer, the subject magnification M
(%) is set every 100n/(R+1)%, and in the case of 8:R+1, the maximum magnification is M multiplied by f(K), and the value is 1oon.

Next, an example will be explained in which the maximum copying magnification is set to 200- and the copying magnification M is set for each image.

Since the maximum magnification is 200 cm, n; 2, that is, the clock signal manually input to the frequency changing circuit 92 changes the image signal by 2.
Since the frequency is set twice as high as that of the clock signal to be converted into a value, and the copying magnification is set for each copying factor M, the maximum count value R of the counter constituting the frequency changing circuit 92 is 199.

Then, the setting value of the clock rate set for the desired copying magnification M is 8 digits, and B=M, therefore, from 0 to 19
By simply setting the desired copying magnification M as a μcrate using a 200-decimal unit that can count up to 9, magnification processing for enlargement and reduction in the main scanning direction can be realized.

FIG. 13 #:t is a circuit diagram showing a specific example of the frequency changing circuit 92 that performs the above-mentioned scaling process. In other words, 2 pieces of 4
By cascading bit DRM 200A, 200B and enable toggle 7, 70, 2 (IN), it forms a 200-decimal unit that can count from 0 to 199.

The 4-bit DRM 200A and B are shown in the circuit diagram in Figure 12 for illustration only.The clock rate setting value is as follows.
It is determined by the gate signals input from θa to Sl, and its specific gravity is as shown in the following table.

By the combination of these gate signals S1 to +3a, 0
It becomes possible to set the rate from φ to 199-. In this circuit,
If you want to achieve 200chi, you can just output the input clock signal as is.
% o case d DRM 200A.

Since the signal does not pass through DRM 200A and B, a phase difference corresponding to the delay time that occurs when passing through DRM 200A and B occurs. This phase difference is
This causes a timing shift when writing image signals to the RAMs 77 and 78. Therefore, as shown in Figure 13,
By using the output signal of the cascade-connected connection terminal RO that constitutes the 200-decimal counter, by outputting one clock that corresponds to 100%, the clock rate of zoo% can be placed at the same level as the other rate. Please output without phase difference.
), the output of this one clock is controlled by the gate signal from 8j.

Note that the decimal counter used in the above example has a range from 0 to 9.
It is not limited to a counter that counts up to 10, but it operates in decimal format and returns the same output state every 10 or 4 times when the input clock signal is input. The combination is from 0 to 9i
Any counter that constitutes a counter that can be realized by

In addition, if the magnification of the image in the main scanning direction can be continuously changed from 1 to 200%, the scanning motor should be adjusted so that the magnification can be changed in the sub-scanning direction KpA by changing the scanning speed. Of course, the speed control, the number of vertical transfer 00D registers, and the output state of the vertical transfer lock φV described above are executed as necessary.

In this embodiment, the case where four line sensors are used has been explained, but it is determined by the desired resolution h8 of this number, the size of the original to be read, etc., and it is understood that any number of line sensors may be used. not.

In addition, it may be possible to implement the same method in a reading device using a so-called reduction optical system that is not a close-contact reading method.Furthermore, it is possible to use materials other than amorphous silicon as the light receiving element, such as crystalline silicon, cadmium sulfide, etc. It is also possible.

Furthermore, the arrangement of the plurality of line sensors is not limited to a staggered arrangement, and there is no limit to the number of possibilities that can be applied to an arrangement in which the reading positions are shifted by several lines.

Furthermore, the output unit may also be an inkjet printer, a thermal printer, etc. other than a laser beam printer, or may be an image file that stores image data.

In addition, in this embodiment, the output of each line sensor chip is switched by an analog switch and output as a serial one-line signal, but the output of each line sensor chip can also be output in parallel. It is possible.

Alternatively, the image may be read by fixing the multi-chip OOD sensor and moving the document onto the reading position.

Furthermore, the number of vertical 00D registers provided corresponding to the line sensor chip that performs the reading operation in advance is determined as appropriate depending on the amount of deviation between the reading positions of adjacent chips and the desired magnification ratio. However, the number of stages is not limited to seven stages as shown in the embodiment. Furthermore, an additional number of stages may be provided in consideration of the margin for consideration.

In addition, in this embodiment, a vertical 00D register for output delay is provided only for the line sensor that performs a reading operation in advance of E, but a delay means is also required for the line sensor that performs a reading operation afterward. It is also possible to provide it accordingly.

Further, in this embodiment, the variable magnification reading of the document is performed by changing the sub-scanning speed of the reading unit and the thinning rate of both signals in the main scanning direction. It is also possible to change the magnification between the front direction and the forward direction. According to this, for example, it is now possible to reproduce vertically long images or horizontally long images, and operations such as recording an image on the entire surface of the recording material regardless of the aspect ratio of the recording material in the recording section are possible. It is achievable.

〔effect〕

As explained above, according to the present invention, by exposing and reading a document with a plurality of line sensors, high-density reading can be performed OT, eliminating problems such as cost and yield rate of line sensors. In addition, when reading images at variable magnification, it is possible to effectively eliminate problems such as deviations in reading signals due to deviations between line sensors, and achieve good image reading.

[Brief explanation of drawings]

@Figure 1 (,) is a schematic diagram of the light-receiving surface of the multi-chip COD sensor, Figure 1 (b) is an enlarged view of the joint of the line sensor chip, Figure 2 is a configuration diagram of the copying device, and Figure 3 is the reader. Timing chart diagram showing operation, Figure 4 is multi-chip OO
FIG. 5 is a block diagram showing a specific example of the circuit, FIG. 6 is a timing chart showing the output status of each part, FIG. 7 is a block diagram showing an example of the configuration of the φV generator,
Figure 8 shows the Kc7 diagram. Figure 9 shows the timing chart of the magnification processing operation. Figure 10 is a block diagram showing an example of the configuration of the frequency changing circuit. Figure 11 shows the frequency changing circuit shown in the 10th diagram. Fig. 12 is a block diagram showing another example of the configuration of the frequency changing circuit, and Fig. 13 is a block diagram showing still another example of the configuration of the frequency changing circuit. , 6 and 7 light receiving element rows, 8 and 9 shift gates, 10 and 11 are horizontal 00D registers, 146
- is a vertical 00D register, 8 B φV generator, 92 is a frequency change circuit, 121 digit 12-bit counter, 123 digit 3-state buffer, 100 digit clock rate setting section,
This is a 104 decoder. Applicant Canon Co., Ltd.

Claims (1)

[Claims] (1) A line sensor consisting of a plurality of light receiving elements is
The document reading device Kj arranged in the scanning direction arranges the plurality of line sensors at different reading positions, and also adjusts the output of the line sensor that scans the document in advance according to the magnification ratio related to document reading. A document reading device characterized in that a document reading device has a delay. (2. In claim (1), there are multiple stages of storage units that store the output of the line sensor that scans in advance, and the transfer operation of the multiple stages of storage units is different depending on the magnification ratio. (3) In claim (1), the document reading device is characterized in that the relative moving speed between the plurality of line sensors and the document is changed according to a magnification ratio. Original reading device 0