JPS60182209A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPS60182209A JPS60182209A JP3757484A JP3757484A JPS60182209A JP S60182209 A JPS60182209 A JP S60182209A JP 3757484 A JP3757484 A JP 3757484A JP 3757484 A JP3757484 A JP 3757484A JP S60182209 A JPS60182209 A JP S60182209A
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- Japan
- Prior art keywords
- circuit
- information
- signal
- signal level
- time constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、電話機等の端末機器における送話おるいは受
話信号レベルを入力信号レベルに拘らず一定に保つ回路
に係わシ、特に出力信号レベルを任意に可変設定できる
自動利得制御回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a circuit that maintains the level of a transmitting or receiving signal in a terminal device such as a telephone set at a constant level regardless of the input signal level, and particularly relates to a circuit that maintains a constant level of a transmitting or receiving signal in a terminal device such as a telephone, and in particular, This invention relates to an automatic gain control circuit that can arbitrarily set the level.
従来、この種の回路として、例えば第１図Ｉに示す如く
、信号レベル可変回路１の出力信号を整流回路２で喪流
してその整流レベルを差励増幅器３で直流電圧可変回路
４にて設定された直流電圧と比較し、その差電圧によシ
時定数回路５の出力レベルを制御してこの制御出力で上
記信号レベル可変回路１の利得を可変することによシ、
信号レベル可変回路１の出力信号レベルを上記直流電圧
可変回路４の設定電圧と等しくなるようにしたものがあ
る。Conventionally, as shown in FIG. 1, for example, as shown in FIG. The output level of the time constant circuit 5 is controlled by the difference voltage, and the gain of the signal level variable circuit 1 is varied by this control output.
There is one in which the output signal level of the variable signal level circuit 1 is made equal to the set voltage of the variable DC voltage circuit 4.
ところが、このような回路は、無信号時の回線雑音等の
異常増幅を抑制す今ため、時定数回路５の放電時定数を
比較的長く設定して信号レベル可変回路１の利得変化が
緩慢になるように構成している。このため、直流電圧可
変回路４のつまみを調整して信号レベル可変回路１の出
力信号レベルを可変しようとしても、信号レベル可変回
路１の動作が応答性良く追従しない欠点があった。However, in order to suppress abnormal amplification of line noise etc. when there is no signal, such a circuit sets the discharge time constant of the time constant circuit 5 to be relatively long so that the gain change of the signal level variable circuit 1 is slow. It is configured so that For this reason, even if an attempt is made to vary the output signal level of the signal level variable circuit 1 by adjusting the knob of the DC voltage variable circuit 4, there is a drawback that the operation of the signal level variable circuit 1 does not follow with good response.
そこで、従来では、例えば第１図に示す如く、ロータリ
スイッチ等を用いたリセット回路６を設け、このリセッ
ト回路６を前記直流電圧設定回路４のつまみと連動させ
て、このつまみが一定量操作される毎に前記時定数回路
５をリセットするようにしている。このようにすれば、
信号レベル可変回路１の出力信号レベルは、リセット直
後こそ最大レベルに達するが、その後時定数回路５の放
電時定数よシも短かい充電時定数に従って比較的短時間
のうちに直流電圧可変回路４で設定した値に達する。Therefore, conventionally, as shown in FIG. 1, for example, a reset circuit 6 using a rotary switch or the like is provided, and this reset circuit 6 is linked with the knob of the DC voltage setting circuit 4, so that this knob is operated by a certain amount. The time constant circuit 5 is reset each time. If you do this,
The output signal level of the variable signal level circuit 1 reaches the maximum level immediately after reset, but after that, the output signal level of the variable DC voltage circuit 4 reaches the maximum level in a relatively short time according to the charging time constant, which is shorter than the discharging time constant of the time constant circuit 5. The value set in is reached.
しかるに、上記従来の回路にあっては、直流電圧可変回
路４を調整する度毎に、１回もしくは操作液によっては
複数回時定数回路５がリセットされることになるため、
調整時に信号レベル可変回路１の出力信号レベルが大き
く変動し＋１１
て送話特定あるいは受話特性を劣化させることになシ、
極めて好ましくなかった。また、リセット回路６は機械
的接点を用いた回路であるため、接触不良等を起し易く
動作が不安定であり、これを改善するには構成が複雑化
して高価になるという欠点があった。However, in the conventional circuit described above, each time the DC voltage variable circuit 4 is adjusted, the time constant circuit 5 is reset once or multiple times depending on the operating fluid.
To prevent the output signal level of the signal level variable circuit 1 from fluctuating greatly during adjustment, the transmitting and receiving characteristics will be deteriorated.
It was extremely undesirable. In addition, since the reset circuit 6 is a circuit using mechanical contacts, it is prone to poor contact and unstable operation, and to improve this, the configuration would be complicated and expensive. .
本発明は、基準レベルの変化に応じて円滑に信号レベル
可変回路の出力信号レベルを制御することができ、かつ
構成が簡単で信頼性の高い自動利得制御回路を提供する
ことを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic gain control circuit that can smoothly control the output signal level of a signal level variable circuit according to changes in a reference level, has a simple configuration, and is highly reliable.
本発明は、上記目的を達成するために、信号レベル可変
回路への入力信号レベルの検出値および別途設定される
基準レベルをそれぞれデジタル化して中央処理部に導び
き、この中央処理部で上記デジタル化された入力信号検
出情報に所定の時定数を付与する時定数演算を行なった
のち、その算出岨と上記デジタル化された基準レベル情
報との差情報を算出し、この差情報に相当する利得制御
信号を信号発生回路で発生させてこの信号によ多信号レ
ベル可変回路の利得を制御するようにしたものである。In order to achieve the above object, the present invention digitizes the detected value of the input signal level to the signal level variable circuit and the separately set reference level, respectively, and guides the digitized values to the central processing section. After performing time constant calculation to give a predetermined time constant to the digitized input signal detection information, the difference information between the calculated value and the digitized reference level information is calculated, and the gain corresponding to this difference information is calculated. A control signal is generated by a signal generating circuit, and the gain of the multi-signal level variable circuit is controlled by this signal.
第２図は、本発明の一実施例における自動利得制御回路
のブロック構成図である。FIG. 2 is a block diagram of an automatic gain control circuit in one embodiment of the present invention.
この回路は、信号レベル可変回路１への入力信号を發流
回路２で整流してその整流出力、つ５−
まり入力信号検出レベルをψ変換器１０でデジタル化し
て制御回路２０に導ひき、かつ直流電圧可変回路４で設
定された基準電圧をい変換器３０でデジタル化して上記
制御回路２０に導入し、この制御回路２０でめられた制
御情報をＤ／Ａ変換器４０でアナログ信号に変換してこ
の信号を利得制御信号として信号レベル可変回路１に供
給し、これによシ出力伯号レベルが一定となるように信
号レベル可変回路１の利得を制御するように構成したも
のである。This circuit rectifies the input signal to the signal level variable circuit 1 in the rectifier circuit 2, digitizes the rectified output, that is, the input signal detection level in the ψ converter 10, and guides it to the control circuit 20. Then, the reference voltage set by the DC voltage variable circuit 4 is digitized by the converter 30 and introduced into the control circuit 20, and the control information determined by the control circuit 20 is converted into an analog signal by the D/A converter 40. The converted signal is supplied as a gain control signal to the signal level variable circuit 1, and thereby the gain of the signal level variable circuit 1 is controlled so that the output signal level is constant. .
制御回路２０は、例えば亀２図に示す如くマイクロプロ
セッサからなる中央制御部（ＣＰＵ ）２１と、このＣ
ＰＵ ２１の実行プログラムを記憶したリード・オンリ
ー・メモリ（ＲＯＭ ） ２２と、人力情報や演算情報
を一時記憶するためのランダム・アクセス・メモリ（Ｒ
ＡＭ ） ２３とから構成されている。そして、制御回
路２０はＣＰＵ２１にて次のような演算動作および制御
動作を行なう。その動作とは、
（１） 前記各い変換器１０．３０で変換され６−
た入力信号情報および基準値情報を一定のタイミング毎
に導入し、一時ＲＡＭ ２ Ｊに記憶する動作。The control circuit 20 includes, for example, a central control unit (CPU) 21 consisting of a microprocessor as shown in Fig.
A read-only memory (ROM) 22 that stores the execution program of the PU 21, and a random access memory (R) that temporarily stores human input information and calculation information.
AM) 23. The control circuit 20 causes the CPU 21 to perform the following arithmetic operations and control operations. The operations are as follows: (1) The input signal information and reference value information converted by each of the converters 10 and 30 are introduced at regular timings and temporarily stored in the RAM 2J.
（１）上記入力信号情報に対し、第３図のフローチャー
トに示される時定数演算を行なう動作。(1) An operation of performing time constant calculation as shown in the flowchart of FIG. 3 on the input signal information.
すなわち、ＣＰＵ ２１は、電源が供給されると同時に
内容がクリアされる第１および第２の記憶領域をＲＡＭ
２３内に設定する。そして、先ず入力信号情報を第１
の記憶領域の内容と比較し、入力信号情報が大きい場合
には第１の記憶領域の内容に一定値を加算し、一方入力
信号情報が小さい場合には第１の記憶領域の内容から一
定値を減算する。ここで、これらの加算および減算は、
上記入力信号情報の変化に対しそれぞれ第１の充電時定
数Ｌｌおよび第１の放電時定数ＬＢＩを付与するため、
入力信号情報と第１の記憶領域の内容との比較結果が所
定回数連続して変化しない場合に１回行なわれるように
なっている。例えば、第１の充電時定数ＬｌがＬｌ ＝
１６ ｍｓ＠ｅ ／ ６ ｄＢの場合には、
入力信号情報〉第１の記憶領域
なる関係が８回連続して変化しない度毎に１回ずつ加算
がなされる。同様に、第１の放電時定数ＬＢ１が
ＬＢＪ＝ ６ ｓｅｅ／６ ｄＢ
の場合には、
人力信号情報〉第１の記憶領域
なる関係が３０００回連続する毎に１回ずつ減算がなさ
れる。なお、上記第１の充電時定数ＬＡＪは、一般に回
路の電源を投入してから自動利得そうして、第１の充放
電時定数による時定数演算が終了すると、ＣＰＵ ２１
ば、次に上記第１の記憶領域の内容を第２の記憶領域の
内容と比較し、前者が大きければ第２の記憶領域の内容
に一定値を加算し、一方小さければ一定値を減算する。That is, the CPU 21 converts the first and second storage areas, whose contents are cleared as soon as power is supplied, into the RAM.
Set within 23. First, the input signal information is
When the input signal information is large, a certain value is added to the contents of the first storage area, and on the other hand, when the input signal information is small, a certain value is added from the contents of the first storage area. Subtract. Here, these additions and subtractions are
In order to assign a first charging time constant Ll and a first discharging time constant LBI to the changes in the input signal information, respectively,
The comparison is performed once when the comparison result between the input signal information and the contents of the first storage area does not change continuously for a predetermined number of times. For example, if the first charging time constant Ll is Ll =
In the case of 16 ms@e/6 dB, addition is performed once every time the relationship: input signal information>first storage area does not change eight times in a row. Similarly, when the first discharge time constant LB1 is LBJ=6 see/6 dB, subtraction is performed once every 3000 consecutive times the relationship: human signal information>first storage area. Note that the first charging time constant LAJ is generally set to an automatic gain after the circuit is powered on, and when the time constant calculation using the first charging/discharging time constant is completed, the CPU 21
For example, the contents of the first storage area are then compared with the contents of the second storage area, and if the former is larger, a certain value is added to the contents of the second storage area, whereas if the former is smaller, a certain value is subtracted from the contents of the second storage area. .
またこのときには、第２の充電時定数ＬＡ、？ （ＬＡ
、？） Ｌｌ ）および第２の放電時定数ＬＢ２ （Ｌ
Ｂ、？） ＬＢＩ ）に応じた加減算が行なわれる。こ
れら第２の充放電告時定数ＬＡ２． ＬＢ２は、例えば
ＬＡ２＝ ６ ｓｅｅ／６ ｄＢ
ＬＢ２＝ ２０ ｓｅａ／ ６ ｄＢ
に設定される。なお、上記第２の放電時定数ＬＢ２は、
通話中の音声の抑揚や短時間の途切れ等によｊ） ＡＧ
Ｃが即応しない値ならば如何なる値に設定してもよい。Also, at this time, the second charging time constant LA, ? (LA
,? ) Ll ) and the second discharge time constant LB2 (L
B.? )LBI) Additions and subtractions are performed according to LBI). These second charge/discharge notification time constants LA2. LB2 is set to, for example, LA2=6 see/6 dB LB2=20 sea/6 dB. Note that the second discharge time constant LB2 is
(j) AG due to voice inflection or short interruptions during a call, etc.
C may be set to any value as long as it does not respond immediately.
そうして第１の充放電時定数ＬＡ１． ＬＢＩおよび第
２の充放電時定数ＬＡ２． ＬＢｊによる、いわゆる２
段階の時定数演算が終了すると、ＣＰＵ２１は続いて第
１の記憶領域の内容と第２の記憶領域の内容とを比較し
、大きい方を基準値情報との演算に供する。すなわち、
記憶領域の内容Ｖムと基準値情報ＶＢとの差Ｖｃを
Ｖｃ−ＶムーＶＢ
なる演算によ請求め、Ｖｃが
Ｖｃ）０
ならば、ＶＣをこの値を利得制御情報の算出に供９−
し、一方
ｖｃ＜、Ｏ
ならばＶｃ ＝ Ｏを発する。Then, the first charge/discharge time constant LA1. LBI and second charge/discharge time constant LA2. The so-called 2 by LBj
When the time constant calculation of the step is completed, the CPU 21 subsequently compares the contents of the first storage area and the contents of the second storage area, and uses the larger one for calculation with reference value information. That is,
Calculate the difference Vc between the content Vm of the storage area and the reference value information VB by calculating Vc-VmuVB. If Vc is Vc)0, use VC to calculate the gain control information.9- However, if vc<,O, then Vc=O is generated.
そして、上記ＶＣの値に相当する利得制御情報を発生し
、この情報をＤ／Ａ変換器４０へ出力する。Then, gain control information corresponding to the value of VC is generated and this information is output to the D/A converter 40.
このような構成であるから、回路に電源が供給され、同
時に例えば発信音が到来すると、この発信音の検出信号
レベルｖＡは、制御回路２０のＣＰＵ ２１にて先ず非
常に短かい第１の充電時定数ＬＡ１が付与され、しかる
のちその時点で直流電圧可変回路４で設定されている基
準値ＶＢとｖｃ＝ ｖＡ−Ｖ。With such a configuration, when power is supplied to the circuit and, for example, a beep sound arrives at the same time, the detection signal level vA of the beep sound is determined by the CPU 21 of the control circuit 20, which first performs a very short first charge. The time constant LA1 is given, and then the reference value VB and vc = vA-V set in the DC voltage variable circuit 4 at that time.
なる減算が行なわれる。そして、この減算によシ得られ
た差出力ＶＣは、伝送路上の信号レベルに対応して利得
制御情報に変換されたのち、Ｄ／Ａ変換器４０でアナロ
グ信号に変換されて信号レベル可変回路１の制御端子に
供給される。A subtraction is performed. The difference output VC obtained by this subtraction is converted into gain control information corresponding to the signal level on the transmission path, and then converted into an analog signal by the D/A converter 40 and then converted into an analog signal by the signal level variable circuit. 1 control terminal.
この結果、信号レベル可変回路１の利得は上記利得制御
情報に対応する址だけ減衰され、これｌＯ−
によシ発信音は上記信号レベル可変回路１の利得に応じ
てレベル制御されて図示しない受話器に送られる。した
がって、発信音の受話レベルは、直流電圧可変回路４で
設定されたレベルで一定に保持される。As a result, the gain of the signal level variable circuit 1 is attenuated by an amount corresponding to the gain control information, and the level of the outgoing tone is controlled according to the gain of the signal level variable circuit 1. sent to. Therefore, the reception level of the dial tone is kept constant at the level set by the variable DC voltage circuit 4.
ところで、以上の動作において、発信音に対する信号レ
ベル可変回路１の利得の立上シ特性は、第１の充電時定
数ＬＡＪによシ規定されるため、電源投入時の回路のア
タックタイム（２０ｍｓ＠ｅ ）よシも高速（１６ｍ５
ｅｃ／６ ｄＢ ）に変化する。したがって、電源投入
後、アタックタイムを経過して回路が定常動作を開始す
るまでの間には、信号レベル可変回路１の利得は既に設
定されていることになるので、電源投入時における出力
音声のふらつき等、不安定な状態は現われない。第４図
中■は、その電源投入時における立上静特性を示すもの
で、Ｍｌは第１の記憶領域の内容の変化を、またＭ２は
第２の記憶領域の内容の変化をそれぞれ示している。By the way, in the above operation, since the rise characteristic of the gain of the signal level variable circuit 1 with respect to the beep sound is defined by the first charging time constant LAJ, the attack time of the circuit when the power is turned on (20ms@ e) Yoshimo high speed (16m5
ec/6 dB). Therefore, after the power is turned on, the gain of the signal level variable circuit 1 has already been set before the circuit starts normal operation after the attack time has elapsed. No unstable conditions such as wobbling appear. In Fig. 4, ■ indicates the start-up static characteristics when the power is turned on, Ml indicates a change in the contents of the first storage area, and M2 indicates a change in the contents of the second storage area. There is.
また上記定常状態において、何らかの理由によシ音声の
瞬断が生じると、検出信号レベルが瞬間的に低下するこ
とになるが、ＣＰＵ ２１では上記検出信号レベルの変
化に対して第１の放電１
時定数り貯が付与されるので、第１の記憶領域の内容Ｍ
１は第４図Ｏに示す如くわずかしか減少しない。このた
め、この第１の記憶領域の内容Ｍ１によシ支配される信
号レベル可変回路１の利得が大きく変化することはなく
、この結果音声の復帰時の信号レベルのふらつきは生じ
ない。Furthermore, in the above-mentioned steady state, if an instantaneous audio interruption occurs for some reason, the detection signal level will drop instantaneously, but the CPU 21 will respond to the change in the detection signal level by controlling the first discharge 1. Since a time constant storage is given, the content of the first storage area M
1 decreases only slightly as shown in FIG. Therefore, the gain of the signal level variable circuit 1, which is controlled by the content M1 of the first storage area, does not change significantly, and as a result, the signal level does not fluctuate when the audio returns.
一方、話の中断等によシ比較的長時間音声が速断えると
、その検出信号レベルの低下に伴って第４図θに示す如
く、第１の記１；！領域の内容Ｍ１は比較的短かい第１
の放電時定数ＬＢＩに従って大きく低下する。しかるに
、このとき第２の記憶領域の内容Ｍ２は、長い第２の放
電時定数ＬＢ２によシそれほど大きく低下しないため、
上記第１の記憶領域の内容Ｍ１よ）も大きくなる。した
がって、この期間では、第１の記憶領域の内容Ｍ１に代
って第２の記憶領域の内容Ｍ２が基準値情報との減算に
供され、この結果信号レベル可変回路１の利得は、上記
第２の記憶領域の内容Ｍ２と基準値情報との差に対応し
て制御される。このため、音声の復帰時に信号レベル可
変回路１が異常増幅を起すことはない。On the other hand, if the voice suddenly cuts out for a relatively long period of time due to an interruption in the conversation, etc., the detection signal level decreases, as shown in θ in FIG. The content of the area M1 is the relatively short first
It decreases greatly according to the discharge time constant LBI. However, at this time, the content M2 of the second storage area does not decrease significantly due to the long second discharge time constant LB2.
The content M1 of the first storage area also increases. Therefore, in this period, the content M2 of the second storage area is subtracted from the reference value information instead of the content M1 of the first storage area, and as a result, the gain of the signal level variable circuit 1 is The control is performed in accordance with the difference between the content M2 of the storage area No. 2 and the reference value information. Therefore, the signal level variable circuit 1 does not cause abnormal amplification when the voice returns.
さらに、通話中において音声の抑揚や短時間の途切れ等
がある場合にも、それによる検出信１
号レベルの変化は先ず第１の放電時定数り靜の付与によ
）吸収され、またこの第１の放電時定１
数ＬＩＦＢで吸収されないものについては第２の放電時
定数ＬＢ２によシ吸収される。したがって、信号レベル
可変回路１の利得が小刻みに変動して、これによシ音声
レベルが聞き離くなるといつた不具合は生じない。Furthermore, even if there is an intonation or a short interruption in the voice during a call, the resulting change in the detection signal level is first absorbed (by applying the first discharge time constant); What is not absorbed by the discharge time constant LIFB of 1 is absorbed by the second discharge time constant LB2. Therefore, the problem that the gain of the signal level variable circuit 1 fluctuates little by little and the audio level becomes unrecognizable does not occur.
さて、以上のような通話動作中に、話者が直流電圧可変
回路４のつまみを受話者声伯号レベルを増加させる方向
に操作すると、制御回路２００ＲＡＭ ２３に、それま
での基準値情報に代って上記操作による新たな基準値情
報が記憶される。そして、この新たな基準値情報は、Ｃ
ＰＵ１３−
２１にて時定数演算を終了した入力信号情報（第１およ
び第２の記憶領域の内容のうちの値の大きい方）と即時
減算される。そうしてこの減算によシ得られた差情報は
、利得制御情報に変換されたのち信号レベル可変回路１
に供給され、この結果信号レベル可変回路１の利得は即
時上記基準値に対応する値に変化する。したがって、以
後入力音声信号は上記基準値によシ定めたレベルで一定
となる。Now, when the speaker operates the knob of the DC voltage variable circuit 4 in the direction of increasing the receiver's voice level during the above-mentioned call operation, the control circuit 200RAM 23 stores information in place of the previous reference value information. New reference value information resulting from the above operation is stored. Then, this new reference value information is C
It is immediately subtracted from the input signal information (the larger value of the contents of the first and second storage areas) whose time constant calculation has been completed in the PU 13-21. Then, the difference information obtained by this subtraction is converted into gain control information, and then the signal level variable circuit 1
As a result, the gain of the signal level variable circuit 1 immediately changes to a value corresponding to the reference value. Therefore, thereafter, the input audio signal remains constant at the level determined by the reference value.
なお、第５図は、基準値ＶＢをノやラメータとしたとき
の入出力特性を示すもので、ＶＣが入力信号と基準値と
の差情報を示す。Note that FIG. 5 shows the input/output characteristics when the reference value VB is set as a parameter, and VC indicates difference information between the input signal and the reference value.
以上のように、本実施例によれは、検出入力信号レベル
をＣＰＵ ２１を有する制御回路２ｏに導入し、このＣ
ＰＵ ２１で上記検出入力信号に時定数演算を行なった
のち、その出力と基準値情報との差情報をめて、この差
情報に対応する利得制御信号によ多信号レベル可変回路
１を利得制御しているので、直流電圧可変回路４のつま
みの操作に応じて応答性良く円滑に信号レペ１４−
ル可変回路１の利得を制御することができる。As described above, according to this embodiment, the detected input signal level is introduced into the control circuit 2o having the CPU 21, and the control circuit 2o has the CPU 21.
After performing time constant calculation on the detection input signal in the PU 21, the difference information between the output and the reference value information is calculated, and the multi-signal level variable circuit 1 is gain controlled by a gain control signal corresponding to this difference information. Therefore, the gain of the variable signal rate circuit 1 can be smoothly controlled with good responsiveness in response to the operation of the knob of the variable DC voltage circuit 4.
また従来のようなロータリスイッチ機構や連動機構等を
使用した複雑なリセット回路を不要にできるので、構成
簡単にして信頼性の高い回路を提供できる利点がある。Further, since a complicated reset circuit using a conventional rotary switch mechanism, interlocking mechanism, etc. can be eliminated, there is an advantage that a highly reliable circuit can be provided with a simple configuration.
さらに本実施例によれば、検出入力信号に対し時定数を
付与する際に、長さの異なる第１および第２の時定数を
それぞれ付与し、その各出力のうち値の大きい方を基準
値情報との減算に供しているので、入力信号の立上シに
関しては高速度で応答し、かつ入力信号の中断等に対し
ては即時応答せずにそれまでの利得をある程度保持する
ことができる。Furthermore, according to this embodiment, when assigning a time constant to a detection input signal, first and second time constants having different lengths are assigned, and the larger value of each output is set as the reference value. Since it is used for subtraction with information, it can respond at high speed to the rise of the input signal, and can maintain the gain to some extent without immediately responding to interruptions of the input signal. .
したがって、立上シ応答性の向上と音声の中断による異
常増幅の防止とをどちらも無理なく確実に実現すること
ができる。Therefore, it is possible to easily and reliably achieve both improvement in start-up responsiveness and prevention of abnormal amplification due to audio interruption.
なお、本発明は上記実施例に限定されるものではない。Note that the present invention is not limited to the above embodiments.
例えば上記実施例では回線を介して到来した信号に対し
てレベル制御を行なう場合について説明したが、マイク
ロホンから入力された音声に対して適用してもよい。た
だしこの場合には、パッドの減衰量を基準値情報として
制御回路２０に供給すればよい。また、前記実施例では
整流回路２で入力信号を対数変換し、この変換した信号
Ｖムと基準値ＶＢとの差をめるようにしたが、入力１Ｍ
号を対数変換せずにＣＰＵ ２１に人力する場合には、
なる演算を行なえばよい。さらに、信号レベル可変回路
としては、利得制御情報に従って減衰量を可変制御する
ものの他に、増幅度を可変制御するものを適用してもよ
い。その他、時定数て実施できる。For example, in the above embodiment, a case has been described in which level control is performed on a signal arriving via a line, but the present invention may also be applied to audio input from a microphone. However, in this case, the amount of attenuation of the pad may be supplied to the control circuit 20 as reference value information. Further, in the above embodiment, the rectifier circuit 2 logarithmically transforms the input signal and calculates the difference between the converted signal Vm and the reference value VB.
When manually inputting the number to the CPU 21 without logarithmically converting it, the following calculation may be performed. Further, as the signal level variable circuit, in addition to one that variably controls the amount of attenuation according to the gain control information, a circuit that variably controls the amplification level may be used. In addition, it can be implemented using a time constant.
以上詳述したように本発明は、信号レベル可変回路への
入力信号レベルの検出値および別途設定される基準レベ
ルをそれぞれデジタル化して中央処理部へ導入し、この
中央処理部で上記デジタル化された入力信号検出情報に
所定の時定数を付与したのち、その出力と上記デジタル
化された基準レベル情報との差情報を算出し、この差情
報に相当する利得制御信号を信号発生回路で発生させて
この信号によシ伯号レベル可変回路の利得を制御するよ
うにしたものである。As described above in detail, the present invention digitizes the detected value of the input signal level to the signal level variable circuit and the separately set reference level, and introduces the digitized values into the central processing section. After assigning a predetermined time constant to the input signal detection information, the difference information between the output and the digitized reference level information is calculated, and a gain control signal corresponding to this difference information is generated by a signal generation circuit. The lever signal controls the gain of the variable level circuit.
したがって本発明によれば、基準レベルの変化に応じて
円滑に信号レベル可変回路の出力信号レベルを制御する
ことができ、かつ構成が簡単で信頼性の高い自動利得制
御回路を提供することができる。Therefore, according to the present invention, it is possible to provide an automatic gain control circuit that can smoothly control the output signal level of a signal level variable circuit according to changes in the reference level, and that has a simple configuration and high reliability. .
第１図は従来における自動利得制御回路のブ・・り構成
図、第２図は本発明−一実施例における自動利得制御回
路のブロック構成図、第３図は同回路における制御回路
の制御手順を示すフローチャート、第４図および第５図
は第２図に示した回路の作用説明に用いるためのもので
、第４図は時定数演算の結果を示す特性図、第５図は信
号レベル可変回路の入出力特性図である。
１７−
１・・・信号レベル可変回路、２・・・整流回路、４・
・・直流電圧可変回路、１０．３０・・・Ａ／ｌ）変換
器、２０・・・制御回路、２１・・・ＣＰＵ、２２・・
・ＲＯＭ 。
２３・・・ＲＡＭ、４（７・・・Ｄ／Ａ変換器。Fig. 1 is a block diagram of a conventional automatic gain control circuit, Fig. 2 is a block diagram of an automatic gain control circuit according to an embodiment of the present invention, and Fig. 3 is a control procedure of the control circuit in the same circuit. 4 and 5 are used to explain the operation of the circuit shown in Fig. 2. Fig. 4 is a characteristic diagram showing the results of time constant calculation, and Fig. 5 is a flowchart showing the operation of the circuit shown in Fig. 2. FIG. 3 is an input/output characteristic diagram of the circuit. 17- 1... Signal level variable circuit, 2... Rectifier circuit, 4...
... DC voltage variable circuit, 10.30... A/l) converter, 20... Control circuit, 21... CPU, 22...
・ROM. 23...RAM, 4 (7...D/A converter.
Claims (2)
、この信号レベル可変回路への入力信号の信号レベルを
検出する信号検出回路と、この信号検出回路により検出
された信号レベルをデジタル化するアナログ・デジタル
変換回路と、前記信号レベル可変回路の出力信号レベル
を設定するために発生された基準値信号をデジタル化す
るアナログ・デジタル変換回路と、これらの各アナログ
・デジタル変換回路から出力される入力信号検出情報お
よび基準値信号情報をそれぞれ入力し入力信号検出情報
の変化に所定の時定数を付与する時定数演算を行なった
のちその演算出力情報と上記基準値信号情報との差情報
を算出する制御回路と、この制御回路から出力された差
情報に相当する利得制御信号を発生しこの利得制御信号
を前記信号レベル可変回路に制御入力として供給して利
得を可変せしめる制御信号発生回路とを具備したことを
特徴とする自動利得制御回路。(1) A signal level variable circuit provided in the signal transmission path, a signal detection circuit that detects the signal level of the input signal to this signal level variable circuit, and digitization of the signal level detected by this signal detection circuit. an analog-to-digital conversion circuit for digitizing the reference value signal generated for setting the output signal level of the signal level variable circuit; After inputting the input signal detection information and the reference value signal information respectively, and performing time constant calculation to give a predetermined time constant to the change in the input signal detection information, the difference information between the calculation output information and the reference value signal information is calculated. a control circuit for calculating, and a control signal generation circuit for generating a gain control signal corresponding to the difference information output from the control circuit and supplying the gain control signal as a control input to the signal level variable circuit to vary the gain. An automatic gain control circuit characterized by comprising:
長さの異なる複数の時定数を伺与する時定数演算をそれ
ぞれ行ない、それらの演算値のうち最も太きいものを基
準値信号情報との演算に供するものである特許請求の範
囲第１項記載の自動利得制御回路。(2) The first circuit performs time constant calculations that give multiple time constants of different lengths to changes in input signal detection information, and uses the thickest of these calculated values as a reference value signal. The automatic gain control circuit according to claim 1, which is used for calculation with information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3757484A JPS60182209A (en) | 1984-02-29 | 1984-02-29 | Automatic gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3757484A JPS60182209A (en) | 1984-02-29 | 1984-02-29 | Automatic gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60182209A true JPS60182209A (en) | 1985-09-17 |
| JPH0423841B2 JPH0423841B2 (en) | 1992-04-23 |
Family
ID=12501298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3757484A Granted JPS60182209A (en) | 1984-02-29 | 1984-02-29 | Automatic gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60182209A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0261967A2 (en) * | 1986-09-25 | 1988-03-30 | Nec Corporation | Automatic electrical power control circuit |
| JPS6372208A (en) * | 1986-09-12 | 1988-04-01 | Nippon Colin Co Ltd | Signal amplification system |
| EP0369135A2 (en) * | 1988-11-17 | 1990-05-23 | Motorola, Inc. | Power amplifier for a radio frequency signal |
| JPH0529854A (en) * | 1991-07-22 | 1993-02-05 | Fujitsu General Ltd | Signal level control circuit |
| JPH05304430A (en) * | 1992-04-24 | 1993-11-16 | Orion Denki Kk | Automatic adjusting circuit of analog control part |
| JPH05343938A (en) * | 1992-06-05 | 1993-12-24 | Japan Radio Co Ltd | Powr controller in digital modulation demodulation system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5614709A (en) * | 1979-07-18 | 1981-02-13 | Shigeru Tanizawa | Agc circuit |
| JPS5660313U (en) * | 1979-10-12 | 1981-05-22 | ||
| JPS5813006A (en) * | 1981-07-16 | 1983-01-25 | Matsushita Electric Ind Co Ltd | Automatic level controller |
-
1984
- 1984-02-29 JP JP3757484A patent/JPS60182209A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5614709A (en) * | 1979-07-18 | 1981-02-13 | Shigeru Tanizawa | Agc circuit |
| JPS5660313U (en) * | 1979-10-12 | 1981-05-22 | ||
| JPS5813006A (en) * | 1981-07-16 | 1983-01-25 | Matsushita Electric Ind Co Ltd | Automatic level controller |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6372208A (en) * | 1986-09-12 | 1988-04-01 | Nippon Colin Co Ltd | Signal amplification system |
| EP0261967A2 (en) * | 1986-09-25 | 1988-03-30 | Nec Corporation | Automatic electrical power control circuit |
| US4803440A (en) * | 1986-09-25 | 1989-02-07 | Nec Corporation | Automatic electrical power control circuit |
| EP0369135A2 (en) * | 1988-11-17 | 1990-05-23 | Motorola, Inc. | Power amplifier for a radio frequency signal |
| WO1990006018A1 (en) * | 1988-11-17 | 1990-05-31 | Motorola, Inc. | Power amplifier for a radio frequency signal |
| US4992753A (en) * | 1988-11-17 | 1991-02-12 | Motorola, Inc. | Power amplifier for a radio frequency signal |
| JPH0529854A (en) * | 1991-07-22 | 1993-02-05 | Fujitsu General Ltd | Signal level control circuit |
| JPH05304430A (en) * | 1992-04-24 | 1993-11-16 | Orion Denki Kk | Automatic adjusting circuit of analog control part |
| JPH05343938A (en) * | 1992-06-05 | 1993-12-24 | Japan Radio Co Ltd | Powr controller in digital modulation demodulation system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0423841B2 (en) | 1992-04-23 |
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| EXPY | Cancellation because of completion of term |