JPS60179879A - Arithmatic circuit of histogram - Google Patents

Abstract

PURPOSE:To improve arithmetic speed by executing the operation of a histogram at the same period as a picture input period. CONSTITUTION:When a histogram arithmetic mode is specified, the added result of an adder 34 is outputted to a data line 30 through a three-state gate 39 during the setting of a table memory 26 in a write mode. If it is defined that the added results of data RB, RD, RF... to a numeral ''1'' are WB, WD, WF..., (1T)WD is outputted to a data line 30 during the 1st write mode, (1T)WT is outputted during the succeeding write mode (after 1T) to a data line 30, and hereinafter, WF... is outputted similarly. The data on the data line 30 are written in an address position in a table memory 26 which is specified by data in an address line 28. Thus, the histogram arithmetic related to data B, D, F... is executed in parallel with the histogram operation related to the data A, C, E... with the delay of a period 1T.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a histogram calculation circuit suitable for examining the distribution of pixels with respect to their gray values.

[Technical background of the invention and its problems]

Conventionally, this type of histogram calculation circuit has been constructed as shown in FIG. In FIG. 1, image data on an image path 11 is latched into a register (RIG) 12 every 2T period, as shown in the timing chart of FIG.

The outputs (A, B, C, . . . ) of the registers 12 are led to the table memory 13 via address lines 14 of the table memory 13. The table memory 13 is set to the read mode during the first half of the period 2T, and during this read mode, the outputs of the register 12 (A, B, C, . . .
・Contents of the address position specified by RA, RB, R
e... is read out to the data line 15 of the table memory 13. RA read out to the cheetah line 15.

RB, RC, . . . are led to the B input terminal of the adder 17 via a register (REG) 16, and
An addition is carried out with the numerical value ゛IM introduced at the input. Addition results WA and WB of adder 17.

WC... is led to the data line 15 via the 3-state f-)(TSG)Ilil which becomes an output enable state in the latter half of the period 2T. The table memory 13 is
The second half of the above cycle 2T is set to write mode.
During this write mode, WA, W on data line 15
B, WC... are the outputs of the register 12 (A, B, C...
) in the table memory 13 (ie, at the address where RA, RB, RC, . . . were stored).

In this way, in the conventional histogram calculation circuit, the period is 2T.
Histogram calculations were performed.

In this case, in order to enable real-time histogram calculation of image input, the period 2T needs to match the image input period (for example, 120 ns). However, if the period T is 172 of the image input period, for example 60 n
11), and real-time histogram calculation of image input could not be realized.

[Purpose of the invention]

This feature was made in view of the above circumstances, and one purpose thereof is to provide a histogram calculation circuit that can speed up histogram calculations and perform real-time processing of image input.

[Summary of the invention]

In this invention, the first and second registers are provided for latching the image data from the image path every cycle and for each other. The output data from the first and second registers are stored in the first and second registers that store intermediate data and operation results of the histogram operation.
Used as an address to atrage the table memory. Further, in the present invention, the first adder adds the data read from the first table memory and the numerical value "1", and the adder adds the data read from the second table memory and the numerical value "1#". 2 adders are provided. 1st
The addition result of the adder is supplied to the first table memory via the first dart, and the addition result of the second adder is supplied to the second table memory via the second dart. Furthermore, in the present invention, memory control means is provided.

This memory control means complementarily switches read/write modes of the first and second table memories every cycle.

[Embodiments of the invention]

FIG. 3 shows the configuration of a histogram calculation circuit according to an embodiment of the present invention. In the figure, 21 is an image path that is a transfer path for image data, 22 is a register (REG) that latches the image data on the image path 21, and 23 and 24 are registers (REG) that latch the output data from register 22.
G). 25. 26 is a table memory for storing intermediate data and calculation results of histogram calculation, 21
．． 28 is the address line of table memory 25 and 26,
Similarly, 29 and 30 are data lines. 31.32 is a register (REG) that latches the data on data lines 29 and 30, and 33 is a selector (SEL) that selects either the data on data line 29 or the numerical value "'1". . 34 is an adder that adds the output data from the register 31 and a predetermined value "'1"; 35 is an adder that adds the output data from the Fi register 32 and the selected output data from the selector 33;

36 is a system path, and 37 is a 3-state r-t (TS
G), 38, 39umW device 34.

3 outputs the addition result of 35 to data line 29.30
State Goo) (TSG). Each of these parts is
It is controlled via a system path 36 by a host device (not shown).

Next, the operation of the histogram calculation circuit shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. 4. Now, the histogram calculation mode is specified by the host device, and image data A, B, C, etc. are sent from the image input device (not shown) to the image node 21 at an image input period (for example, 120 na
) is transmitted at a period T that matches the period T. Image data A, B, C, etc. are composed of, for example, 8 pits,
Indicates the medical value of the corresponding pixel. The register 22 registers the image data A and B on the image path 21 under the control of the host device.
, C... are latched at a period T as shown in the timing chart of FIG. Output data A, B, C, . . . from the register 22 are commonly led to registers 23, 24. Register 23 latches the output data from register 22 at a period of 26. As a result, the register 23 has the following information:
For example, data A is latched first, and thereafter data C1, data E, and so on are latched sequentially every 2T (see FIG. 4). Further, the register 24 inputs the output data from the register 22 to J, T according to the latch timing of the register 23.
It is latched with a period of 2T at a delayed timing. As a result, data B is latched first in the register 24, and thereafter, data C1 data F, . . . are sequentially latched every 2T (see FIG. 4).

The output data from register 23 is sent to address line 27.
is led to the table memory 25 via. In the table memory 25, under the control of the host device, the first half IT of the data output cycle (data latch cycle) 2T of the register 23 is set to read mode, and the second half IT1-1. Set to pledge mode. However, address line 27
During the read mode, the contents of the address location in the table memory 25 specified by the data above (i.e., the output data from the register 23) are stored in the table memory 25 during the read mode.
5 to data line 29. The contents of addresses A, C, E... of the table memory 25 are RA, R.
C, RE-... (However, in the initial state, RA
, R.C.

RE... are all MO''), during the first read mode (IT) data RA is read', during the next read mode (after IT) (IT) data RC is read, and so on. Similarly, data RE... is read out. The data on the data line 29 is latched into the register 31 at a predetermined timing in the read mode. The output data from the register 31 is led to the B input terminal of the adder 34. .

The value "'1" is introduced to the A input terminal of the adder 34. The adder 34 performs addition of both data introduced to the A and B input terminals. The addition result of adder 34 is 3-state dart 3
Guided by 8. This 3-state dart 38 is executed while the table memory 25 is set to write mode (i.e.,
Only during the second half IT of the data output period 2T of the register 23), the host device is set to the output enable state, and the addition result of the adder 34 is output to the data line 29. Therefore, data RA.

WA the result of adding RC, RE... and the value "1".

When WC, WE..., WA is output to the data line 29 during the first write mode (I T ), and (
During the next write mode (after IT) (IT) WC is output, and thereafter WE... is output in the same way (see Figure 4).
. During the write mode, the data on data line 29 is
It is written to the address location in table memory 25 specified by the data on address line 27 (ie, the output data from register 23). Specifically, in the first write mode, data WA is written to address A of the table memory 25, in the next write mode, data WC is written to address C, and in the same way, data is written to address E... WE... is written. That is,
Data in the table memory 25 RA, RC, RE...
・is plowed by WA, WC, WE... with a cycle of 2T.

On the other hand, the output data from the register 24 is led to the table memory 26 via the address line 28. The table memory 26 is controlled by the post device, and the register 2
4 data output cycle (data latch cycle) 2T first half I
T (that is, the second half I of the data output period 2T of the register 23
T) is set to the read mode, and similarly, the latter 1T (ie, the first half IT of the data output period 2T of the register 23) is set to the write mode. However, address line 2
8 (i.e., output data from register 24)
The contents of that address location of the table memory 26, specified by , are read from the table memory 26 onto the data line 30 during the read mode. The contents of addresses B, D, F... of the table memory 26 are set to RB, R.
D, RF... (However, in the initial state, RB
, RD, RF, etc. are all 0''), data RB is read during the first read mode (IT), and data RD is read during the next read mode (after IT). , and so on are similarly read out.The data on the data line 30 is latched into the register 32 at a predetermined timing in the read mode.

The output data from register 32 is directed to the input of adder 350B. Selected output data from the selector 33 is input to the A input terminal of the adder 35. The selector 33 is controlled to select the numerical value "BI" from among the numerical value "1" and the data on the data line 29 in the histogram calculation mode. Therefore, in the histogram calculation mode, the data led to the A input terminal of the adder 35 is a numerical value "
11''.The adder 35 adds both data introduced to the A and B input terminals.The addition result of the adder 35 is commonly introduced to the 3-state darts 37 and 39.In the histogram calculation mode, the 3-state data Dart 37 is set to an output high impedance state by the host device. In contrast, 3-state dart 39 is set to an output high impedance state by the host device while table memory 26 is set to write mode (i.e., data output period 2 of register 24). During the second half 1T of the data output period 2T of the register 24), the output enable state is set, and while the read mode is set (that is, during the first half IT of the data output period 2T of the register 24), the output high impedance state is set. Therefore, in this example where the histogram operation mode is specified, the addition result of adder 34 is transferred to data line 30 via three-state gate 39 while table memory 26 is set to write mode.
is output to. Here, data Rn, RD.

WB and WD are the addition results of RF... and the numerical value "1".

WF..., WB is output to the data line 30 during the first write mode (IT), and (after ]T)
During the next baroque meeting mode (IT) WD is output, and thereafter WF... is output in the same manner (see FIG. 4). Data on data line 30 is written to that address location in table memory 26 specified by the data on address line 28 (ie, the output data from register 24) during the fill mode. Specifically, in the first write mode, the data WB is stored at address B of the table memory 26.
is written, data WD is written to address D in the same write mode, and the same goes to address F...
・Data WF... is written to. That is, the data RB, RD, RF, . . . in the table memory 26 changes to WB, WD, WF, . be renewed.

In this way, in this example, the bicentric data A.

Histogram calculations for B, C, D, E, F, . . . are each performed at a cycle of 2T. However, data A,
In contrast to the histogram calculations regarding data B, D, F, etc., the period IT is
Since the histogram calculations are performed in parallel with a delay of

Next, an explanation will be given of the operation when the host IT uses the contents of the table memory 25.degree. 260 to examine the distribution of image patterns for grayscale values. In this case, the host device [L specifies the addition mode for the histogram top and bottom circuits in FIG. However,
The host device sends an address to the system bus 36 for accessing the table memory 26,26. The address on the system path 36 is led to the address line 27.28 via a 3-state path (not shown), and is transferred from the address line 27.28 to the table memory 25.26.
It will be destroyed. In this case, the table memories 25, 26 are in read mode, which causes the address lines 27.
Address on 28 (i.e. address from host device)
The contents of the location specified in table memory 26.26
The data line is 29°30. In addition mode, data on data line 29 is selectively directed by selector 33 to the A input of adder 35. On the other hand, the data on the data line 30 is led to the B input terminal of the adder 35 via the register 32.

The adder 35 adds both data introduced to the A and B input terminals. This gives the total number of pixels with the same gray value. The addition result of the adder 35 is sent to the 3-state gate 37 which is set to the output enable state in the addition mode.
via the system path 36 and transferred to the host device. The host device repeats the above operation for various addresses (ie, gray values) and obtains the pixel distribution t-A for the gray values.

〔Effect of the invention〕

As described in detail above, according to the present invention, the histogram calculation can be performed at the same cycle as the image input cycle.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a conventional histogram calculation circuit, FIG. 2 is a timing chart for explaining the operation of the histogram enhancement circuit shown in FIG. 1, and FIG. 3 is a histogram calculation according to an embodiment of the present invention. FIG. 4 is a circuit configuration diagram of the circuit, and is a timing chart for explaining the operation of the histogram calculation circuit of FIG. 3. 21... Image path, 22-24.31.32... Register (REG), 25.26... Table memory,
34.35... Adder, 37-39... 3 stages
To Dart (TSG). Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 1 Figure 4

Claims (1)

[Claims] First and second registers that alternately latch image data from the image path every cycle, and a first table that stores intermediate data and calculation results of histogram calculations and is dressed by the output data from the second register. a second table memory that stores intermediate data and operation results of the histogram operation and is addressed by the output data from the second register; and a second table memory that stores the intermediate data and operation results of the histogram operation, and the data read from the first table memory and the numerical value "1". a first adder that performs the addition of ``'1'' and a second adder that adds the data read from the second table memory and the numerical value "'1".
an adder; a first ff-) for supplying the addition result of the first adder to the first table memory; a second date supplying the addition result of the second adder to the second table memory; A histogram calculation circuit comprising memory control means for switching read/write modes of the first and second table memories every cycle and in a complementary manner.