JPS6017931A - Basic cell in master slice system - Google Patents

Abstract

PURPOSE:To eliminate an excess transistor by forming the a shape of a unit cell to be freely elongated laterally and longitudinally, thereby readily constructing a circuit such as an RAM or the like. CONSTITUTION:Two normal type basic cells BC, BC' are aligned in the gate length direction of the transistor interposed therein, four p-channel transistors QP5-QP8 having gate length are added in combination by two in a direction perpendicular to the gate length direction of the transistor interposed in the cell at one side of the gate width direction of the transistor interposed therein, and four n-channel transistors QN5-QN8 are similarly added in combination by two at the other side. Since the transistors QP6, QP8 and the transistors QN6, QN8 respecitively have common gates, 2-bit content can be obtained in case of constructing an RAM, and excess transistor is not produced. In case of constructing a unit cell, the cell can be freely elongated laterally and longitudinally.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement of a basic cell for configuring a large scale integrated circuit device (LSI) manufactured by applying a mask slicing method.

Conventional technology and problems In the mask slicing method, a gate array is created in advance in which a large number of basic cells consisting of multiple transistors and resistors are formed in one semiconductor chip, and wiring masks are created according to the required product. Then, using the wiring mask, processing is performed to connect between the transistors and resistors, and t and sr that perform the desired operation are completed.

Figure 1: [This is a plan view of the main part showing a general LSI pattern formed by applying the master slice method.

As can be seen from the figure, there is a bad PD area and a bulk pattern area for the input/output (Ilo) cell IOC at the periphery of the chip, and basic cells are formed by vertically connecting them inside. Basic cell row BLI, BT-2...
BT, , n are arranged at intervals. Note that the area between the basic cell columns becomes a wiring area.

FIG. 2 is an equivalent circuit diagram of essential parts of basic cells constituting the basic cell array.

In the figure, QPI and QP2 represent n-channel transistors, and QNI and QN2 represent n-channel L-transistors, respectively.

FIG. 3 is a plan view of essential parts showing a so-called bulk pattern that embodies the circuit configuration of the basic cell shown in FIG. 2, and the same parts as those explained in connection with FIG. .

In the figure, 1 is a p-type impurity diffusion region, 2C is an on-type impurity diffusion region, 3G1 and 3G2 are polycrystalline silicon electrodes, 4CN is an n-type substrate contact pattern, 4
CP indicates a p-type substrate contact pattern, respectively. The p-type impurity diffusion region 1 constitutes the source region or drain region of the n-channel transistors Q'PI and QP2, and the n-type impurity diffusion region 2 constitutes the n-channel transistors QNI and QN2.
Source region: J constitutes the drain region.

Here, in this specification 1, the basic cell explained with reference to FIGS. 2 and 3 is defined as "1 normal type basic cell".

Now, in order to configure a circuit using the normal type basic cells explained above, as shown in FIG.
In LI or BL2, the necessary number of basic cells BC arranged vertically are used to form a small-scale circuit called a Uniso I-cell, such as a two-man NAND circuit UCI, a two-man NAND circuit, and a two-man NAND circuit UCI.
R circuit UC2, flip-flop times 1? & U C3
etc., and connect them by forming two layers of aluminum (A#) wiring in the wiring area between the basic cell rows BLi and BLZ.

Generally, when forming an A/wiring in a wiring area existing between basic cell rows, the 1Nth A7! wiring is placed in the longitudinal direction (bf input direction) of the basic cell rows, and the A7! (in the lateral direction), the second layer Al wiring is formed respectively, and if the wiring is bent, contact between the first layer Al wiring and the second layer /l wiring is made. Use the hall.

The wiring formed using the first layer Al wiring and the second N-th Al wiring is arranged on a virtual lattice divided at regular intervals. To explain the configuration of the wiring, refer to FIG. 4 again.

That is, LA is the 1Nth Al wiring, and LB is the A of the 2nd layer.
A double circle (◎) is shown in the contact area between the L wiring, the NB, the second layer Al wiring, and the first layer AA wiring LA.

In the figure, grid-like lines can be seen between the basic cell rows B L 1 and BLZ. However, this is a virtual thing,
It doesn't actually exist. If we consider that there are 9 virtual grid lines in the vertical direction, the first layer is A7! Wiring 1
-A means that nine channels can be formed, and in that case, it is said that there are nine channels between the basic cell rows. Note that this also applies to the lateral direction.

By the way, when using the conventional technology as described above, the wiring formed in the wiring area between the basic cell columns becomes an obstacle.
It is difficult to extend the unit cell in the lateral direction, that is, to form the unit cell across a plurality of basic cell rows.

Therefore, the unit cell has no choice but to be vertically elongated, but if the unit cell could have flexibility in size not only in the vertical direction but also in the horizontal direction, the LSI configuration would be extremely easy. Become.

In addition, for example, RAM (ran
When configuring circuits such as dom ac, cess memory, etc., there are drawbacks such as an increase in the required number of circuits and the generation of surplus I/Ransis. For example, rnΔ
To construct M, four of the conventional basic cells described above are required, and moreover, there are 61 unused transistors.

Purpose of the Invention The present invention improves the configuration of a basic cell for configuring an LSI manufactured by applying the mask slicing method.
Unison]...The shape of the cell can be freely stretched in the vertical and horizontal directions, and it is also possible to
The purpose of this is to make it possible to easily configure the circuit, and to avoid having surplus transistors.

Structure of the Invention In the basic cell of the present invention, two cells share a source region or a drain region and are arranged so that the gate length is in the vertical direction.
N-channel consisting of 1 to transistors
2 (f
The two n-channel transistors have an n-channel transistor region consisting of two n-channel transistors.
The transistor and the n-channel transistor are individually associated with each other, and the gate 1- of the n-channel transistor is
A normal basic cell is arranged in the gate length direction of the above-mentioned internal transistor in the gate length direction of the above-mentioned internal transistor, and the normal basic cell is formed by commonly connecting the gate 1- of the n-channel transistor 1 to the transistor. Data 1 - On one side in the width direction, four n-channel transistors each having a gate length in a direction perpendicular to the gate length direction of the internal transistor of the normal basic cell are arranged in groups of 41'. and on the other side, four n-channel transistors each having a gate 4iL in a direction perpendicular to the gate 1-length direction of the internal transistor of the normal basic cell are added in groups of two. Added 4 n-channels 2IIl11 behind 1 Hellandisk and 4+ also added
l? Two of the n-channel transistors of the illumination unit share a gate.

As a result, when connecting basic cells to form a Unison cell, it is possible to expand freely not only in the vertical direction but also in the horizontal direction, giving greater freedom when manufacturing LSIs. The number increases dramatically by 1, and if the basic cell is used to configure, for example, a RAM, 2 bits can be obtained, and no redundant transistors are generated. When configuring a RAM, the channel width of the added transistor needs to be larger than the channel l1fJ of the transistor included in the same part as the conventional basic cell configuration.

Embodiment of the Invention FIG. 5 is an equivalent circuit diagram of a main part of an embodiment of the present invention.
The same parts as those explained with reference to FIGS. 4 to 4 are designated by the same numbers and symbols.

In the figure, QP3. QP4. QP5. QP6゜QP7
．． QP8 n-channel transistor, QN3. QN4
．． QN5. QN6. QN7. QN8 is an n-channel transistor, BC is a p-channel transistor QPI, Q
A conventional basic cell consisting of P2 and n-channel transistors QNI, QN2, BC'' is an n-channel transistor QP3, QP4 and an n-channel transistor Q
A normal basic cell consisting of N3 and QN4 is shown, respectively.

FIG. 6 is a plan view of a main part showing a so-called bulk pattern that embodies the circuit configuration of the basic cell shown in FIG. 5, and the same parts as those explained in connection with FIGS. It is an instruction.

In the figure, 5, 6, 7, 8.9 are p-type impurity diffusion regions; 10. II, 12, 13.14 & on-type impurity diffusion region, 15, 16.17, 18, 19° 20.21, 22
, 23 and 24 indicate polycrystalline silicon gate electrodes, respectively.

The p-type impurity diffusion region 5 is an n-channel L transistor Q.
The source or drain regions of P3 and QP4 are
type impurity diffusion region 6 is an n-channel transistor QP5
The p-type impurity diffusion region 7 is the source region or drain region of the n-channel transistor QP6, and the p-type impurity diffusion region 8 is the source region or drain region of the n-channel transistor QP7. p
The type impurity diffusion region 9 is an n-channel 1-transistor QP.
8 source regions or drain regions, respectively.

N-type impurity expansion 11<qr s>10ban n channel・1
- The n-type impurity diffusion region Jgi12 is the source region or drain region of the n-channel transistor QN6, the n-type impurity diffusion region Jgi12 is the source region or drain region of the n-channel transistor The drain region is the n-type impurity diffusion region @13, which is the n-channel transistor 1 to the transistor QN.
The n-type impurity diffusion region 14 forms the source region or drain region of the n-channel transistor QN8, respectively.

Next, the case where various circuits are constructed using the basic cell according to the embodiment of the present invention explained with reference to FIGS. 5 and 6 will be explained.

FIG. 7 is an equivalent circuit diagram of a main part when a RAM cell is configured, and will be explained with reference to FIGS. 5 and 6, and the same parts as 1 and 1 are indicated by the same symbols.

In the figure, INVI, INV2. INV3゜INV4
is an inverter, WRD is a read word line, WW is a write word line, D+l+D+2 is an input data signal, Dil and Di2 are inverted input data signals, and shoulder 1 is an inverted output data signal.

Inverters TNVI, INV2, I at this time
NV3. INV4 1ffl Regular basic cell BC and BC
'.

Figure 8 shows a bulk circuit embodying the circuit configuration shown in Figure 7.
7 is a plan view of a main part showing a pattern, and the same parts as those explained in connection with FIG. 7 are indicated by the same symbols.

In the figure, LA is the 11 wiring in the first layer (thick solid line), T and B are the Al wiring in the second layer (thick broken line), and NA is the Aβ wiring LA in the first layer and the semiconductor substrate. (white circle: Q), NB is the contact part between the second layer Aρ wiring LB and the first
Contact part with layer Aρ wiring LA (double circle: ◎)
, V[lD indicate the positive power supply level, and VSS indicates the ground power supply level, respectively.

As is clear from FIGS. 7 and 8, a 2-bit RAM is constructed by one basic cell according to the present invention, and no redundant transistors are generated.

FIG. 9 is a plan view of a main part showing a bulk pattern when basic cells according to the present invention are arranged next to each other, and the same parts as those explained with reference to FIGS. 5 to 8 are designated with the same symbols. It is.

As can be seen from the figure, when the basic cells in the present invention are adjacent to each other, there is a cell in the opposing part that is similar to the state in which the l-transistor in the conventional normal basic cell is rotated 90 degrees. Consists of two sets. However, the polycrystalline silicon gate electrodes of the n-channel transistor and the n-channel I transistor are not common.

Therefore, when looking at a wider area, as shown in FIG. 10, the normal type basic cell rows BL1 and BL2
It can be considered that there is a basic cell row in which the basic cells are rotated 90 degrees between them. In the figure, a new basic cell row is designated by BL', and the symbol UC represents a unit cell.

Therefore, when configuring a Uniso I cell, it is possible not only to select and combine basic cells arranged in the vertical direction but also to combine basic cells arranged in the horizontal direction. In other words, the unit cell frame can be enlarged not only vertically but also horizontally, and as a result, the shape of the unit cell frame can be designed freely within a considerable range, making it possible to create large-scale integrated circuits. It is extremely effective when configuring.

Effects of the Invention In the basic cell of the present invention, two conventional normal basic cells are arranged side by side in the gate length direction of the internal transistor thereof, and the gate width direction of the internal transistor of these normal basic cells is arranged side by side. On one side of the normal basic cell, 4 (solid p-channel transistors) having a gate length in a direction perpendicular to the gate length direction of the internal transistors are added in parallel to each other by 211!it. In addition, on the other side, two N-channel transistors each having a gate length in a direction perpendicular to the data length direction of the internal transistor of the 4-type basic cell are added in a silk pattern. , two of the added 4+l!+1 n-channel transistors and two of the four added n-channel 1-channel transistors have a structure in which the gates are shared respectively. Therefore, if you configure RAM, number 1
It is possible to obtain 2 pins, and in addition, the surplus transistors do not emit light, and when forming a unit cell, it is possible to stretch not only in the longitudinal direction, but also in the lateral direction. Therefore, it is extremely advantageous for manufacturing LST.

[Brief explanation of the drawing]

Fig. 1 is a plan view of the main part of the gate array, Fig. 2 is an equivalent circuit diagram of the main part of a conventional basic cell, and Fig. 3 is a plan view of the main part showing the bulk pattern of the basic cell in Fig. 2. 4-1 is a plan view of the main part showing a bulk pattern for explaining the relationship between unit cells and wiring.1. Fig. 5 is an equivalent circuit diagram of the main part showing the present invention - an embodiment, Fig. 6 is a plan view of the main part showing the hull pattern of the basic cell shown in Fig. 5, and Fig. 7 is the basic cell. FIG. 8 (J) is a circuit diagram showing a RAM configured using FIG. 10 is a plan view of the main part showing a bulk pattern for explaining the selective use of the LJ basic cell array. In the figure, PD is a pad, IOC is an input/output cell, nT-, BLI, BT-2...RLn is a basic cell column, QPI and QP2 are n-channel transistors, Q
NI and QN2 are n-channel transistors, 1 is an n-type impurity diffusion region, 2 is an n-type impurity diffusion region, 3G1 and 3G2 are polycrystalline silicon gate electrodes, 4CN is an n-type substrate contact pattern, 4CP is a p-type substrate Contact pattern, BC and BC' are normal basic cells, UC is unit cell, UC1 is two-man NAND circuit, UC2
is a 2-person NOR circuit, UC3 is a flip-flop circuit, LA is the 1Nth A7+ wiring, L B &; l: 2nd layer 2nd layer perspective β wiring, 1st layer A1 wiring and 6 semiconductor substrate. Contact part, NB is second layer Ae
Wiring LB and 11th A (contact I/portion with 2nd wiring LA, Ql)3. Q, P/I, QP5. 'QP6゜QP7. QPB number: In channel transistor, QN
3. QN/1. , QN5. QN6. QN7. QN8 is n
Channel transistors, 5, 6, 7, 8° 9 are p-type impurity regions 11, 10, 11, 12, 13.14 are n
type impurity diffusion region, 15, 16, 17.1.8, 19,
20, 2L 22, 23. 24 are polycrystalline silicon gate electrodes, INVI, TNV2. TNV3 and TNV/I are inverters, WRD is the read-to-1 line, WW is the write word line, D+1+D i2 is the input data signal, open and open is the inverted output data signal, VIllD is the positive power supply level, and VSS is the Ground power level. 7 Figure 1 Figure 2 Figure 3 - To Figure 9 Figure 10 R1'

Claims (1)

[Claims] An n-channel transistor region consisting of two n-channel L transistors arranged so that the source region or drain region is shared and the gate length is vertical. an n-channel transistor region consisting of two n-channel transistors arranged in the same direction, each of which corresponds to the two p-channel transistors and two (2) n-channel transistors separately; Two normal basic cells each having a gate of an n-channel transistor and a gate of an n-channel transistor connected in common are arranged in the gate length direction of the internal transistor, and the internal transistors of these normal basic cells are connected in common. On one side in the gate width direction of the 1111-type basic cell, there are four p-channel transistors (2) each having a gate length perpendicular to the gate length direction of the internal transistor of the 1111-type basic cell. On the other side, four n-channel transistors having a length of 1-2 are arranged in a direction perpendicular to the gate length direction of the internal transistor of the normal basic cell.
The transistors are added in pairs, and two of the four n-channel transistors added and two of the four n-channel transistors added each share a gate. A basic cell in the mask/slice method, which is characterized by the following characteristics: