JPS60178753A - Dc offset addition system - Google Patents

Abstract

PURPOSE:To eliminate the effects of temperatures by applying an DC offset with a means which converts either one of n-bit multi-value orthogonal signals into an (n+2)-bit signal corresponding to the 2<n> multi-value level having a center shifted in a digital stage. CONSTITUTION:The 3-bit inputs A-C show levels 0-7 as shown in a figure (a); while the outputs are turned into 4-bit Q1-Q4 outside a circuit. The corresponding output levels are turned into 8 levels 5-C among 4-bit 16 levels as shown by figures (b) and (c). The middle of 8 levels shown by the inputs A-C is set at ''0'' in the form of plus-minus symmetry. Thus the middle of 16 levels of outputs Q1-Q4 can also be set at ''0''. Then both middle points are set at each other and therefore the outputs Q1-Q4 are turned into 8 levels 4-B out of 16 levels. Thus no DC offset appears. In such a connection, 8 levels are assumed as 5-C in order to leave the DC component by shifting by every one level. Then a DC offset is applied. In such a way the DC offset is supplied in a digital stage, a level change of the DC offset is eliminated.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention provides two
This method is related to the DC offset addition method of the multi-value quadrature amplitude modulation communication system, which adds a DC offset to one of the two multi-value orthogonal signals to cause carrier wave leakage.The DC offset addition method allows DC offset addition without being affected by temperature. Regarding.

(b) Prior Art and Problems The multi-value quadrature amplitude modulation (hereinafter referred to as multi-value QAM) method in which a DC offset is added to one of two orthogonal signals to cause carrier wave leakage will be explained first.

FIG. 1 is a block diagram showing a conventional 64-value QAM transmission system. In the figure, 1 is a serial-to-parallel converter (hereinafter referred to as S/P), 2 is an encoder, and 3 and 4 are digital Analog converter (hereinafter referred to as D/A converter), 5.6 is a low-frequency P-wave converter, 7 is an adder, 8 is a DC offset source, 9.10 is a mixer, 11 is a π/2 phase shifter, 12 indicates a hybrid circuit.

The transmission data applied to an input stage (not shown) is
hase ) CHdoQ (Quadrature)
It is divided into two binary data consisting of CH data and S
/PL is converted into a parallel signal, divided into two series of 3 bits each, inputted to the encoder 2, and coated. The coated binary signals of 2 series of 3 bits each are sent to the D/A converter a+4. The signals are applied thereto, and digital-to-analog conversion is performed here to generate eight-valued analog signals. The outputs of the D/A converters 3 and 4 pass through low frequency transducers 5 and 6 to limit the band, and only the output of one F wave transducer 5 is energized, reaching the transducer 71C, which is then DC offset source 8 (DC offset source 8). are added to mixers 9 and 10, respectively. Mixers 9 and 10 have π/
A two-phase shifter 11 applies orthogonal carrier waves having phases different from each other by π/2 to perform modulation. The two orthogonal modulated signals are combined in a no-bridging circuit 12 to form a 64-value QAM signal and sent to the next stage.

Here, when DC offset Vdc is applied, a leakage carrier wave is generated and a carrier wave stands in the modulated signal.

FIG. 2 is a circuit diagram of a conventional DC offset adding circuit, which corresponds to the adder 7 and DC offset source 8 in FIG.
In the figure, 8 indicates a DC offset source, and 13 indicates a summing amplifier.

Conventionally, the addition of DC offset is done in the Bunalog section, so as shown in FIG.
A DC offset Vdc of υ is added. However, since the DC offset Vdc is added in an analog manner, the level changes depending on the temperature. That is, the summing amplifier 13
Each element has temperature characteristics, and the level of the DC offset Vdc changes depending on the temperature. If this level change causes a change in the direction in which the DC offset Vdc becomes smaller, the leakage carrier wave will become smaller, making it difficult for the receiving side to extract the leakage carrier wave and perform carrier wave regeneration. The conventional DC offset addition method has the above-mentioned drawbacks.

(cl) OBJECT OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a DC offset addition method capable of adding a stable DC offset without being affected by temperature changes.

(d) Structure of the Invention In order to achieve all of the above objects, the present invention focuses on the fact that if a DC offset is added in the digital stage, the effect of temperature change will be reduced, The present invention is characterized in that a direct current off-centro is added at the digital stage by a means for converting into an n+2 bit signal corresponding to 2n multi-levels whose centers are shifted, thereby making it less susceptible to the influence of temperature.

(e) Embodiments of the Invention Below, embodiments of the present invention will be explained according to the drawings. 6 Figure 3 shows how the input 3-bit signal of the embodiment of the present invention is converted into a 4-bit signal corresponding to an 8-level level shifted from the center. This is a circuit diagram of the converting DC offset addition circuit. In the figure, 14.20#'i AND circuit, 15.17 is an OR circuit, 16 is a NOR circuit, and 18.
22 is an inverter circuit, 19 is a NAND circuit, and 21 is an exclusive OR (hereinafter referred to as EX-OR) circuit.

FIG. 4 is a diagram showing the level relationship between the input 3 vias of the circuit of FIG. 3 and the FJ1 input 4 bits.

In the case of the present invention, the addition of a DC offset to generate a leakage carrier wave is performed between the encoder 2 and the D/A converter 3 in FIG. 1 when using ICH, for example. Therefore, a DC offset adding circuit is inserted between the encoder 2 and the D/Af converter 3, and the adder 7 and DC offset source 8 are not used.

An example of a DC offset adding circuit inserted between the encoder 2 and the D/A converter 3 is shown in FIG. FIG. 3 shows how a DC offset is added to the 3-bit input of the ICH in the case of the 64-value QAM system, where A, B, and C represent the 3-bit input, Q, and .

(b, Qs, Q- represent 4-bit output.

The 3-bit inputs A, B, and C are 0 as shown in Figure 4(a).
~7 levels, but when it passes through the circuit of Figure 3, the output becomes 4 bits Q1 to Q4, and the corresponding output level is within 16 levels of 4 bits, as shown in Figures 4(b) and (c). 8
Level 5 to C.

If we assume that the middle of the 8 levels represented by 3-bit inputs A, B, and C is 0, and consider that they are symmetrical, then the 4-bit output Q is
The middle of the 16 levels indicated by 1 to Q4 can also be considered to be 0. If you match the middle of both, you will get a 4-bit output Q.
, ~Q4 u 8 levels of 4~B within 16 levels, but no DC offset appears in this case. Therefore, the third
In the circuit shown in the figure, the Lebel shift 8 level is set to 5 to C and a DC offset is added so as to leave a DC component.

The fifth example also used a full adder and did the same thing as above.
This is shown in the figure.

FIG. 5 is a block diagram of a DC offset adding circuit using a full adder that converts 3-bit input into a 4-bit signal corresponding to 8-value levels shifted from the center according to another embodiment of the present invention. 23 in the middle shows a full adder.

The full adder 23 is a 4-bit full adder, and the lower 3 bits of one input are the 3-bit A of ICH.

Input B, (J, ground the most significant bit, and apply 01014 from the most significant bit to the other input.

If arranged in this way, the 4-bit output QI"Q4 will have 5 of 8 levels within 16 levels of 4 bits, similar to the circuit shown in Figure 3.
~C. Also, input 0110 from the most significant bit to the other input.
? When the input is input, the output Q is 6 to D, which is 8 levels within 116 levels.

In this way, if the DC offset is added digitally, the level of the DC offset will not change due to temperature changes. The above description has been made on the case where the input 3 bits are used as a 4 bit output, but by setting the input n bits as an output of fn+2 bits, it is possible to add a DC off-axis controller.

(f) Effects of the Invention As explained in detail above, according to the present invention, since the DC offset is added in a digital stage, there is no change in the DC offset level due to temperature changes, and stable carrier wave regeneration can be performed on the receiving side. There is an effect that can be done.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a transmission system of a conventional 64-value QAM system, Fig. 2 is a circuit diagram of a conventional DC offset addition circuit, and Fig. 3 is an input 3-bit t-center of an embodiment of the present invention. Figure 4 is a diagram showing the level relationship between the input 3 bits and output 4 bits of the circuit in Figure 3. The figure is a block diagram of a DC offset adding circuit using a full adder for converting input 3 bits into a 4-bit signal corresponding to an 8-value level shifted from the center of f, according to another embodiment of the present invention. In the figure, 1 is a serial-parallel converter, 2 is an encoder, 3 and 4 are digital Φ analog converters, 5 and 6 are low-frequency waveformers, 7 is an adder, 8 is a DC offset source, 9° and 10 are mixers. , 11 is a π/2 phase shifter, 12 is a /% hybrid circuit, 13 is a summing amplifier, 14.20 is an AND circuit, 15.17 is an OR circuit, 16 is a NOR circuit, 18.221'i inverter circuit ,
19 is a NAND circuit, 21 is an exclusive OR circuit, and 23 is a full adder.

Claims (1)

[Claims] In the DC offset addition method in which a DC offset is added to one of the two n-bit multi-value orthogonal signals to cause carrier wave leakage in the multi-value quadrature amplitude modulation communication system, the n-bit multi-value orthogonal signal is A DC offset (DC offset) addition method characterized in that, before digital-to-analog conversion, a DC offset is added by means of converting the signal into an n+2 bit signal corresponding to a 2n multi-value level with a shifted center.