KR0153011B1 - Modulator - Google Patents

Abstract

The objective is to provide a modulator with low power consumption and few adjustment points, the configuration of which is a delta sigma modulator that converts the modulated signal Mo into a binary signal such that a part of the frequency components after the signal conversion is a desired analog signal. (1) and a multiplication circuit (2) for inputting the binary signal (D1) and the carrier signal (Ca) output from the delta sigma modulator (1) and outputting the product of the carrier signal (Ca) and the binary signal (D1). It is provided.

According to the present invention, since the modulator can be configured with a switching circuit of the same circuit scale as the analog circuit, it is possible to realize a modulator with high power consumption with low power consumption.

Description

Modulator

1 is a block diagram showing the configuration of an amplitude modulator as a first embodiment of the present invention.

2 is a block diagram showing a configuration of an orthogonal modulator as a second embodiment of the present invention.

3 is a block diagram showing a configuration of an orthogonal modulator as a third embodiment of the present invention.

4 is a circuit diagram showing an example of the configuration of a selector of the third embodiment.

5 is a block diagram showing an orthogonal modulator of the fourth embodiment.

6 is a configuration example of a circuit for realizing the logic expression 3. FIG.

7 is a block diagram showing a configuration of an orthogonal modulator of a fifth embodiment of the present invention.

8 is a timing chart showing an input / output relationship of the switch of the fifth embodiment.

9 is a block diagram showing a configuration of an orthogonal modulator of the sixth embodiment.

10 is a circuit diagram showing an example of the configuration of the signal conversion circuit of the sixth embodiment.

Fig. 11 is a circuit diagram showing an example of the configuration of the phase changer of the sixth embodiment.

12 is a block diagram showing a configuration of an amplitude phase modulator according to the seventh embodiment.

FIG. 13 is a diagram for explaining the output of the selector shown in FIG.

FIG. 14 is a block diagram showing the configuration of a vector delta sigma modulator of the amplitude phase modulator shown in FIG.

FIG. 15 is a diagram for explaining the output of the encoder shown in FIG. 14. FIG.

FIG. 16 is a diagram for explaining the output of the vector player shown in FIG.

17 is a result of calculating the spectrum of the output signal of the amplitude phase modulator of the fifth embodiment of the present invention by computer simulation.

18 is a result of calculating the spectrum of the output signal of the amplitude phase modulator of the seventh embodiment of the present invention by computer simulation.

19 is a block diagram showing a configuration of an amplitude phase modulator according to the eighth embodiment.

FIG. 20 illustrates the output of the selector shown in FIG. 19. FIG.

21 is a diagram for explaining the output of an encoder in the eighth embodiment.

Fig. 22 is a table showing the input / output relationship of the vector player in the eighth embodiment.

23 is a diagram for explaining a ninth embodiment of the present invention.

FIG. 24 is a diagram for explaining the output of the selector shown in FIG.

25 is a block diagram showing the configuration of a transmitter using a delta sigma quadrature modulator of the present embodiment.

FIG. 26 is a block diagram showing the configuration of a transmitter using the delta sigma quadrature modulator of this embodiment. FIG.

FIG. 27 is a block diagram showing the configuration of a transmitter using the delta sigma quadrature modulator of this embodiment. FIG.

28 is a waveform diagram for explaining the output power control method according to the present invention.

29 is a circuit diagram of a class-D amplifier to which the output power control method according to the present invention is applied.

30 is a block diagram showing a configuration of an example of a conventional quadrature modulator.

* Explanation of symbols for main parts of the drawings

1,7,8,13,14: Delta Sigma Modulator

2,9,10: Multiplication circuit 3,11: Ideal phase

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to modulators used for amplitude modulation, amplitude phase modulation, and the like, and more particularly to modulators suitable for integrated circuits.

Portable telephones and the like are becoming widespread, but in such wireless devices, miniaturization and low power consumption are very important factors. With such a situation, miniaturization and low power consumption are demanded for the modulation / demodulation circuit.

30 is a block diagram showing a configuration of an example of a conventional quadrature modulator.

This quadrature modulator includes D / A converters 71 and 72 for converting two series of digitally given modulation signals into analog modulated signals, and a low pass filter 73 for removing sampling noise included in the output of each D / A converter. 74, a synthesizer 79 for generating a local signal, a π / 2 idealizer 80 for π / 2 or more the frequency of a local signal output from the synthesizer 79, and a low pass filter ( A mixer 77 for amplitude modulating the output of the phase shifter 80 at the output of 73; a mixer 78 for amplitude modulating the output of the synthesizer 79 at the output of the low pass filter 74; and an output of each mixer. Is basically composed of a synthesizer 81 which outputs an amplitude phase modulated wave. The mixers 77 and 78 can also use amplitude modulators.

Since this kind of quadrature modulator is analog signal processing after the D / A converters 71 and 72, various kinds of errors and distortions are generated. In general, in order to reduce the distortion, a sufficiently large bias current is required for the signal, and the current consumption is large. This problem is common even when the mixer is used as an amplitude modulator. In addition, in the quadrature modulator, there is a problem in that the circuit scale becomes large, for example, a correction circuit for correcting an error, a correction signal generating circuit, or the like is required for high precision modulation. On the other hand, as a high precision orthogonal modulator, as shown in the Japanese Society for Electronics and Telecommunications Fall Conference, B-239, a method of digitally constructing a signal has also been proposed. Multi-bit digital signals must be processed at high speed, and the circuit size is large and power consumption is large, so it is not suitable for portable wireless terminals.

As described above, the conventional amplitude modulator or quadrature modulator requires a sufficiently large bias current to accompany analog signal processing, resulting in a large current consumption. In the digital modulator, in order to improve precision, a multi-bit There is a problem that the digital signal must be processed at high speed, and the circuit size is increased and power consumption is also increased.

The present invention has been made in view of such a problem, and an object thereof is to provide a modulator with low power consumption and few adjustment points.

In order to achieve the above object, the first invention of the present application provides a signal conversion means for converting a modulated signal into a binary or trivalue signal, and inputs a binary or trivalue signal and a carrier signal output from the signal conversion means. And multiplication means for outputting a product of the carrier signal and the binary or trivalue signal.

The second invention of the present application is an abnormal means for converting an input signal into a first carrier signal and a second carrier signal having a phase different from each other by 90 °, and a first signal conversion for converting the first modulated signal into a binary or trivalue signal. Means; first multiplication means for inputting a binary or trivalue signal and the first carrier signal output from the first signal conversion means, and outputting a product of the first carrier signal and the binary or trivalue signal; Second signal converting means for converting a second modulated signal into a binary or trivalue signal, a binary or trivalue signal output from the second signal converting means and the second carrier signal, and inputting the second carrier signal. Second multiplication means for outputting the product of the carrier signal and the binary or trivalue signal, and combining means for combining the outputs of the first multiplication means and the second multiplication means to output an amplitude phase modulated wave.

The third invention of the present application includes signal conversion means for converting a modulation signal into a selection signal according to the modulation signal, and selection means for selecting one of the signals having the same frequency and different phases or amplitudes as an output according to the selection signal. .

The fourth invention of the present application is a first signal converting means for converting the first modulated signal into a binary first selection signal by the signal converting means in the modulator of the third invention, and the second modulated signal of the second modulated signal. And a second signal converting means for converting into?, Wherein the selecting means selects one of four kinds of signals having the same frequency and different phases from each other by 90 ° according to the first and second selection signals as an amplitude phase modulated signal. do.

In the fifth aspect of the present invention, in the modulator of the third aspect of the present invention, a linear converter for linearly converting the input vector using a signal conversion means as a plurality of modulated signals and a plurality of feedback signals and a vector of the linearly transformed vector An encoder for encoding by quantization and outputting as a selection signal and a vector player for combining the encoded output as the plurality of feedback signals.

In the present invention, a D / A converter of a conventional quadrature modulator is conversion means for converting a modulated signal into a binary signal.

The output of the converting means is a switching signal which takes a binary value of 1 and -1, for example, 1, -1, 1, -1,. When outputting a series, the average of the output is 0. 1, 1, -1, 1, 1, -1,... If you output the series, average the output, you can assume that 1/3 output.

As such, there is a delta sigma modulator as one of conversion means for outputting a binary signal series so that the average of the signal series becomes a desired analog signal.

The process of averaging the signal sequence of the modulation means can be realized by passing the signal through a low pass filter. In other words, when the output signal sequence of the converting means is viewed in the frequency domain, unnecessary signal components such as quantization noise are small in the low frequency band where the desired signal exists and are distributed in the high frequency band so that only the low frequency component is removed by the filter to remove the desired signal component. You can get it.

In the present invention, it is basic to obtain an amplitude modulated signal by multiplying a binary signal series that causes the average of the signal series to be a desired analog signal and a carrier signal. That is, by means of outputting cosωt when the output of the modulation means is 1 and outputting -cosωt when the output of the modulation means is -1, 1, 1, -1, 1, 1, -1,... When you enter, you get an output that averages 1/3 cosωt. The averaging process in this case corresponds to passing through a bandpass filter in which the center angle frequency of the signal is ω.

The above-described signal processing is performed on orthogonal two components to realize orthogonal modulation. That is, orthogonal modulation is realized by means for outputting cosωt, -cosωt, sinωt, and -sinωt in accordance with the output of the binary values of the first and second conversion means, respectively.

The output signal contains quantization noise or harmonic components in addition to the desired signal, but the desired signal component is in the vicinity of the carrier frequency and the unwanted signal component is distributed in the band relatively away from the carrier frequency.

In the case of the conventional analog system, an analog multiplication circuit is required. However, in the present invention, since the amplitude of the modulated signal, the carrier signal, and the modulated signal is constant, the switching circuit can be used to perform multiplication or quadrature signal processing. Can be. In addition, since the switching signal can easily avoid the problem of amplitude error and distortion as compared with an analog circuit, a high-precision amplitude modulation or quadrature modulator can be realized by using a signal having a small error on the time axis.

In an analog circuit, a signal with a large amplitude is required to reduce the influence of noise, and a bias current larger than the amplitude of the signal must be flowed to reduce the distortion. On the other hand, since the switching circuit can reduce the bias current within the range that can guarantee the operation speed of the circuit, and the present invention is realized by 1-bit signal processing, the circuit scale becomes the same as that of the analog circuit, and the current consumption is reduced. can do.

Delta sigma modulation has a multi-value output of three or more values for the purpose of reducing quantization noise. In order to use this quadrature modulator, for example, in the case of 3 values or more, when -1, 0, 1 is mapped to -cosωt, 0, cosωt, an amplitude modulated signal is obtained as in the case of the binary value. As described above, in the case of three or more values, an amplitude modulator or an orthogonal modulator can be configured similarly to the case of two values. In the case of only 3 values, it can be realized on the same circuit scale as in the case of 2 values. However, as the value is increased, the quantization noise becomes smaller, but the circuit size increases, resulting in increased error and power consumption. .

As described above, according to the present invention, part or all of the amplitude modulator and the quadrature modulator can be constituted by a switching circuit, so that the influence of the modulation error due to the nonuniformity of the element values which is a problem in the analog circuit can be avoided. In addition, since only 1-bit signal is basically handled, the circuit size is smaller than that of the conventional digital modulator, and the switching circuit does not have the same distortion problem as the analog circuit, thereby achieving low power consumption in a range in which switching operation speed does not become a problem. can do. And cosωt, cosωt, -cosωt,... In the same way as to obtain 1/3 cos omega t by averaging outputs, cos omega t, cos (omega t + ψ), cos omega t, cos (omega t + ψ),... Is averaged, 1 / 2cosωt + 1 / 2cos (ωt + ψ) = sin (ψ / 2) cos (ωt + ψ / 2).

In order to obtain a desired signal in this manner, it is not necessary to necessarily refer to a signal having a phase difference of 90 °, and amplitude phase modulation can be realized by switching a signal having a phase difference of 120 ° such as, for example, three-phase alternating current. In this case, it is necessary to switch signals so that a part of the frequency components is a desired signal and quantization noise is distributed in a frequency band far from the frequency band of the desired wave. Generating such a switching signal is a vector delta sigma modulator. The output of an amplitude phase modulator using two sets of delta sigma modulators had to be a signal having the same amplitude and 90 ° in phase with each other. However, by using vector delta sigma modulation, an output of any combination of amplitude and phase can be obtained. have. In addition, since the loop filter of the delta sigma modulator handles a scalar signal, the transfer function can be realized only with the rational function of the real coefficient. Therefore, the distribution of the quantization noise of the output of the amplitude phase modulator using this becomes symmetrical with respect to the carrier frequency. On the other hand, when the vector delta sigma modulator is used, the loop filter of the delta sigma modulator is a linear modulator, and apparently, a transfer function of a complex coefficient can be realized. Therefore, the distribution of the quantization noise of the output of the amplitude phase modulator using this can be made asymmetrical with respect to a carrier frequency. For example, in a wireless system that is strictly limited in unwanted radiated power from 900 MHz to 910 MHz, when transmitting a signal having a center frequency of 901 MHz, and using a sigma modulator, the distribution of quantization noise is determined relative to the center frequency. Since it is symmetric, a delta sigma modulator must be designed to reduce quantization noise in the range of 892 MHz to 910 MHz. On the other hand, since the vector delta sigma modulator can make the distribution of quantum noise asymmetric, it is designed to reduce the quantization noise from 900MHz to 910MHz. In other words, in order to reduce noise over a wide frequency range, it is necessary to increase the sampling frequency, but in general, a circuit operating at high speed consumes much more power. On the other hand, vector delta sigma modulation has a large degree of freedom in designing the frequency characteristic of quantization noise and can lower the sampling frequency, thereby reducing power consumption.

An embodiment of the present invention will be described below with reference to the drawings.

1 is a block diagram showing the configuration of an amplitude modulator as a first embodiment of the present invention. Modulated signal Mo, given digitally or analog, is converted into binary signal D1 by delta sigma modulator 1. The signal D1 and the carrier signal Ca are input to the multiplication circuit 2, and the carrier signal Ca is switched to the normal or reverse phase by the signal D1, and the amplitude modulated wave ( Output as A1). As the multiplication circuit 2, an analog multiplication circuit such as a Gilbert multiplication circuit or a diode ring modulation circuit may be used, but an exclusive OR circuit may be used. Even when an analog multiplication circuit is used, the amplitude of the input / output signal is constant, so it does not need to be linear as in the conventional amplitude modulation circuit.

When three values are used for the delta sigma modulator 1, the output of the multiplication circuit 2 is one of a normal output, no output, and a reversed phase output. As the multiplication circuit 2, an analog multiplication circuit or a three-value logic circuit is used.

The delta sigma modulator 1 of FIG. 1 may be replaced with another conversion circuit that outputs a binary or trivalue signal sequence whose average value of the output signal sequence is a desired analog signal. For example, it can be replaced by a pulse width modulator (PWM) or other pulse density modulator used in a switching regulator. In particular, in the case of transmitting a digital signal, a memory can be used as a conversion circuit, a memory address can be provided as a modulated signal, and a circuit that obtains a binary signal sequence as an output can be realized. The output of the amplitude modulator 1 is a signal having a constant amplitude by superimposing an unwanted signal such as quantization noise on a desired signal when viewed on the time axis. When the signal is viewed on the frequency axis, a desired signal component is present near the carrier frequency, and an unnecessary signal component is distributed near the carrier frequency and distributed in a frequency band relatively far from the carrier frequency. Thus, by removing the unwanted signal components with a filter, a desired amplitude modulated signal can be obtained.

2 is a block diagram showing the configuration of a quadrature modulator as a second embodiment of the present invention. The local oscillation signal Lo is input to the phase shifter 3 to obtain a carrier signal Ca1 and a carrier signal Ca2 having phases different from each other by 90 degrees. The modulated signals Mo1 and Mo2 and the carrier signals Ca1 and Ca2 are respectively input to the amplitude modulators 4 and 5 having the same configuration as the amplitude modulator described in the first embodiment to obtain the amplitude modulated signals A1 and A2. This is synthesized by the analog signal synthesizer 6 to output an amplitude phase modulated signal AP. 7, 8 denote delta sigma modulators, and 9 and 10 denote multiplier circuits, respectively.

3 is a block diagram showing the configuration of a quadrature modulator as a third embodiment of the present invention. The local oscillation signal Lo is input to the phase shifter 11 and divided into four carrier signals Ca1, Ca2, Ca3, Ca4 having phases of 0 °, 90 °, 180 °, and 270 °, respectively, to the selector 12. Is entered. On the other hand, the outputs D1 and D2 of the two delta sigma modulators 13 and 14 are also input to the selection means 12. The two delta sigma modulators 13 and 14 can be replaced with other conversion circuits that output binary signal sequences so that the average of the output signal sequences described in the first embodiment becomes a desired analog signal.

The selector 12 selects and outputs one of four input signals Ca1, Ca2, Ca3, and Ca4 according to the two input signals D1 and D2. For example, Ca1 when (D1, D2) is (1,1), Ca2 when (1, -1), Ca3 when (-1, -1), (-1,1) In the case of), Ca4 is output to obtain the same amplitude phase modulated signal as in the second embodiment. This amplitude phase modulation output also has an unwanted signal component such as quantization noise superimposed on a desired signal component and its amplitude is also constant. The desired amplitude phase modulated signal can be obtained by removing unwanted signal components distributed in a frequency band relatively far from the carrier frequency in the filter.

4 is a circuit diagram showing an example of the configuration of the selector 12 of the third embodiment. Normally, logic circuits are represented by binary values of 1 and 0, but are described here as binary values of 1 and -1. Ca1 when (D1, D2) is (1,1), Ca2 when (1, -1), Ca3 when (-1, -1), Ca4 when (-1,1) It can be expressed as the formula 1 if the expression.

[Logic 1]

When the logical formula 1 is transformed by the D'Morian theorem, the logical formula 2 is obtained.

[Logical 2]

The logic circuit of FIG. 4 realizes the logic formula 2.

The NAND circuit outputs -1 only when all inputs are one. In Fig. 4, when (D1, D2) is (1, 1), the three-input NAND circuit 15 to which Ca1 is input outputs an inverted signal of Ca1. Since at least one -1 is input to the other three-input NAND circuits 16, 17, and 18, the output is necessarily one. Therefore, the four-input NAND circuit 19 outputs the inverted signal of the inverted signal of Ca1, that is, Ca1. Similarly, Ca2 is selected when (D1, D2) is (1, -1), Ca3 is selected when (-1, -1), and Ca4 is selected when (-1,1) is output.

5 is a block diagram showing an orthogonal modulator of a fourth embodiment of the present invention.

The carrier signal is inputted to the abnormality means 20, divided into two signals of 0 ° and 90 ° and input to the selector 21. On the other hand, the outputs D1 and D2 of the two delta sigma modulators 23 and 24 are also input to the selector 21. As described above, the delta sigma modulators 23 and 24 can be replaced by another conversion circuit that outputs a binary signal series whose average of the output signal series becomes a desired analog signal.

The selector 21 selects and outputs one of the input signals Ca1 and Ca2 and its inverted signal according to the two input signals D1 and D2. For example, Ca1 when D1 and D2 are (1,1), Ca2 when (1, -1), and Ca1 inversion signal when (-1, -1) is (-1,1) Outputs a reverse signal of Ca2. If this is represented by an expression, it will become logical formula 3.

[Logic 3]

6 is a configuration example of a circuit for realizing the logic formula 3, and is composed of three-input AND circuits 25 to 28, four-input OR circuits 29, and the like. The output is the same as in the third embodiment of the present invention.

7 is a block diagram showing a configuration of an orthogonal modulator of a fifth embodiment of the present invention.

The outputs D1 and D2 of the two delta sigma modulators 30 and 31 and their inverted signals D3 and D4 by the inverters 32 and 33 are input to the switch 34. The switch 34 inputs a clock signal four times the carrier frequency and sequentially selects and outputs D1, D4, D3, and D2 for each clock. As a result, as shown in FIG. 8, when (D1, D2) is (1,1), 1, -1, -1, 1 is (1, -1) in the order of D1, D4, D3, and D2. 1, 1, -1, -1 for (-1, -1), -1, 1, 1, -1 for (-1, -1), -1, -1, 1 for (-1,1) Repeatedly print 1 Thus, the same output as in the above embodiment is obtained.

Similarly, even when D1 and D2 are three values of -1, 0, and 1, the quadrature modulator can be realized by sequentially selecting and outputting D1 and D2 and their sign inversion signals D3 and D4 according to the clock signal.

9 is a block diagram showing the configuration of an orthogonal modulator of a sixth embodiment of the present invention.

The outputs D1 and D2 of the two delta sigma modulators 35 and 36 are converted by the signal converter 37 into control signals P1 and P2 of the phase changer. On the other hand, the local outgoing signal Ca is input to the 180 ° phase switch 38 and output in phase of 0 ° or 180 ° according to the control signal P1. The output of the 180 ° phase switch 38 is input to the 90 ° phase switch 39 and output in phase of 0 ° or 90 ° according to the control signal P2. As a result, the output is the same as in the third embodiment of the present invention. The 180 ° phase switch 38 and the 90 ° phase switch 39 can obtain the same output even if their order is changed.

FIG. 10 is a circuit diagram showing an example of the configuration of the signal converter 37 of the sixth embodiment of the present invention, and is composed of an exclusive OR circuit 40. As shown in FIG.

If the phase changer outputs 0 ° when P1 and P2 are 1, the output is 0 ° when (D1, D2) is (1,1), and 90 ° when (1, -1), and (-1 And -1) to 180 °, and to (-1,1) to 270 °.

11 is a circuit diagram showing an example of the configuration of the phase changer of the sixth embodiment of the present invention. A signal whose phase is delayed by 90 ° or 180 ° depending on the length of the delay circuit 42 when an output of 0 ° is opened by the control signal when the input / output is shorted by the switch 41 by the control signal P1. Outputs

12 is a block diagram showing the configuration of an amplitude phase modulator as a seventh embodiment of the present invention. The modulated signals I and Q are converted by the vector delta sigma modulator 43 into symbol strings represented by five symbols of a, b, c, d, and e, and are input to the selector 44 as a selection signal. When the selection signal a is input to the selector 44, the selector 44 outputs a signal corresponding to the point indicated by a on the phase plan view shown in FIG. Similarly, when the selection signals b, c, d and e are input to the selector 44, the selector 44 outputs signals corresponding to the points b, c, d and e on the phase plan shown in FIG. do.

The selector 44 inputs a reference signal of frequency 4f four times the desired output frequency and generates four signals indicated by a to d on the phase plan of FIG. 13 by a divider circuit (not shown). do. e corresponds to the state of stopping the output. In this way, the output of the selector 44 is composed of four signals having the same amplitude and different phases and five states of stopping the output.

FIG. 14 is a block diagram showing the configuration of the vector delta sigma modulator 43 of the amplitude phase modulator shown in FIG. The encoder 45 depends on which area of five of a, b, c, d, and e on the coordinate plane shown in FIG. 15 is included in the coordinate (X, Y) indicated by the two scalar inputs of the encoder 45. ) Prints the corresponding sign.

The output of the encoder 45 is output as an output signal (selection signal) of the vector delta sigma modulator 43 and input to the vector player 46. The vector player 46 outputs the coordinates on the phase plane of the output of the selector 44. The coordinates of each point on the phase plane of FIG. 13 can be expressed as shown in the table of FIG. This table shows the input / output relationship of the vector player 46.

The input / output relationship of the linear transducer 47 is generally

[Equation 1]

Can be displayed as: Each element of the transformation matrix

[Equation 2]

In this manner, the same amplitude phase modulated waves as in the third to sixth embodiments can be obtained. However, in the third to sixth embodiments, the output of e corresponding to the origin on the phase plane cannot be selected. Therefore, in the seventh embodiment in which the output of e can be selected, the quantization noise is reduced by that much.

In the third to sixth embodiments, the frequency characteristic of the quantization noise is symmetrical with respect to the carrier frequency, but in the vector delta sigma modulator, the asymmetric frequency characteristic with respect to the carrier frequency can be obtained by the characteristic of the linear converter.

17 is a result obtained by calculating a spectrum of the output signal of the amplitude phase modulator of the fifth embodiment of the present invention by computer simulation. The modulation frequency of 4Hz is applied to the carrier frequency of 4096Hz to output 4100Hz. Delta sigma modulators 30 and 31 have a second order loop filter with a pole of about 100 Hz. This filter only allows real coefficients, so the pole must be on the real axis or else it must be a complex conjugate. The spectrum of quantization noise is minimal at 3996 Hz and 4192 Hz, ± 100 Hz from the carrier frequency.

18 is a result obtained by calculating a spectrum of an output signal of the amplitude phase modulator of the seventh embodiment by computer simulation. Although the carrier frequency and the modulated signal are the same as those in FIG. 17, since the vector delta sigma modulator is used, the complex coefficient filter in the linear converter 47 can be realized. The complex coefficient filter can determine the placement of the poles without the requirement of complex airspace. In this case, poles were placed at 10 Hz and -200 Hz. As a result, there are minima of quantization noise at 3896Hz and 4106Hz.

19 is a block diagram showing the configuration of an amplitude phase modulator as an eighth embodiment of the present invention. The reference signal input to the selector 48 is three times the frequency f of the desired output signal and divides this signal into three to generate signals that are 120 degrees out of phase with each other.

The modulated signals I and Q are converted into symbol strings represented by three symbols a, b, and c by the vector delta sigma modulator 49, and are input to the selector 48 as a selection signal. For input of the selection signals a, b and c, the selector 48 outputs signals corresponding to the points indicated by a, b and c on the phase plane shown in FIG. 20, respectively. In this case as well, since only signals with the same amplitude are handled, the selector can be configured by a switching circuit.

The vector delta sigma modulator 49 shown in FIG. 19 is the same as that shown in FIG. However, the encoder 45 outputs a corresponding code depending on which area among the three areas of a, b, and c on the coordinate plane shown in FIG. 21 is included in the coordinates indicated by the two scalar inputs. . The input / output relationship of the vector player 46 is as shown in the table shown in FIG. The input / output relationship of the linear transducer 47 may also be expressed as in Equation 1. When each element of the conversion matrix is represented by Equation 2, an amplitude phase modulated wave can be obtained as in the case of using two sets of conventional sigma delta converters. In this case, since there are only three points of output, the quantization noise is increased, but the frequency of four times the desired wave is not required, and the correct modulation signal can be obtained by three times the frequency.

23 is a diagram for explaining a ninth embodiment of the present invention. This embodiment applies the present invention as a frequency converter (inverter) which is mathematically equivalent to a modulator but mainly used for controlling power.

Three-phase alternating current is input to the selector 50 shown in this figure. The selection signals output from the vector delta sigma modulator 51 are three types: a, b, and c. When the selection signal (a) is input, the input (I) is connected to the output (1), the input (II) is connected to the output (2), and the input (III) is connected to the output (3), as shown in the table shown in FIG. do. When the selection signal (b) is input, input (I) is connected to output (2), input (II) to output (3), input (III) to output (1), and selection signal (c) When input, the input I is connected to the output 3, the input II to the output 1, and the input III to the output 2.

For example, a power input of 60 Hz is converted to 50 Hz to supply power. For example, a vector delta sigma modulator 51 receives a sinusoidal signal having a frequency of 10 Hz and a 90 ° phase shift from each other.

The configuration of the vector delta sigma modulator 51 is the same as that of the eighth embodiment. The output frequency is 10 Hz lower than the input frequency (60 Hz).

Therefore, when the vector delta sigma modulator 51 is designed such that the frequency characteristic of the linear modulator 47 is the lowest in quantization noise at 10 Hz, the minimum point of the quantization noise can be placed at 50 Hz instead of at 70 Hz.

25 is a block diagram showing the configuration of a transmitter using the delta sigma quadrature modulator of this embodiment.

As shown in this figure, the output from the delta sigma modulator 52 is removed by the band pass filter 53 to remove signals outside the desired band. The output from the band pass filter 53 and the local oscillation signal are mixed in the mixer 54, and the signal passes through the band pass filter 55 to obtain a signal of a frequency to be transmitted. This signal is amplified and output by the linear amplifier 56.

26 is a block diagram showing another configuration of a transmitter using the delta sigma quadrature modulator of the present embodiment.

As shown in this figure, the output from the delta sigma quadrature modulator 57 is removed by a band pass filter 58 and a signal other than the desired band is removed, and amplified by the linear amplifier 59 and output.

27 is a block diagram showing another configuration of a transmitter using the delta sigma quadrature modulator of this embodiment.

As shown in this figure, the output from the delta sigma quadrature modulator 60 is nonlinearly amplified in the nonlinear amplifier 61. Since the output from the delta sigma quadrature modulator 60 is constant in amplitude, an efficient nonlinear amplifier 61 is used. After the nonlinear amplification by the nonlinear amplifier 61, only a predetermined band is selected and output from the band pass filter 62. In addition, control of the output power is required for wireless transmitters, especially mobile communication. In the conventional transmitter, output power control is performed using a variable gain amplifier or a variable attenuator. However, in the method of using a switching amplifier as an output means, it is necessary to use a different control method. One of them is amplitude phase modulation, and there is a method of reducing the amplitude of the modulation signal itself. In addition, as shown in FIG. 28, the output can be controlled by a method in which the input signal (output of the selector) is removed in accordance with the output power. That is, Fig. 28 (b) shows the output of the selector at full power, and when the output power is 1/2, the selector outputs only one half period as shown in Fig. 28 (b), and outputs the output. When the power is 1/4, as shown in Fig. 28 (c), the selector may be used to filter out only one quarter of the period. 29 is a conceptual diagram of a class D amplifier, but since the output of the amplifier is approximately proportional to the power supply voltage VDD, the efficiency is improved even when the output power is small by controlling the power supply voltage VDD with a high efficiency voltage control circuit such as a switching regulator. I can do it with a high amplifier.

As described above, according to the present invention, it is possible to realize a modulator having a high precision according to a digital circuit with low power consumption equivalent to or higher than that of an analog circuit.

In addition, since it is basically composed of a switching circuit (logical circuit), the control system can be configured with good affinity with a microcomputer and no interface circuit or simple interface circuit.

When vector delta sigma modulation is used, the degree of freedom in designing the frequency characteristics of quantization noise is increased, and the clock frequency can be lowered, thereby further reducing power consumption.

Therefore, the radio transmitter as a whole can be miniaturized by using the modulator according to the present invention.

Claims (9)

A delta sigma conversion means for converting a modulated signal into a three-value signal, and a multiplication signal for outputting a red signal of the carrier signal and the three-value signal by multiplying a three-value signal and a carrier signal output from the delta sigma conversion means. A modulator comprising means. Abnormal means for converting the input signal into a first carrier signal and a second carrier signal having a phase different from each other by 90 °, first delta sigma conversion means for converting the first modulated signal into a binary or trivalue signal, and a first A first multiplication means for multiplying and outputting a first binary or three-value signal output from the delta sigma conversion means and the first carrier signal, and a second for converting the second modulated signal to a second binary or three-value signal; Delta sigma conversion means, second multiplier means for multiplying and outputting a second binary or ternary signal output from the second delta sigma conversion means and the second carrier signal, the first multiplication means and the second And a synthesizing means for synthesizing the output of the multiplication means and outputting an amplitude phase modulated signal. Delta sigma conversion means for converting a modulated signal into a binary signal, and a multiplication means for outputting a product of the carrier signal and the binary signal by multiplying a binary signal and a carrier signal output from the delta sigma conversion means. And a signal value of the binary values is 1 and -1. Delta sigma conversion means for converting a modulated signal into a binary signal, and multiplication means for multiplying the binary signal with a carrier signal and changing a phase of a carrier signal to a normal phase or an opposite phase in accordance with the binary signal. Modulator characterized in that. 2. The modulator according to claim 1, wherein the three-valued signal values are 1, 0 and -1. The modulator according to claim 1, wherein said multiplication means is an analog multiplication circuit. 7. The modulator of claim 6 wherein the analog multiplication circuit is selected from the group consisting of a Gilbert multiplication circuit and a diode ring modulation circuit. 2. The modulator of claim 1 wherein the multiplication circuit is an exclusive OR circuit. 4. The modulator according to claim 3, wherein said multiplication means is an analog multiplication circuit.